JP2014225681A - ハニカムヘテロエピタキシーを含む半導体装置 - Google Patents
ハニカムヘテロエピタキシーを含む半導体装置 Download PDFInfo
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- JP2014225681A JP2014225681A JP2014143317A JP2014143317A JP2014225681A JP 2014225681 A JP2014225681 A JP 2014225681A JP 2014143317 A JP2014143317 A JP 2014143317A JP 2014143317 A JP2014143317 A JP 2014143317A JP 2014225681 A JP2014225681 A JP 2014225681A
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
Abstract
Description
102 ナノアイランド
200 シリコン基板
202 ゲート酸化層
204 チャネル小バンドギャップ層
206 アンドープワイドバンドギャップ層
208 p+ワイドバンドギャップ層
300、300’ トランジスタ
302 ナノアイランド
302’シリコン
304、304’ 面積
306、306’ ゲート
308、308’ オーミックコンタクト
Claims (12)
- 貫通する複数のナノサイズの開口であって、それぞれの該開口がシリコン基板に向かって延出し、かつ、該シリコン基板の表面を露出する溝を定義する複数個の該開口を有するマスクをシリコン基板上に定義するステップと、
前記定義ステップ後、前記シリコン基板のそれぞれの露出表面上のそれぞれの前記溝内に、酸化層、チャネル小バンドギャップ層、アンドープワイドバンドギャップ層、及び、ドープトワイドバンドギャップ層とを含み、それぞれのナノアイランドが作られた前記溝内に、本質的に無欠陥のナノアイランドを作成するステップと、
前記作成ステップ後、前記ナノアイランド上に、トランジスタを構成するステップと、
からなることを特徴とする方法。 - 前記作成ステップは、有機金属化学気相成長法(MOCVD)によってナノアイランドの選択的ヘテロエピタキシャル成長を実行するステップを含むことを特徴とする請求項1に記載の方法。
- 前記作成ステップは、ガスソース分子線エピタキシー(MBE)法によってナノアイランドの選択的ヘテロエピタキシャル成長を実行するステップを含むことを特徴とする請求項1に記載の方法。
- 前記開口は、それぞれ、六角形の形状をしていることを特徴とする請求項1に記載の方法。
- シリコン基板と、
前記シリコン基板の上面に配置され、貫通する複数のナノサイズの開口であって、それぞれの該開口がシリコン基板に向かって延出し、かつ、該シリコン基板の表面を露出する溝を定義する複数個の該開口を有するマスクと、
前記マスク開口を介して、前記シリコン基板のそれぞれの露出表面上のそれぞれの前記溝内に、酸化層、チャネル小バンドギャップ層、アンドープワイドバンドギャップ層、及び、ドープトワイドバンドギャップ層とを含み、それぞれのナノアイランドが作られ、前記溝内に作られた本質的に無欠陥のナノアイランドと、
前記ナノアイランド上に構成されたトランジスタと、
からなることを特徴とする半導体装置。 - 前記開口は、それぞれ、六角形の形状をしていることを特徴とする請求項5に記載の半導体装置。
- 前記ナノアイランドの厚さは、50nm以下であることを特徴とする請求項5に記載の半導体装置。
- 前記シリコン基板は(111)面方位を有することを特徴とする請求項5に記載の半導体装置。
- 前記マスクはハードマスクを含むことを特徴とする請求項5に記載の半導体装置。
- 貫通する複数のナノサイズの開口であって、それぞれの該開口がシリコン基板に向かって延出し、かつ、該シリコン基板の表面を露出する溝を定義する複数個の該開口を有するマスクをシリコン基板上に定義するステップと、
有機金属化学気相成長法(MOCVD)、及びガスソース分子線エピタキシー(MBE)法のうちの少なくとも一つを用いて、前記シリコン基板のそれぞれの露出表面上であって、酸化層、チャネル小バンドギャップ層、アンドープワイドバンドギャップ層、及び、ドープトワイドバンドギャップ層とを含み、それぞれのナノアイランドが作られた前記溝内に、本質的に無欠陥のナノアイランドの選択的ヘテロエピタキシャル成長を実行するステップと、前記ナノアイランド上にトランジスタを構成するステップと、
からなることを特徴とする方法。 - 前記構成ステップは、ゲート、側壁及びオーミックコンタクトを設置するステップを含むことを特徴とする請求項10に記載の方法。
- 前記開口は、それぞれ、六角形の形状をしていることを特徴とする請求項10に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/562,852 US20110068368A1 (en) | 2009-09-18 | 2009-09-18 | Semiconductor device comprising a honeycomb heteroepitaxy |
US12/562,852 | 2009-09-18 |
Related Parent Applications (1)
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JP2010203889A Division JP2011066410A (ja) | 2009-09-18 | 2010-09-13 | ハニカムヘテロエピタキシーを含む半導体装置 |
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JP2014225681A true JP2014225681A (ja) | 2014-12-04 |
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JP2010203889A Pending JP2011066410A (ja) | 2009-09-18 | 2010-09-13 | ハニカムヘテロエピタキシーを含む半導体装置 |
JP2014143317A Pending JP2014225681A (ja) | 2009-09-18 | 2014-07-11 | ハニカムヘテロエピタキシーを含む半導体装置 |
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JP2010203889A Pending JP2011066410A (ja) | 2009-09-18 | 2010-09-13 | ハニカムヘテロエピタキシーを含む半導体装置 |
Country Status (6)
Country | Link |
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US (1) | US20110068368A1 (ja) |
EP (1) | EP2299490A3 (ja) |
JP (2) | JP2011066410A (ja) |
KR (1) | KR101345897B1 (ja) |
CN (1) | CN102024759B (ja) |
TW (1) | TWI484564B (ja) |
Families Citing this family (1)
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US9450007B1 (en) | 2015-05-28 | 2016-09-20 | Stmicroelectronics S.R.L. | Integrated circuit with reflective material in trenches and related methods |
Citations (4)
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JP2003077844A (ja) * | 2001-09-03 | 2003-03-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2005011915A (ja) * | 2003-06-18 | 2005-01-13 | Hitachi Ltd | 半導体装置、半導体回路モジュールおよびその製造方法 |
JP2008546181A (ja) * | 2005-05-17 | 2008-12-18 | アンバーウェーブ システムズ コーポレイション | 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法 |
JP2009503871A (ja) * | 2005-07-26 | 2009-01-29 | アンバーウェーブ システムズ コーポレイション | 代替活性エリア材料の集積回路への組み込みのための解決策 |
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-
2009
- 2009-09-18 US US12/562,852 patent/US20110068368A1/en not_active Abandoned
- 2009-12-22 TW TW098144136A patent/TWI484564B/zh active
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2010
- 2010-01-20 CN CN201010004651XA patent/CN102024759B/zh active Active
- 2010-06-21 EP EP10006435.1A patent/EP2299490A3/en not_active Withdrawn
- 2010-06-29 KR KR1020100061926A patent/KR101345897B1/ko active IP Right Grant
- 2010-09-13 JP JP2010203889A patent/JP2011066410A/ja active Pending
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2014
- 2014-07-11 JP JP2014143317A patent/JP2014225681A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003077844A (ja) * | 2001-09-03 | 2003-03-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2005011915A (ja) * | 2003-06-18 | 2005-01-13 | Hitachi Ltd | 半導体装置、半導体回路モジュールおよびその製造方法 |
JP2008546181A (ja) * | 2005-05-17 | 2008-12-18 | アンバーウェーブ システムズ コーポレイション | 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法 |
JP2009503871A (ja) * | 2005-07-26 | 2009-01-29 | アンバーウェーブ システムズ コーポレイション | 代替活性エリア材料の集積回路への組み込みのための解決策 |
Also Published As
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EP2299490A2 (en) | 2011-03-23 |
KR101345897B1 (ko) | 2013-12-30 |
JP2011066410A (ja) | 2011-03-31 |
EP2299490A3 (en) | 2013-11-20 |
TW201112335A (en) | 2011-04-01 |
TWI484564B (zh) | 2015-05-11 |
US20110068368A1 (en) | 2011-03-24 |
CN102024759A (zh) | 2011-04-20 |
CN102024759B (zh) | 2013-05-29 |
KR20110031080A (ko) | 2011-03-24 |
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