CN102024759B - 半导体装置及其制造方法 - Google Patents
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Abstract
本发明提供一种半导体装置的制造方法,包括:在一硅基底上定义一掩模,该掩模包括多个穿过其中的纳米尺寸开口;在定义该掩模之后,在该硅基底穿过所述多个掩模开口而露出的表面部分建造实质上无缺陷的非硅半导体纳米岛;在建造所述多个纳米岛之后,在所述多个纳米岛上沉积高介电常数栅极电介质;以及在沉积该高介电常数栅极电介质之后,在所述多个纳米岛上架构晶体管。本发明的结构有益于热能的移除并有良好的平坦度,且相容于目前22纳米节点或低于22纳米节点的CMOS制造需求。
Description
技术领域
本发明涉及一种半导体装置及其制造方法。
背景技术
在最近几十年来,使用硅基材的互补型金属氧化物半导体(CMOS)技术在例如微处理器的数字电路中已占有主要地位。然而,当临界特征尺寸接近22纳米或更小时,更进一步的尺寸微缩化所造成的效能优势,似乎会受限于硅通道而被缩减。为了持续地提高效能,是使用例如砷化铟镓(indiumgallium arsenide;InGaAs)、锑砷化铟(indium arsenide antimonide;InAsSb)与锗(germanium;Ge)的迁移率高的材料,取代硅作为通道材料。然而,这样迁移率高的材料其结晶结构、晶格常数、热膨胀系数与其他参数并不相容于硅。此不相容性会造成降低材料特性、装置效能与电路合格率的缺陷。
这里说明两种不同公知的在晶格失配(lattice mismatch)系统的异质外延中减少缺陷密度的方法。一种方法是使用一般为三元或四元半导体的覆盖薄膜或缓冲层。缺陷(特别是穿透位错(threading dislocation))会被捕捉或终止在缓冲层中的某些区域。另一种方法是捕捉或终止图案化掩模侧壁上晶格失配所造成的缺陷,上述掩模一般包含电介质。在此方法中,外延晶格失配的材料是生长至一厚度,而横向地延伸在掩模上。一般而言,在上述两种方法中,穿透位错的密度会随着离基底表面的距离愈远而愈低。这种现有技术的缺点包括需要相当厚的缓冲层,而厚度一般是超过0.5μm至1μm,或者会在靠近表面的位置或当中留下密度相当高的穿透位错,而上述缺陷密度一般是介于105个/cm2至106个/cm2,或更高。此厚度的缓冲层不相容于CMOS的平坦度与工艺需求,且更不益于热能的移除,特别是一般的CMOS微处理器需要消散超过100瓦特至300瓦特的热能。此三元或四元材料的导热系数(heat conductivity)一般比硅差一个数量级或更多。
现有技术还揭示在硅基底上异质外延(heteroepitaxial)生长晶格失配(lattice mismatched)、无位错(dislocation-free)的纳米线。此纳米线的高度一般介于5μm至10μm。举例来说,虽然无位错的InAs纳米线能够生长至150nm(T.Martensson等人,Advanced Materials 2007,19,1801-1806),然而其一般是使用例如金或自组有机涂物(self-assembled organic coating)的成核模板(template),成核在未图案化的硅基底上,并生长至50nm。已有文献报导栅极环绕线结构的纳米线金属氧化物半导体场效应晶体管(nanowireMOSFET)(Q.T.Do等人,“High Transconductance MISFET with a SingleInAs Nanowire Channel,”Electron Device Letters,Vol.28,No.8,p.682(2007),以及C.Thelander等人“Vertical Enhancement-Mode InAs NanowireField-Effect Transistor with 50nm Wrap Gate,”Electron Device Letters,Vol.29,No.3,p.206(2008))。而纳米线MOSFET的缺点是,其非平面的结构并不相容于标准的CMOS技术。
现有技术也揭示浅沟槽隔离(shallow trench isolation;STI)工艺,其是在半导体装置工艺的前段、在形成晶体管之前进行。浅沟槽隔离工艺的主要步骤包括在硅基材中蚀刻沟槽图案;沉积例如二氧化硅的一或多个介电材料以填充沟槽;及使用例如化学机械研磨的技术移除多余的电介质。
发明内容
为了解决现有技术中存在的上述问题,本发明提供一种半导体装置的制造方法,包括:在一硅基底上定义一掩模,该掩模包括多个穿过其中的纳米尺寸开口;在定义该掩模之后,在该硅基底穿过所述多个掩模开口而露出的表面部分建造实质上无缺陷的非硅半导体纳米岛;在建造所述多个纳米岛之后,在所述多个纳米岛上沉积高介电常数栅极电介质;以及在沉积该高介电常数栅极电介质之后,在所述多个纳米岛上架构晶体管。
本发明也提供一种半导体装置,包括:一硅基底;一掩模,设置在该硅基底的顶表面上,并包括多个穿过其中的纳米尺寸开口;实质上无缺陷的非硅半导体纳米岛,生长在该硅基底穿过所述多个掩模开口而露出的顶表面部分;高介电常数栅极电介质,设置在所述多个纳米岛上;以及晶体管,形成在所述多个纳米岛上。
本发明还提供一种半导体装置的制造方法,包括:在一硅基底上定义一掩模,该掩模包括多个穿过其中的纳米尺寸开口;使用金属有机化学气相沉积法与气相源分子束外延法中的至少一个方法,在该硅基底穿过所述多个掩模开口而露出的表面进行实质上无缺陷的非硅半导体纳米岛的选择性的异质外延生长;在建造所述多个纳米岛之后,借由金属有机化学气相沉积法、原子层沉积法与分子束外延法中的至少一个方法,在所述多个纳米岛上沉积高介电常数栅极电介质;以及在沉积该高介电常数栅极电介质之后,在所述多个纳米岛上架构晶体管。
本发明的结构有益于热能的移除并有良好的平坦度,且相容于目前22纳米节点或低于22纳米节点的CMOS制造需求。
附图说明
图1显示一实施例设置在硅基底上的硬掩模与形成于硬掩模中的纳米岛;
图2显示一实施例用来形成n型沟道MOSFET的纳米岛的外延层结构;
图3A显示一实施例形成在纳米岛上的晶体管;
图3B显示现有技术形成在一般材料上的晶体管;
图4显示一实施例在基底上形成无位错、薄的异质外延、单晶的纳米岛的方法流程图;
图5显示各种逻辑栅极单元的历史与预计尺寸的曲线图。
主要元件符号说明
100~掩模;102~纳米岛;200~硅基底;202~栅极氧化层;204~小能隙通道层;206~未掺杂的大能隙层;208~p+型大能隙层;300~晶体管;300′~晶体管;302~纳米岛;302′~一般的硅材料;304~区域;304′~区域;306~栅极;306′~栅极;308~欧姆接触;308′~欧姆接触。
具体实施方式
以下是通过附图说明本发明的概念。要强调的是,图中的各种元件并未画成与工业标准规范相符的比例。实际上,为了清楚地描述本发明,各种元件的尺寸可任意地放大或缩小。
在此说明的实施例提供一种相容于CMOS需求的少缺陷(low-defect)或无缺陷(defect-free)的异质外延方法,其形成的结构包括、但不限于,有益于热能的移除并有良好的平坦度,且相容于目前22纳米节点或低于22纳米节点的CMOS制造需求。详细地说,在此说明的实施例是在硅基底上提供单晶材料的无位错异质外延纳米岛(dislocation-free heteroepitaxialnano-island)。架构在纳米岛上的晶体管相容于CMOS制造需求;详细地说,上述结构是平坦的,薄的装置层能益于热能的移除,且需求的面积相同于如国际半导体技术蓝图(International Technology Roadmap for Semiconductors;ITRS)中所述的标准硅CMOS。此外,用来在硅基底上建造纳米岛的掩模也同时用来电性隔离各个装置。
请参考图1,可包括例如电介质的硬掩模100是用来在硅基底200(参考图2)上建造无位错、薄的异质外延、单晶的纳米岛102,如参照图4的说明。纳米岛102可解释为只包含装置功能需要的薄层厚度的终止纳米线。在一实施例中,纳米岛102的总厚度不超过50nm。如图2中所示,纳米岛102可根据装置的需求而包括一些异质外延层。详细地说,图2显示单一个纳米岛102的n型沟道MOSFET层结构,其包括栅极氧化层202、小能隙通道层204、未掺杂的大能隙层206与p+型大能隙层208。每个纳米岛102上可制得一或更多个晶体管,或者可将纳米岛合并以形成较大的晶体管。纳米岛102的尺寸相似于一般纳米线的剖面尺寸,且纳米岛102尺寸的上限取决于无位错生长的限制。
由于纳米线一般是以横剖面为六角形(hexagonal)的结构生长,因此在一实施例中,用来促进无位错的生长的硬掩模100包括六角形的开口(hexagonally-shaped opening)(因此也可称之为“蜂巢孔(honeycomb)”)。硅基底200可更具有(111)表面方向,以促进无位错的生长。可设计硬掩模100,让使用纳米岛架构的晶体管所需要的面积等于一特定节点的标准CMOS硅晶体管,如图3A与图3B所示。详细地说,图3A显示一实施例架构在纳米岛302上的晶体管300。图3B显示现有技术架构在一般的材料上,在此例子中,是形成在硅材料302′上的晶体管300′。在图3A中,区域304表示硬掩模与隔离物。在图3B中,区域304′表示浅沟槽隔离结构与隔离物。每个晶体管300、300′分别包括栅极306、306′与欧姆接触308、308′。从图3A与图3B的比较可发现,如上所述,晶体管300的面积实质上等于晶体管300′的面积。
图4显示一实施例在基底上建造无位错、薄的异质外延、单晶的纳米岛的方法流程图。请参考图4,在步骤400中,掩模是借由例如热氧化法、氧化沉积法及/或微影法定义在硅基底上。如参照图1所述的内容,在步骤400中定义的掩模为硬掩模。在步骤402中,借由例如金属有机化学气相沉积法及/或气相源分子束外延法,在露出的硅表面进行非硅半导体纳米岛的选择性的异质外延生长。在步骤404中,高介电常数栅极电介质是借由例如金属有机化学气相沉积法、原子层沉积法及/或分子束外延法沉积。最后,在步骤406中,在纳米岛上架构晶体管的栅极、侧壁与欧姆接触。
非硅通道材料,例如III-V族半导体与锗(Ge),可应用于超过22纳米世代的CMOS。一般此技术的晶体管面积是小于20,000nm2。图5显示嵌入式微处理器(MPU)栅极尺寸(四个晶体管(4t))的历史与预计的尺寸曲线图。举例来说,包括隔离结构的单一个晶体管,在16纳米节点与11纳米节点(节点在此是以嵌入式微处理器/专用集成电路第一层金属1/2间距(MPU/ASIC metal 1(M1)1/2pitch)定义)的预计尺寸为约20,000nm2与约10,000nm2,分别如图中的点500与点501所示。此说明是假设晶体管单元包括隔离结构且占有正方形面积时,晶体管单元的边缘长度为140nm与100nm。要注意由于异质外延材料的纳米岛是建造在隔离掩模图案中,因此上述纳米岛仍是非常小的。目前已证实能在此尺寸的硅基底上形成无位错的InAs纳米线。
虽然本发明已以较佳实施例揭示如上,然而其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可做些许改变与润饰。举例来说,所述方法的各种步骤可以不同的顺序或连续地执行,或与其他步骤合并、甚至分割成其他步骤或以其他步骤取代,或全部移除。另外,在说明书中的方法或其他部分所述的各种功能,可合并提供额外及/或其他的功能。因此,本发明的保护范围应当视随附的权利要求所界定的范围为准。
Claims (14)
1.一种制造半导体装置的方法,包括:
在一硅基底上定义一掩模,该掩模包括多个穿过其中的纳米尺寸的开口,多个开口中的每一个露出所述硅基底的表面部分;
在定义该掩模之后,在每个所述开口中自该硅基底的表面部分建造实质上无缺陷的非硅半导体的纳米岛,其中,所述纳米岛的顶面与所述掩模的顶面齐平,所述纳米岛的厚度小于或等于50纳米,以及,所述纳米岛由异质外延层构成并且异质外延层中之一为栅极氧化层,所述栅极氧化层最远离所述硅基底的表面部分;
在建造所述多个纳米岛之后,在所述多个纳米岛上沉积高介电常数栅极电介质;以及
在沉积该高介电常数栅极电介质之后,在所述多个纳米岛上架构晶体管。
2.如权利要求1所述的方法,其中建造所述多个纳米岛包括借由金属有机化学气相沉积法进行多个非硅半导体纳米岛的选择性的异质外延生长。
3.如权利要求1所述的方法,其中建造所述多个纳米岛包括借由气相源分子束外延法进行多个非硅半导体纳米岛的选择性的异质外延生长。
4.如权利要求1所述的方法,其中沉积该高介电常数栅极电介质是借由金属有机化学气相沉积法进行。
5.如权利要求1所述的方法,其中沉积该高介电常数栅极电介质是借由原子层沉积法进行。
6.如权利要求1所述的方法,其中沉积该高介电常数栅极电介质是借由分子束外延法进行。
7.如权利要求1项所述的方法,其中所述多个开口中的每一个是六角形。
8.一种半导体装置,包括:
一硅基底;
一掩模,设置在该硅基底的顶表面上,并包括多个穿过其中的纳米尺寸开口,多个开口中的每一个露出所述硅基底的顶表面部分;
多个实质上无缺陷的非硅半导体的纳米岛,每个所述开口中形成有一个纳米岛,并且纳米岛生长在该硅基底穿过开口而露出的顶表面部分,其中,所述纳米岛的顶面与所述掩模的顶面齐平,所述纳米岛的厚度小于或等于50nm,以及,所述纳米岛的异质外延层中之一为栅极氧化层,并且所述栅极氧化层最远离所述硅基底的顶表面部分;
高介电常数栅极电介质,设置在所述多个纳米岛上;以及
晶体管,形成在所述多个纳米岛上。
9.如权利要求8所述的半导体装置,其中所述多个开口中的每一个是六角形。
10.如权利要求8所述的半导体装置,其中该硅基底具有(111)表面方向。
11.如权利要求8所述的半导体装置,其中该掩模包括一硬掩模。
12.一种制造半导体装置的方法,包括:
在一硅基底上定义一掩模,该掩模包括多个穿过其中的纳米尺寸的开口,多个开口中的每一个露出所述硅基底的表面部分;
使用金属有机化学气相沉积法与气相源分子束外延法中的至少一个方法,在该硅基底穿过所述多个开口而露出的表面进行实质上无缺陷的多个非硅半导体纳米岛的选择性的异质外延生长,其中,所述非硅半导体纳米岛的顶面与所述掩模的顶面齐平,所述纳米岛的厚度小于或等于50nm,以及,所述非硅半导体纳米岛由异质外延层构成并且异质外延层中之一为栅极氧化层,所述栅极氧化层最远离所述硅基底的表面部分;
在建造所述多个非硅半导体纳米岛之后,借由金属有机化学气相沉积法、原子层沉积法与分子束外延法中的至少一个方法,在所述多个非硅半导体纳米岛上沉积高介电常数栅极电介质;以及
在沉积该高介电常数栅极电介质之后,在所述多个非硅半导体纳米岛上架构晶体管。
13.如权利要求12所述的方法,其中架构所述多个晶体管包括设置栅极、侧壁与欧姆接触。
14.如权利要求12所述的方法,其中所述多个开口中的每一个是六角形。
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