TWI483359B - 線路載板及應用此線路載板之半導體封裝結構 - Google Patents

線路載板及應用此線路載板之半導體封裝結構 Download PDF

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TWI483359B
TWI483359B TW098105657A TW98105657A TWI483359B TW I483359 B TWI483359 B TW I483359B TW 098105657 A TW098105657 A TW 098105657A TW 98105657 A TW98105657 A TW 98105657A TW I483359 B TWI483359 B TW I483359B
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bonding pad
wafer
layer
substrate
bump
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TW098105657A
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TW201032306A (en
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Chien Liu
Chih Ming Chung
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Advanced Semiconductor Eng
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Priority to US12/683,613 priority patent/US8384204B2/en
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
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    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
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Description

線路載板及應用此線路載板之半導體封裝結構
本發明是有關於一種線路載板及應用此線路載板之半導體封裝結構，且特別是有關於一種在基板之接合墊上形成一棕化層的線路載板及應用此線路載板之半導體封裝結構。
覆晶接合技術(flip chip interconnect technology)係為一種將晶片(die)連接到承載器(carrier)的封裝技術，其主要係將晶片之多個銲墊(pad)，利用面陣列(area array)的排列方式，配置於晶片之主動表面(active surface)上，並在各個銲墊上分別依序形成球底金屬層(Under Bump Metallurgy,UBM)及凸塊(bump)，其例如為銲料凸塊(solder bump)，接著將晶片翻面(flip)之後，再利用這些凸塊來將晶片之主動表面上的這些銲墊分別電性及結構性地連接至一承載器(例如為基板(substrate)或印刷電路板(printed circuit board,PCB))之表面的多個接點。值得注意的是，覆晶接合技術可適用於高接腳數(high pin count)之晶片封裝結構，並具有縮小封裝面積及縮短訊號傳輸路徑等優點。
圖1A繪示為習知之一種線路載板與對接晶片上之凸塊未接合前的剖面示意圖。圖1B繪示為圖1A中所示之線路載板與對接晶片上之凸塊接合後的剖面示意圖。請參考圖1A所示，線路載板100主要包含一基板110、多個接合墊(bonding pad)120以及一銲罩層(solder mask)130。其中基板110包含多個導線層、多個絕緣層及多個導電孔(conductive via)(圖均未繪示)，而每一絕緣層配置於相鄰兩導線層之間，且每一導電孔穿過至少一絕緣層，以連接至少兩導線層。此外，這些接合墊120a配置於基板110之表面112上，用以分別連接對接晶片200上的多個凸塊(bump)210，例如為覆晶接合用之銲料凸塊(flip chip solder-bump)。而這些接合墊120a可由基板110最外層的導線層120所構成。此外，由於基板110上之導線層120的材質通常為銅，所以接合墊120a之材質亦為銅。銲罩層130全面性地覆蓋於基板110的表面112上，且銲罩層130具有多個開口132以分別暴露出接合墊120a。
如圖1B所示，在進行迴焊製程以將凸塊210與接合墊120a連結時，由於凸塊210與接合墊120a之間結合的狀況很好，因此，凸塊210會整個塌陷下來，且包覆住整個接合墊120a。而此將會降低線路載板100與對接晶片200之間的間距，進而增加後續製程之困難度。
此外，由於在製作銲罩層130時，其開口132會有製作公差，且銲罩層130可能會發生偏移(shift)的情形。對於微間距(fine pitch)的元件而言，上述這些因素皆會提升線路載板製作時之困難度。
本發明提供一種線路載板及應用此線路載板之半導體封裝結構。此線路載板主要是在其接合墊上形成一棕化層，以解決習知技術中因凸塊塌陷而造成線路載板與晶片之間的間距縮小，以及製作銲罩層時可能會發生偏移的問題。
本發明提出一種線路載板，適於連接一凸塊。此線路載板包括一基板與至少一接合墊。基板具有一表面。此接合墊配置於基板之表面，以連接凸塊。其中，此接合墊之一表面具有一棕化層。
在本發明之一實施例中，接合墊之材質包括銅。
在本發明之一實施例中，棕化層之材質為氧化銅。
本發明另提出一種半導體封裝結構，包括一晶片、一線路載板以及一封裝膠體。晶片之一主動面上具有至少一凸塊。線路載板用以承載晶片，且包括一基板與至少一配置於基板表面之接合墊。此接合墊之一表面具有一棕化層，且接合墊連接相對應之凸塊，使線路載板透過凸塊與晶片電性連接。封裝膠體配置於線路載板上，以包覆晶片。
在本發明之一實施例中，接合墊之材質包括銅。
在本發明之一實施例中，棕化層之材質為氧化銅。
在本發明之一實施例中，半導體封裝結構更包括一底膠，填充於晶片與線路載板之間。
本發明之線路載板及應用此線路載板之半導體封裝結構主要是在基板的表層線路及接合墊上形成一棕化層。當線路載板與對接晶片接合時，凸塊能直接站在接合墊表面之棕化層上，以增加線路載板與對接晶片之間的間距，而使得後續製程容易進行。
此外，在線路載板之表層線路及接合墊上形成棕化層之後，線路載板上不需再形成銲罩層而能直接與對接晶片連接，如此，即可避免習知技術中因採用銲罩層而遭遇到之製作公差及偏移的問題。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。
圖2繪示為根據本發明之一實施例的一種線路載板之剖面示意圖。請參考圖2所示，此線路載板300包括一基板310與至少一接合墊320。以下將搭配圖示說明線路載板300所包含之各元件以及元件之間的連接關係。此外，在此實施例中，是以多個接合墊320為例以作說明，然而，本發明對於配置於基板310上之接合墊320的數目不作任何限制。
基板310包含多數個導線層、多數個絕緣層及多數個導電孔(圖均未示)，而每一絕緣層係配置於相鄰兩導線層之間，且每一導電孔係穿過絕緣層而與至少兩導線層相互連接。這些接合墊320配置於基板310之表面310a上，用以連接對接晶片(圖中未示)上覆晶接合用的凸塊。而這些接合墊320可由基板310之最外層的表層線路層所構成，由於基板310之表層線路層的材質通常為銅，所以接合墊320之材質亦為銅。而這些接合墊320的表面上形成有一棕化層322。此棕化層322可藉由對基板310上之表層線路層320a及接合墊320進行一棕化處理而形成。在此實施例中，棕化層322之材質為氧化銅。
由於在利用迴焊製程將線路載板300之接合墊320與對接晶片上的凸塊接合時，凸塊會站在接合墊320表面之棕化層322上，而不會整個塌陷下來，且包覆住整個接合墊320，如此，將有助於增加線路載板300與對接晶片之間的間距，使後續填膠的製程更容易進行。
圖3繪示為根據本發明之一實施例的一種半導體封裝結構的剖面示意圖。此半導體封裝結構主要是利用圖2中所示之線路載板與對接晶片連接，以避免習知技術中凸塊與接合墊之間結合的狀況太好，而發生凸塊坍塌的情形。
請參考圖3所示，此半導體封裝結構600主要包含一如圖2中所示之線路載板300、一晶片400以及一封裝膠體500。晶片400之一主動面400a上具有多個凸塊410。線路載板300即用以承載晶片400，其具有一基板310及配置於基板310表面之接合墊320。同樣地，接合墊320的表面形成有一棕化層322。而接合墊320會連接相對應的凸塊410，使線路載板300透過凸塊410與晶片400電性連接。如圖3中所示，由於在接合墊320上有形成一棕化層322的原故，因此，凸塊410會站在接合墊320表面的棕化層322上，而不會整個塌陷下來，以增加線路載板300與晶片400之間的間距，使後續填膠的製程更容易進行。
封裝膠體500配置於線路載板300上。此封裝膠體500會包覆住整個晶片400，以保護整個封裝結構免於受損及受潮。在此實施例中，是先於線路載板300與晶片400之間填充一底膠700，之後，再於線路載板300上形成封裝膠體500，以包覆整個晶片400。然而，亦可直接在線路載板上300形成封裝膠體500，使其亦填充於線路載板300與晶片400之間即可。
綜上所述，本發明之線路載板及應用此線路載板之半導體封裝結構主要是在基板的表層線路及接合墊上形成一棕化層。當線路載板與對接晶片接合時，凸塊能直接站在接合墊表面之棕化層上，以增加線路載板與對接晶片之間的間距，而使得後續製程容易進行。此外，在線路載板之表層線路及接合墊上形成棕化層之後，線路載板上不需再形成銲罩層而能直接與對接晶片連接，如此，即可避免習知技術中因採用銲罩層而遭遇到之製作公差及偏移的問題。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．線路載板
110．．．基板
112．．．表面
120．．．導線層
120a．．．接合墊
130．．．銲罩層
132．．．開口
200．．．對接晶片
210．．．凸塊
300．．．線路載板
310．．．基板
310a．．．表面
320．．．接合墊
320a‧‧‧表層線路層
322‧‧‧棕化層
400‧‧‧晶片
400a‧‧‧主動面
410‧‧‧凸塊
500‧‧‧封裝膠體
600‧‧‧半導體封裝結構
700‧‧‧底膠
圖1A繪示為習知之一種線路載板與對接晶片上之凸塊未接合前的剖面示意圖。
圖1B繪示為圖1A中所示之線路載板與對接晶片上之凸塊接合後的剖面示意圖。
圖2繪示為根據本發明之一實施例的一種線路載板之剖面示意圖。
圖3繪示為根據本發明之一實施例的一種半導體封裝結構的剖面示意圖。
300．．．線路載板
310．．．基板
310a．．．表面
320．．．接合墊
320a．．．表面
322．．．棕化層

Claims (7)

  1. 一種線路載板，適於連接一凸塊，該線路載板包括：一基板，具有一表面；以及至少一接合墊，配置於該基板之該表面，以連接該凸塊，其中該接合墊之一表面具有一棕化層位於其上而該棕化層完全覆蓋該接合墊之該表面，該接合墊並未被一銲罩層覆蓋。
  2. 如申請專利範圍第1項所述之線路載板，其中該接合墊之材質包括銅。
  3. 如申請專利範圍第1項所述之線路載板，其中該棕化層之材質為氧化銅。
  4. 一種半導體封裝結構，包括：一晶片，該晶片之一主動面上具有至少一凸塊；一線路載板，用以承載該晶片，該線路載板包括：一基板，具有一表面；以及至少一接合墊，配置於該基板之該表面，其中該接合墊之一表面具有一棕化層位於其上而該棕化層完全覆蓋該接合墊之該表面，該接合墊並未被一銲罩層覆蓋，且該接合墊連接相對應之該凸塊，使該線路載板透過該凸塊與該晶片電性連接；以及一封裝膠體，配置於該線路載板上，以包覆該晶片。
  5. 如申請專利範圍第4項所述之半導體封裝結構，其中該接合墊之材質包括銅。
  6. 如申請專利範圍第4項所述之半導體封裝結構，其 中該棕化層之材質為氧化銅。
  7. 如申請專利範圍第4項所述之半導體封裝結構，更包括一底膠，填充於該晶片與該線路載板之間。
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