TWI485840B - 具有彈性導電體之堆疊式封裝 - Google Patents

具有彈性導電體之堆疊式封裝 Download PDF

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TWI485840B
TWI485840B TW099130975A TW99130975A TWI485840B TW I485840 B TWI485840 B TW I485840B TW 099130975 A TW099130975 A TW 099130975A TW 99130975 A TW99130975 A TW 99130975A TW I485840 B TWI485840 B TW I485840B
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Taiwan
Prior art keywords
package
stacked
semiconductor wafer
elastic
substrate
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TW099130975A
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TW201135906A (en
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Tae Min Kang
You Kyung Hwang
Jae-Hyun Son
Dae Woong Lee
Byoung Do Lee
Yu Hwan Kim
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Hynix Semiconductor Inc
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Publication of TW201135906A publication Critical patent/TW201135906A/zh
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Publication of TWI485840B publication Critical patent/TWI485840B/zh

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

具有彈性導電體之堆疊式封裝
本發明係揭示一種堆疊式封裝，包括一第一封裝，具有一第一半導體晶片和一密封該第一半導體晶片之第一封裝構件；及一第二封裝，係堆疊於第一封裝上，並且包括一第二半導體晶片和一密封該第二半導體晶片之第二封裝構件。而彈性導電體係被設置於第一封裝之第一封裝構件中，用以電性連接該第一封裝和第二封裝。
本申請案在此聲明以2010年4月14日提出申請之韓國專利申請第10-2010-0034400主張優先權，該申請之全部內容已合併於本說明中作為參考。
本發明係有關一種堆疊式封裝，特別是關於一種堆疊式封裝，可以實際防止由於零組件之間熱膨脹係數之差異而發生之缺陷。
近來，已經發展一種具有可以在短時間內儲存及處理大量資料之記憶體半導體封裝之半導體封裝。又，已經發展一種堆疊式封裝，其中數個記憶體半導體封裝係於晶片層級或封裝層級堆疊，以增加資料儲存容量。層疊封裝(POP)係堆疊式封裝之代表例子，其係經由於封裝層級堆疊記憶體半導體封裝而構成。
近來的封裝發展又包括一種系統級封裝(SIP)，其中係堆疊記憶體半導體封裝和一系統半導體晶片以改進資料儲存容量與資料處理速度。一般，此系統級封裝係經由將記憶體半導體封裝和系統半導體晶片於一晶片層級堆疊而構成。該系統級封裝亦可能經由將記憶體半導體封裝和系統半導體晶片於一封裝層級堆疊而構成。
習見之堆疊式封裝係經由垂直堆疊半導體封裝而構成。然而，此種垂直堆疊之半導體封裝由於零組件之間熱膨脹係數之差異而會發生缺陷等問題，因此降低此種封裝之可信賴性。
詳言之，在習見堆疊式封裝中，介於一第一封裝和第二封裝之電性連接係藉由在第一封裝形成預焊接劑或貼銅封裝而達成。在此習見堆疊式封裝結構中，由於作為密封一半導體晶片之封裝構件之環氧樹脂(EMC)與用於第一封裝和第二封裝之間之電性連接而形成之預焊接劑或貼銅封裝之熱膨脹係數(CTE)不一致，第一封裝可能發生折曲和缺陷，因此會降低堆疊式封裝之可信賴性。
本發明之一具體實施例係包括一堆疊式封裝，可以實際防止由於零組件之間熱膨脹係數不一致而發生之折曲。
又，本發明之一具體實施例係包括一堆疊式封裝，可以抑制由於零組件之間熱膨脹係數不一致所發生之缺陷。
再者，本發明之一具體實施例係包括一堆疊式封裝，可以經由減少由於零組件之間熱膨脹係數不一致所發生之折曲和缺陷而提高可信賴性。
在本發明之一具體實施例，一堆疊式封裝係包括：一第一封裝，具有一第一半導體晶片和一密封該第一半導體晶片之第一封裝構件；一第二封裝，係堆疊於第一封裝上，並且具有一第二半導體晶片和一密封該第二半導體晶片之第二封裝構件；及彈性導電體，係設置於第一封裝之第一封裝構件，用以電性連接該第一封裝和第二封裝。
該彈性導電體可具有一配置結構，其中一軟式電路板係有銅圖案於其一面形成，該銅圖案以中空圓柱之形狀捲起，因此該銅圖案係配置於外部；或者，該彈性導電體具有一配置結構，其中一軟式電路板係有銅圖案於其一面形成，該面呈截面狀並且於反向彎曲。
第一封裝構件可具有數個插入各彈性導電體之孔。
該堆疊式封裝又包括底部填充物，係於插入各彈性導電體之第一封裝構件之各孔形成。
該堆疊式封裝可又包括附著於第一封裝之下表面之第一耦合構件。
該堆疊式封裝又可包括第二耦合構件，係附著於第二封裝之下表面，並且與彈性導電體電性連接。
第二耦合構件可包括數個錫球數個錫球或其他彈性導電體。
本發明之一具體實施例中，一堆疊式封裝係包括：一第一封裝，包括一第一基板，該第一基板之上表面係設置數個第一焊手指與連接墊，其下表面係設置數個第一銲錫球墊；一第一半導體晶片，係設置於第一基板之上表面於第一基板之上表面，並且與具有與第一焊手指電性連接之第一銲墊與一於第一基板之上表面形成以密封該第一半導體晶片之第一封裝構件；一第二封裝，係堆疊於第一封裝上，並且包括一第二基板，具有一設置第二焊手指之上表面與一設置第二銲錫球墊之下表面；一第二半導體晶片，係設置於第二基板之上表面，並且具有與第二焊手指電性連接之第二銲墊；及一第二封裝構件，於第二基板之上表面形成，用以密封第二半導體晶片；及彈性導電體，係設置於第一封裝之第一封裝構件，以電性連接第一封裝和第二封裝。
該堆疊式封裝又可包括數個附著於第一銲錫球墊之第一耦合構件。
該彈性導電體也許具有由第一封裝構件露出之一端，該端係直接連接各第二銲錫球墊。
該堆疊式封裝又可包括第二耦合構件，係附著於該第二銲錫球墊，並且與設置於第一封裝構件彈性導電體相接。
該彈性導電體也許具有由第一封裝構件露出之一端，該端係與第二耦合構件相接。
第二耦合構件可包括數顆錫球或其他彈性導電體。
各彈性導電體可具有一配置結構，其中一軟式電路板係有銅圖案於其一面形成，該銅圖案以中空圓柱之形狀捲起，因此該銅圖案係配置於外部；或者，該彈性導地舔具有一配置結構，其珠一軟式電路板係有銅圖案於其一面形成，該面呈截面狀並且於反向彎曲。
第一封裝構件也許具有分別使各連接墊露出之孔，各彈性導電體可分別插入這些孔。
該堆疊式封裝又可包括於第一封裝構件之孔形成之底部填充物，該孔係可插設該彈性導電體。
第一封裝構件也許具有數個孔，各孔同時使兩個鄰近之連接墊露出，各彈性導電體分別插入各孔。
各彈性導電體可包括一軟式電路板，該電路板具有一面以及在該面另一方向之另一面，以及於該軟式電路板之一面形成之銅圖案，其係具有一配置結構。其中該銅圖案係分別配置於各孔之二側壁，並且具有一U形截面形狀。
該堆疊式封裝又可包括於第一封裝構件之孔形成之底部填充物，該孔係可插設該彈性導電體。
具有第一銲墊之第一半導體晶片與具有第二銲墊之第二半導體晶片，係分別以向上形式設置於設置有第一焊手指之第一基板之上表面，以及設置有第二焊手指之第二基板之上表面。
該堆疊式封裝又可包括連接構件，係將第一半導體晶片之第一銲墊與第一基板之第一焊手指相互電性連接，及將第二半導體晶片之第二銲墊與第二基板之第二焊手指相互電性連接。
該連接構件可包括數條導線或圖案薄膜。
具有第一銲墊之第一半導體晶片與具有第二銲墊之第二半導體晶片，係分別以向下形式設置於有第一焊手指之第一基板之上表面，以及設置有第二焊手指之第二基板之上表面。
該堆疊式封裝又可包括連接構件，係將第一半導體晶片之第一銲墊與第一基板之第一焊手指相互電性連接，以及將第二半導體晶片之第二銲墊與第二基板之第二焊手指相互電性連接。
該連接構件也許包括數個凸塊或焊錫。
在本發明之一具體實施例中，一堆疊式封裝係包括：一第一封裝，具有一第一半導體晶片和一密封該第一半導體晶片之第一封裝構件；一或多個第二封裝，係堆疊於第一封裝上，並且具有第二半導體晶片和密封該第二半導體晶片之第二封裝構件；及彈性導電體，係分別設置於第一封裝之第一封裝構件與第二封裝之第二封裝構件(除了在堆疊之第二封裝當中之最上者)，以致將各第一封裝與各第二封裝相互電性連接。
各彈性導電體可具有一配置結構，其中一軟式電路板係有銅圖案於其一面形成，該銅圖案以中空圓柱之形狀捲起，因此該銅圖案係配置於外部；或者，該彈性導電體具有一配置結構，其中一軟式電路板係有銅圖案於其一面形成，該面呈截面狀並且於反向彎曲。
該堆疊式封裝又可包括第一耦合構件，係附著於第一封裝之下表面；及第二耦合構件，係附著於第二封裝之下表面，並且與該彈性導電體電性連接。
第二耦合構件可包括數顆錫球或其他彈性導電體。
茲將參照附加圖示詳細說明本發明之各具體實施例。
茲將參照附加剖面圖示說明各具體實施例(及中間結構)。據此，由於圖示形狀之不同所造成之結果，可預期製造技術和(或)容差之差異。因此，不應該將各具體實施例侷限於在此描述之特定區域形狀，亦需包括製造而導致之各種形狀偏差。在圖示中，各層與各區之長度與大小可能被放大以明示。圖示中類似之圖號係代表類似之元件。需了解的是，當指稱一層或在另一層或基板「上」，可以表示直接在另一層或基板上，或者表示中介層。
第1圖係顯示根據本發明之一具體實施例之一堆疊式封裝之剖面圖。參照第1圖，根據本發明之一具體實施例之堆疊式封裝100係包括一第一封裝100a和一堆疊於第一封裝100a上之第二封裝100b。
第一封裝100a，係包括一第一基板110a，一設置於第一基板110a上之第一半導體晶片120a，一密封第一半導體晶片120a之第一封裝構件150a，及設置於第一封裝構件150a之彈性導電體170。
第一基板110a可以為一印刷電路板，雖然其並不侷限於此。該第一基板110a具有數個第一焊手指112a，設置於第一基板110a之上表面之連接墊114a，及設置於第一基板110a之下表面之第一銲錫球墊116a。舉例而言，第一半導體晶片120a係包括一邊緣接片型式晶片。該第一半導體晶片120a係藉由一第一黏著構件130a而以向上形式附著於第一基板110a之上表面。
第一封裝100a又包括第一連接構件140a，係連接分別設置於第一半導體晶片120a之第一銲墊122a與鄰近第一銲墊122a的第一基板110a之第一焊手指112a。如圖所示，第一連接構件140a可包括數條導線，不過應了解到本發明並未侷限於此。舉例而言，儘管未顯示於圖示中，具有電路圖案之圖案薄膜可以用來作為第一連接構件140a。
第一封裝100a又可包括數個第一耦合構件160a，分別附著於設置於第一基板110a之下表面之各第一銲錫球墊116a。如圖所示，該第一耦合構件160a可包括數個錫球。
第一封裝構件150a係形成而覆蓋包括第一半導體晶片120a和第一連接構件140a之第一基板110a之上表面。例如，可使用環氧樹脂(EMC)作為第一封裝構件150a。
彈性導電體170係設置於第一封裝100a之第一封裝構件150a。根據本發明之一具體實施例，如第2圖所示，各彈性導電體170係包括一絕緣軟式電路板172和於該軟式電路板172之一面形成之銅圖案174。如第2圖所示，各彈性導電體170皆具有一種結構，其中軟式電路板172具有於裹著中空圓柱之一面之數個銅圖案174，因此該銅圖案174係沿著該圓柱體之周邊外部配置。軟式電路板172之兩面，係藉由一膠黏劑而相互附著(並未詳細顯示)。
根據一具體實施例，彈性導電體170也許具有一配置結構，其中在一面形成銅圖案174之軟式電路板172，其具有之橫截面形狀係於反方向上彎曲，如第3圖所示。呈彎曲結構之彈性導電體170，由於該銅圖案174係配置在軟式電路板172之上、下端，以致該銅圖案174位於各軟式電路板172之上、下端之接觸點。
如第1圖所示，在彈性導電體170中，銅圖案174之下端係與第一基板110a之連接墊114a相接，而銅圖案174之上端係由第一封裝構件150a之表面露出。
根據一具體實施例，在形成第一封裝構件150a之前，彈性導電體170可以設置於第一基板110a之各連接墊114a上。接著，第一封裝構件150a形成，舉例而言，至使彈性導電體170之上端露出之厚度。或者，第一封裝構件150a形成至可完全覆蓋彈性導電體170之厚度，然後減少其厚度，例如藉由進行研磨，以致使該彈性導電體170之上端露出。
雖未詳細顯示，可想見的是第一封裝構件150a也許於具有彈性導電體170之第一基板110a上形成，該第一基板110a形成之厚度係完全覆蓋該彈性導電體170，接著。可以選擇性地對該第一基板110a蝕刻，使該彈性導電體170之上端同時露出。
第二封裝100b，係包括一第二基板110b，一設置於第二基板110b上之第二半導體晶片120b，及一密封第二半導體晶片120b之第二封裝構件150b。
第二基板110b可用作為一印刷電路板，雖然本發明未侷限於此。該第二基板110b具有配置於第二基板110b上表面之第二焊手指112b與第二基板110b下表面之第二銲錫球墊116b。第二半導體晶片120b可能包括，舉例而言，一邊緣接片型式晶片。該第二半導體晶片120b係藉由第二黏著構件130b以朝上形式附著於第二基板110b之上表面。
第二封裝100b又包括第二連接構件140b，係電性連接分別設置於鄰近第二半導體晶片120b之第二銲墊122b和第二基板110b之第二焊手指112b。該第二連接構件140b可包括數條導線。雖然未顯示於圖示，具有電路圖案之圖案薄膜可被用來作為第二連接構件140b。
第二封裝100b又可包括數個分別附著於配置於第二基板110b下表面之第二銲錫墊116b之第二耦合構件160b。該第二耦合構件160b可包括數個錫球。又，如同第二耦合構件160b，其他具有與該彈性導電體170相同或相似結構之彈性導電體，亦可被用來插入第一封裝構件150a。
根據一具體實施例，第二耦合構件160b係與第一封裝100a之第一封裝構件150a之表面露出之彈性導電體170電性連接。詳言之，第二耦合構件160b係與配置於彈性導電體170上端之銅圖案172電性連接，而且由第一封裝構件150a之表面露出，以致將第二封裝100b和第一封裝100a相互電性連接。
第二封裝構件150b係形成而覆蓋包括第二半導體晶片120b和第二連接構件140b之第二基板110b之上表面。環氧樹脂(EMC)可被用來作為第二封裝構件150b。
根據本發明之一具體實施例之上述堆疊式封裝100中，第二封裝100b可以不用將第二耦合構件160b附著於第二銲錫球116b之形式構成。依此方式，由第一封裝100a之第一封裝構件150a之表面露出之彈性導電體170，係直接連接第二封裝100b之第二銲錫球墊116b。
如上所述，根據本發明之一具體實施例構成之堆疊式封裝係具有一層疊封裝(POP)結構，其中第一封裝和第二封裝之間之電性連接係經由將彈性導電體插入第一封裝而實現。因此，根據本發明之一具體實施例之堆疊式封裝，相較於經由將預焊接劑或貼銅封裝插入第一封裝而構成之習見堆疊式封裝，其零組件之間之熱膨脹係數(CTE)之不一致可以減少，因此可降低第一封裝折曲之發生，並且抑制缺陷之發生。
舉例而言，相較於習見技術，根據本發明之一具體實施例之堆疊式封裝，由於在習見技術中作為第一封裝構件之材料之環氧樹脂(EMC)和焊料或環氧樹脂(EMC)和貼銅封裝之間不一致相對降低，折曲將減少百分之五十或更多。而且，該彈性導電體能減少由於環氧樹脂(EMC)和焊料或環氧樹脂(EMC)和貼銅封裝之間不一致所導致之應力，相較於習見技術，發生之缺陷減少大約百分之二十～五十。
因此，根據本發明之第一具體實施例之堆疊式封裝，由於零組件間熱膨脹係數(CTE)不一致所產生之折曲和缺陷的發生相對降低，因此可以改進根據本發明之一具體實施例之堆疊式封裝之可信賴性。
第4圖係顯示根據本發明之一具體實施例之一堆疊式封裝之剖面圖。茲機使用與第1圖相同之圖號來指稱相同或相似之部件。
參照第4圖，數個孔H1係界定於第一封裝100a之第一封裝構件150a，以致於分別使設置於第一基板110a上表面之各連接墊114a露出。各彈性導電體170分別被插入各孔H1，並且配置而分別與各對應之連接墊114a連接。底部填充物180係於可插入彈性導電體170之孔H1中形成。該孔H1係穿通之孔，例如在第一封裝構件150a形成後進行一鑽孔或蝕刻製程。
彈性導電體170係設置而呈，舉例而言，一環形截面形狀，如第2圖所示，底部填充物180亦於該彈性導電體170形成。除了環形截面形狀之外，雖然未顯示於圖中，該彈性導電體170亦或具有一於反方向彎曲之截面形狀，如第3圖所示。
由於第4圖所示之根據本發明之一具體實施例之堆疊式封裝200之其他零組件係與第1圖之堆疊式封裝100之零組件一樣，茲將省略重複說明。
第5圖係顯示根據本發明之一具體實施例之一堆疊式封裝之剖面圖。茲將使用與第1圖相同之圖號來指稱相同或相似之部件。
參照第5圖，孔H2係被限定於第一封裝100a之第一封裝構件150a，以致於各孔H2露出二鄰近之連接墊114a，各彈性導電體170係插入各孔H2。底部填充物180係於用以插入彈性導電體170之各孔H2形成。該底部填充物180亦於該彈性導電體170形成。
在此具體實施例，彈性導電體170之配置方式係其中之軟式電路板172之一面形成銅圖案174，該銅圖案174係分別配置於各孔H2之二側壁，並且呈一U形截面形狀。
由於第5圖所示之根據本發明之一具體實施例之堆疊式封裝300之其他零組件係與第1圖之堆疊式封裝100之零組件一樣，茲將省略重複說明。
第6圖係顯示根據本發明之一具體實施例之一堆疊式封裝之剖面圖。茲將使用與第1圖相同之圖號來指稱相同或相似之部件。
參照第6圖，第一封裝100a之第一半導體晶片120a與第二封裝100b之第二半導體晶片120b，係以向下之形式分別設置於第一基板110a和第二基板110b，即覆晶結合(flip chip bonding)相對於打線接合(wire bonding)。
第一基板110a之第一焊手指112a與第二基板110b之第二焊手指112b分別配置於與第一半導體晶片120a之第一銲墊122a與第二半導體晶片120b之第二銲墊122b對應之位置。該第一半導體晶片120a之第一銲墊122a與第一基板110a之第一焊手指112a係藉由第一連接構件140a，例如凸塊，而相互電性連接。第二半導體晶片120b之第二銲墊122b與第二基板110b之第二焊手指112b係藉由第二連接構件140b，例如凸塊，而相互電性連接。除了凸塊之外，焊錫或相似物亦可用來作為第一連接構件140a和第二連接構件140b。
由於第6圖所示之根據本發蒙之一具體實施例之堆疊式封裝400之其他零組件係與第1圖所示之堆疊式封裝100之零組件一樣，茲將省略重複說明。
第7圖係顯示根據本發明之一具體實施例之一堆疊式封裝之剖面圖。茲將使用與第1圖相同之圖號來指稱相同或相似之部件。
根據本發明之具體實施例，可以將二或更多個第二封裝堆疊於第一封裝上。舉例而言，參照第7圖，兩個第二封裝100b1、100b2係堆疊於第一封裝100a上。堆疊之第二封裝100b1、100b2之最上面的第二封裝100b2，係具有與上述第二封裝100b1相同之結構。設置於最上面之第二封裝100b2下面之其餘的第二封裝100b1，係具有與第一封裝100a一樣之結構，亦即，彈性導電體170係配置於一第二封裝構件150b中，而與配置其上之第二封裝100b2電性連接。
如上所述，彈性導電體170具有一配置結構，其中一軟式電路板之一面形成銅圖案，其係捲曲呈一中空圓柱狀，以致於該銅圖案配置於該電路板之一外表面上。雖然未顯示於圖示中，彈性導電體170也許具有一配置結構，其中一軟式電路板之一面形成銅圖案，該面具有於反方向彎曲之截面形狀，如第3圖所示。
在此具體實施例，彈性導電體170係設置於第一封裝100a和第二封裝100b1。該彈性導電體170係將第一封裝100a和第二封裝100b1電性連接，以及將第二封裝100b1、100b2電性連接。
彈性導電體170之一端係連接相對應之連接墊114a、114b，該彈性導電體170之另一端，其係在上述端之另外的方向，而且由該封裝構件150a、150b之表面露出，係與第二封裝100b1、100b2之第二耦合構件160b電性連接。
由於第7圖所示之根據本發明之一具體實施例之堆疊式封裝500之其他零組件係與第1圖之堆疊式封裝100之零組件一樣，茲將省略重複說明。
雖然本發明較佳具體實施例主要要作為說明之用，那些熟悉本技術的人將察覺到各種修改、增加及替換，而沒有偏離揭示於下之申請專利範圍中的範圍和精神，均有其可能性。
100．．．堆疊式封裝
100a．．．第一封裝
100b．．．第二封裝
110a．．．第一基板
110b．．．第二基板
112a．．．第一焊手指
112b．．．第二焊手指
114a、114b．．．連接墊
116a．．．第一銲錫球墊
116b．．．第二銲錫球墊
120a．．．第一半導體晶片
120b．．．第二半導體晶片
122a．．．第一銲墊
122b．．．第二銲墊
130a．．．第一黏著構件
130b．．．第二黏著構件
140a．．．第一連接構件
140b．．．第二連接構件
150a．．．第一封裝構件
150b．．．第二封裝構件
160a．．．第一耦合構件
160b．．．第二耦合構件
170．．．彈性導電體
172．．．軟式電路板
174．．．銅圖案
200．．．堆疊式封裝
180．．．底部填充物
300．．．堆疊式封裝
400．．．堆疊式封裝
500．．．堆疊式封裝
100b1、100b2．．．第二封裝
第1圖係一根據本發明之一具體實施例顯示一堆疊式封裝之剖面圖。
第2、3圖係根據本發明之具體實施例顯示用於堆疊式封裝之彈性導電體之透視圖。
第4圖係一根據本發明之一具體實施例顯示一堆疊式封裝之剖面圖。
第5圖係一根據本發明之一具體實施例顯示一堆疊式封裝之剖面圖。
第6圖係一根據本發明之一具體實施例顯示一堆疊式封裝之剖面圖。
第7圖係一根據本發明之一具體實施例顯示一堆疊式封裝之剖面圖。
100．．．堆疊式封裝
100a．．．第一封裝
100b．．．第二封裝
110a．．．第一基板
110b．．．第二基板
112a．．．第一焊手指
112b．．．第二焊手指
114a．．．連接墊
116a．．．第一銲錫球墊
116b．．．第二銲錫球墊
120a．．．第一半導體晶片
120b．．．第二半導體晶片
122a．．．第一銲墊
122b．．．第二銲墊
130a．．．第一黏著構件
130b．．．第二黏著構件
140a．．．第一連接構件
140b．．．第二連接構件
150a．．．第一封裝構件
150b．．．第二封裝構件
160a．．．第一耦合構件
160b．．．第二耦合構件
170．．．彈性導電體

Claims (16)

  1. 一種堆疊式封裝，包括：一第一封裝，包括一第一半導體晶片和一密封該第一半導體晶片之第一封裝構件；一第二封裝，係堆疊於第一封裝上，並且包括一第二半導體晶片和一密封該第二半導體晶片之第二封裝構件；及彈性導電體，係設置於第一封裝之第一封裝構件中，以電性連接該第一封裝和第二封裝；其中各彈性導電體係包括一軟式電路板，而於該軟式電路板之一面形成銅圖案；其中該彈性導電體之一種配置結構係以中空圓柱狀捲曲，將銅圖案配置於一圓柱體之外表面上，或具有一在反向彎曲之截面形狀。
  2. 如申請專利範圍第1項之堆疊式封裝，其中該第一封裝構件具有數個用以插入各彈性導電體之孔。
  3. 如申請專利範圍第1項之堆疊式封裝，其又包括：第一耦合構件，係附著於第一封裝之下表面。
  4. 如申請專利範圍第1項之堆疊式封裝，其又包括：第二耦合構件，係附著於第二封裝之下表面，並且與該彈性導電體電性連接。
  5. 如申請專利範圍第4項之堆疊式封裝，其中該第二耦合構件係包括多數個錫球或其他彈性導電 體。
  6. 一種堆疊式封裝，包括：一第一封裝，包括：一第一基板，其上表面係設置第一焊手指和連接墊，其下表面係設置第一銲錫球墊；一第一半導體晶片，係設置於第一基板之上表面，並且具有與該第一焊手指電性連接之第一銲墊；及一於第一基板之上表面形成之第一封裝構件，以密封第一半導體晶片；一堆疊於第一封裝之第二封裝，該第二封裝，包括：一第二基板，其上表面係設置第二焊手指，其下表面係設置第二銲錫球墊；一第二半導體晶片，係設置於第二基板之上表面，並且具有與第二焊手指電性連接之第二銲墊；及一第二封裝構件，係於第二基板之上表面形成，以密封第二半導體晶片；以及多數個彈性導電體，係設置於第一封裝之第一封裝構件，以電性連接第一封裝和第二封裝；其中各彈性導電體係包括一軟式電路板，而於該軟式電路板之一面形成銅圖案；其中該彈性導電體之一種配置結構係以中空 圓柱狀捲曲，將銅圖案配置於一圓柱體之外表面上，或具有一在反向彎曲之截面形狀。
  7. 如申請專利範圍第6項之堆疊式封裝，其又包括：第一耦合構件，係附著於第一銲錫球墊。
  8. 如申請專利範圍第6項之堆疊式封裝，其中每個彈性導電體之一端係由第一封裝構件露出，且直接連接第二銲錫球墊。
  9. 如申請專利範圍第8項之堆疊式封裝，其又包括：第二耦合構件，係附著於第二銲錫球墊，並且與設置於第一封裝構件之彈性導電體相互連接。
  10. 如申請專利範圍第9項之堆疊式封裝，其中第二耦合構件係包括多數錫球或額外之彈性導電體。
  11. 如申請專利範圍第7項之堆疊式封裝，其中該第一封裝構件當中具有數個孔，每個孔同時使各連接墊露出，該孔可分別插入各彈性導電體。
  12. 如申請專利範圍第11項之堆疊式封裝，其又包括：底部填充物，係形成於第一封裝構件之各孔中，而這些孔能讓各彈性導電體插入。
  13. 一種堆疊式封裝，包括：一第一封裝，包括：一第一基板，其上表面係設置第一焊手指和連接墊，其下表面係設置第一銲錫球墊； 一第一半導體晶片，係設置於第一基板之上表面，並且具有與該第一焊手指電性連接之第一銲墊；及一於第一基板之上表面形成之第一封裝構件，以密封第一半導體晶片；其中該第一封裝構件當中具有多數個孔，每個孔同時使二鄰近之連接墊露出，該孔又可分別插入各彈性導電體；一堆疊於第一封裝之第二封裝，該第二封裝，包括：一第二基板，其上表面係設置第二焊手指，其下表面係設置第二銲錫球墊；一第二半導體晶片，係設置於第二基板之上表面，並且具有與第二焊手指電性連接之第二銲墊；及一第二封裝構件，係於第二基板之上表面形成，以密封第二半導體晶片；以及多數個彈性導電體，係設置於第一封裝之第一封裝構件，以電性連接第一封裝和第二封裝；其中各彈性導電體係包括一軟式電路板，而於該軟式電路板之一面形成銅圖案；其中該彈性導電體之一種配置結構係以中空圓柱狀捲曲，將銅圖案配置於一圓柱體之外表面上，或具有一在反向彎曲之載面形狀。
  14. 如申請專利範圍第13項之堆疊式封裝，其又包 括：底部填充物，係形成於插入著彈性導電體之第一封裝構件之孔中。
  15. 一堆疊式封裝，包括：一第一封裝，係包括一第一半導體晶片和一密封該第一半導體晶片之第一封裝構件；一個或多個第二封裝，係堆疊於第一封裝上，各第二封裝係包括第二半導體晶片與密封該第二半導體晶片之第二封裝構件；以及彈性導電體，分別設置於第一封裝之第一封裝構件及第二封裝之各第二封裝構件(除了一或多個堆疊之第二封裝之最上者之外)，使第一封裝和第二封裝相互電性連接；其中各彈性導電體係包括一軟式電路板，而於該軟式電路板之一面形成銅圖案；其中該彈性導電體之一種配置結構係以中空圓柱狀捲曲，將銅圖案配置於一圓柱體之外表面上，或具有一在反向彎曲之截面形狀。
  16. 如申請專利範圍第15項之堆疊式封裝，其又包括：第一耦合構件，係附著於第一封裝之下表面；以及第二耦合構件，係附著於第二封裝之下表面，並且與彈性導電體電性連接。
TW099130975A 2010-04-14 2010-09-14 具有彈性導電體之堆疊式封裝 TWI485840B (zh)

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CN102222663A (zh) 2011-10-19
US8680688B2 (en) 2014-03-25
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