TWI463625B - 多晶片積體電路 - Google Patents

多晶片積體電路 Download PDF

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Publication number
TWI463625B
TWI463625B TW099138910A TW99138910A TWI463625B TW I463625 B TWI463625 B TW I463625B TW 099138910 A TW099138910 A TW 099138910A TW 99138910 A TW99138910 A TW 99138910A TW I463625 B TWI463625 B TW I463625B
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TW
Taiwan
Prior art keywords
wafer
interconnect structure
oxide
patterned metal
layer
Prior art date
Application number
TW099138910A
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English (en)
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TW201131727A (en
Inventor
Arifur Rahman
Venkatesan Murali
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Xilinx Inc
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Publication of TW201131727A publication Critical patent/TW201131727A/zh
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Publication of TWI463625B publication Critical patent/TWI463625B/zh

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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Description

多晶片積體電路
本發明概括關於積體電路，且更特別關於由多個晶粒(die)來製造大的積體電路。
針對於已知的節點技術，增大積體電路(IC,integrated circuit)尺寸典型提高可在晶片(chip)所納入的功能性。不幸的是，缺陷經常隨著晶片面積而按比例增減。大的晶片是相較於較小晶片者而更有可能納入缺陷。缺陷影響良率，且良率損失經常隨著增大晶片尺寸而提高。已經開發種種技術以提供大IC至期望良率程度。
提供大IC的一種方式是從在矽置入件上的多個較小IC(晶粒)來構成大IC。矽置入件是本質為基板，在矽置入件已經處理以提供金屬接線與接點之後，晶粒是覆晶式接合到矽置入件。舉例來說，如通稱為“後端處理”，矽晶圓是經製造以形成一或多個矽置入件，其具有連接到通孔的數個圖型化金屬層與中間絕緣層。習知之導電通孔通過絕緣層而與圖型化金屬層連接在一起，且晶粒是以微凸塊陣列而物性地且電性地連接到置入件。
此等圖型化金屬層提供對IC晶粒的高密度互連圖型(pattern)。矽置入件是將細間距的晶粒連接到置入件相對面上的較粗的凸塊陣列，且提供在晶粒之間的互連。導電貫穿矽通孔(TSV,through-silicon via)延伸通過矽置入件以將晶粒電氣連接到矽置入件相對面上的凸塊陣列。此凸塊陣列是被用以將大IC電氣且機械連接到圖型化電路板或封裝基板。
不幸的是，要製造導電TSV是相當昂貴的且諸如電鍍TSV之對於TSV的一些技術引入顯著的處理延遲。舉例來說，貫穿電鍍TSV的使用可能對大IC的處理流程增加二到三個小時。
避免先前技術的缺點來提供大IC是期望的。
一種積體電路(IC)具有：第一IC晶片(晶粒)，其被安裝在重建晶圓底座上且具有第一晶上(on-chip)互連結構；及第二IC晶片，其被安裝在重建晶圓底座上且具有第二晶上互連結構。第二IC晶片是以氧化物對氧化物(oxide-to-oxide)邊緣接合而被邊緣接合到第一IC晶片。被配置在第一IC晶片上且在第二IC晶片上的晶片對晶片(chip-to-chip)互連結構將第一晶上互連結構電氣耦合到第二晶上互連結構。在又一個實施例中，該IC具有在晶片對晶片互連結構上的接觸陣列，諸如：球柵陣列或凸塊陣列。在一個特定實施例中，重建晶圓底座包含造模化合物。在一個特定實施例中，氧化物對氧化物邊緣接合包含二氧化矽。
在又一個實施例中，該IC包括其安裝在重建晶圓底座上且具有第三晶上互連結構的第三IC晶片，第三晶上互連結構是透過晶片對晶片互連結構而被耦合到第一晶上互連結構或第二晶上互連結構的至少一者。
在一個特定實施例中，晶片對晶片互連結構包括第一圖型化金屬層、在第一晶上互連結構與第二晶上互連結構與第一圖型化金屬層之間的第一介電層、第二圖型化金屬層以及在第一圖型化金屬層與第二圖型化金屬層之間的第二介電層。在再一個實施例中，第一導電通孔是從第一圖型化金屬層延伸透過第一介電層到第一晶上互連結構，且第二導電通孔是從第二圖型化金屬層延伸透過第二介電層到第一圖型化金屬層。
在另一個實施例中，一種複合IC是藉由生產IC晶粒所製造，各個IC晶粒具有晶上互連結構。IC晶粒的邊緣是被拋光，且氧化物層是被沉積來塗覆IC晶粒的邊緣以形成邊緣氧化物層。在一些實施例中，即將成為複合IC周邊邊緣的晶粒之邊緣係為未拋光。
邊緣氧化物層是諸如藉由以氨溶液或氧電漿處理而被活化，且IC晶粒是以一或多個複合IC圖型而配置在邊緣接合載件上。IC晶粒為邊緣接合在一起，例如：使用低溫接合方法，其在特定方法中包括：將IC晶粒加熱到不大於攝氏250度的溫度。力量是被選用式施加在邊緣接合過程期間以使IC晶粒保持為彼此接觸。
重建晶圓底座是形成在IC晶粒上以形成重建晶圓。在一個特定實施例中，重建晶圓底座是由造模化合物所作成。在重建晶圓上的晶片對晶片互連結構電氣耦合載晶互連結構。若重建晶圓具有超過一個複合IC，該等複合IC是從重建晶圓經單一化。
在一個特定實施例中，氧化物層包含沉積的二氧化矽且為以不大於攝氏450度的溫度而沉積。在一個特定實施例中，製造晶片對晶片互連結構包括：在重建晶圓上形成至少二個圖型化金屬層具有中間介電層。在一個特定實施例中，中間介電層包含沉積的二氧化矽層，且二個圖型化金屬層中的第一者包含金屬鑲嵌(damascene)或雙金屬鑲嵌圖型化金屬層。
在又一個實施例中，在製造晶片對晶片互連結構之後而在使複合IC單一化之前，第一接觸陣列(例如：球柵陣列或焊錫凸塊陣列)是形成在重建晶圓的第一複合IC上，且第二接觸陣列是形成在重建晶圓的第二複合IC上。在一些實施例中，在重建晶圓上的複合IC是均為相同型式(圖型)。或者是，IC晶粒是以不同圖型所配置來產生不同型式的複合IC。舉例來說，第一複數個IC晶粒是以第一複合IC圖型所配置，且第二複數個IC晶粒是以不同於第一複合IC圖型的第二複合IC圖型所配置。
圖1是根據一個實施例之IC 100的橫截面圖。該種IC包括多個晶片(晶粒) 102、104、106，其彼此為邊緣接合且被安裝在諸如矽晶圓或造模化合物的重建晶圓底座108之上。在一些實施例中，該載件是多晶或單晶矽載件。或者是，載件是由造模化合物所形成。在一個特定實施例中，在造模材料中納入矽粒子或其他粒子以改良熱膨脹匹配或導熱性。
晶粒102、104、106是諸如場可程式閘陣列(FPGA,field-programmable gate array)、處理器、特殊應用IC(ASIC,application-specific IC)、或記憶體晶片(例如：RAM)的IC。該等晶粒可為相同型式者(例如：均為FPGA晶片)或為不同型式者(例如：一些為FPGA且一些為RAM晶片)。該等晶粒是小於IC 100的IC，且將被稱作為晶粒，使得此等實際晶片在後續描述中為與較大的IC 100作區別。晶粒102、104、106已經被測試且經挑選來確保有缺陷的晶粒不會被使用在IC 100中，且為以氧化物對氧化物接合110而邊緣接合在一起。氧化物對氧化物接合110的厚度是為了說明而經誇大。
為了便於討論，晶粒102、104、106及IC 100的頂面將指主要處理表面(即：圖型化金屬互連層與中間介電層為以通稱為後端IC製造順序者而被形成在其上的表面，亦被稱為面)。該等晶粒及IC的底面將指晶粒電路為形成在其上的矽晶圓背面。舉例來說，晶粒102的底面112是被附接到重建晶圓底座108。如在IC晶片製造技術中為通常已知，晶粒102的晶上互連結構114已使用一連串的圖型化金屬層、中間介電層以及導電通孔而被形成在晶粒102的頂面上。舉例來說，FPGA晶粒可能具有十一個圖型化金屬層，其通常從矽晶片基板為按其順序所描述(例如：M1、M2、...、M11)。晶上互連結構115、117亦已經被形成在其他晶粒104、106的頂面上。
晶片對晶片互連結構118是在晶粒102、104、106已經邊緣接合且牢固到重建晶圓底座108之後而被形成在複合IC之上。晶片對晶片互連結構118包括第二組的圖型化金屬層119、121、中間介電層123、125以及通孔131。圖型化金屬層119、121是為了清楚說明而顯示為整層。在一個特定實施例中，使用金屬鑲嵌或雙金屬鑲嵌、或對於熟悉後端晶圓處理技術人士為已知的諸多其他技術來形成圖型化金屬層。在一個特定實施例中，晶片對晶片互連結構包括四個圖型化金屬層(例如：M12-M14)具有中間介電層。晶片對晶片互連結構118是與球塊或凸塊陣列122為介面連接，球塊或凸塊陣列122提供電氣連接到IC 100的晶粒102、104、106。舉例來說，IC 100可為覆晶式接合到印刷接線板或到封裝基板或載件(未顯示)。
在示範實施例中，二氧化矽是使用諸如化學氣相沉積技術的低溫(低於攝氏450度且或者是低於約攝氏400度)沉積技術而被沉積在晶粒的拋光邊緣上。使用低溫的沉積技術允許在沒有損壞晶片內金屬層的情況下而處理晶粒。已知數種二氧化矽處理，其形成保形的(conformal)二氧化矽層，基本為以二氧化矽層覆蓋該等晶粒。適用於一個實施例的典型二氧化矽層厚度是大約數微米。在上方金屬層中(例如：在M11到M14圖型化金屬層中)的接線寬度是典型為數個微米的間距。
圖2是根據一個實施例在製造IC的步驟中之具有沉積氧化物層126的晶粒102、104、106的側視圖。氧化物層126是典型為在約1微米與約3微米厚之間的一層二氧化矽。該等晶粒是頂面朝下置放在沉積處理載件127之上且具有在晶粒間的充分間距以允許沉積氧化物塗覆該等晶粒的邊緣128、130。
晶粒102、104、106是被製造在(未顯示的)一或多個半導體基板(晶圓)上且藉由鋸切或其他技術而被單一化。個別晶粒的邊緣是在單一化後而選用式拋光來改良晶粒邊緣的品質以供後續的氧化物沉積及邊緣接合。單一化可能產生具有碎屑或突出的晶粒邊緣，且拋光可改良表面平滑度與晶粒邊緣的垂直性。在將氧化物層126沉積在晶粒102、104的背面132、134與邊緣128、130之後，氧化物層是使用氨基溶液或諸如電漿活化或微洗滌技術的其他適合技術而選用式活化以利於低溫的氧化物對氧化物接合。在又一個實施例中，沉積氧化物層是從晶粒背面所移除。舉例來說，用於移除此背面氧化物的適合技術包括各向同性電漿蝕刻技術。移除背面氧化物降低晶片彎曲且可改良在複合IC中的晶粒的熱耦合。
圖3是在邊緣接合載件136之上的晶粒102、104、106、142、144、146的側視圖。晶粒102、104、106、142、144、146是頂面朝下置放在接合處理表面138之上而彼此接觸。隨著該等晶粒是針對在晶粒的氧化物塗覆邊緣之間的低溫氧化物對氧化物接合而被加熱，可選用式施加由箭頭140所代表的力量以將該等晶粒保持在一起。在一個示範實施例中，附加晶粒是遠離觀者延伸以形成磚塊狀表面的晶粒陣列(參閱例如：圖6)。還可選用式施加在平面正交方向(未顯示)的力量以網格方式將該等晶粒保持在一起。在一個實施例中，在化學活化(即：氨溶液處理)的化學汽相沉積二氧化矽之間的氧化物對氧化物接合是以在約攝氏150度與約攝氏200度之間的溫度而進行，此溫度為充分低於約攝氏400度到約攝氏450度的期望最大溫度極限。
圖4是圖3的邊緣接合晶粒為具有重建晶圓底座400的側視圖。在一個特定實施例中，造模化合物或其他材料是形成在接合晶粒上以形成重建晶圓底座400。該等晶粒的頂面是在處理表面138上為共平面。造模化合物形成其將從載件136被移除且經單一化為多個複合IC的重建晶圓。在晶片邊緣上的沉積氧化物層已經接合在一起，如由虛線402所代表。氧化物-氧化物邊緣接合是在複合IC的晶粒間提供無間隙的邊界，接著在用於晶片對晶片互連結構中的金屬線的晶粒間提供平滑的過渡。
圖5是具有用於多個複合IC的晶片對晶片互連結構501、503之重建晶圓500的側視圖。舉例來說，晶片對晶片互連結構是附加的圖型化金屬層及中間介電層，其形成在重建晶圓上以將一個晶片102的晶上互連結構114上的接點電氣耦合到另一個晶片104的晶上互連結構115。球塊或凸塊505(通稱為“焊錫球塊”或“焊錫凸塊”)的接觸陣列502、504是被形成在最後將成為複合IC者的晶片對晶片互連結構501、503之上。在一個特定實施例中，晶片對晶片互連結構501使在晶上互連結構114、115上的接點之相當細的間距轉變為在接觸陣列502中的球塊或凸塊之相當粗的間距。在重建晶圓形成凸塊後，複合IC是從重建晶圓而經單一化。複合IC是根據期望應用而進一步處理或組裝。
圖6是根據一個實施例之複合IC 600的平面圖。複合IC 600是為了說明而顯示為不具有晶片對晶片互連結構或球柵陣列。晶粒102、104、106、602、604、606以氧化物對氧化物接合608而為邊緣接合在一起。晶粒數目是僅為示範性質。替代的複合IC具有較多或較少個晶粒。在替代實施例中，並非所有在複合IC之上的晶粒均為相同尺寸。該等晶粒是均為相同型式的IC晶片(例如：六個FPGA)、或者是不同型式的IC晶片(例如：一或多個FPGA、數位訊號處理器、或記憶體晶片)。
圖7是根據一個實施例之製造積體電路的方法700的流程圖。一或多個晶圓是經製造、測試及挑選以產生已知良好的IC晶粒(步驟702)。在一些實施例中，IC晶粒均為相同型式的IC。舉例來說，晶粒均為FPGA。在替代實施例中，不同型式的IC被納入在晶粒中。舉例來說，晶粒可能包括FPGA與記憶體IC(例如：RAM)。在一些實施例中，一些晶粒是使用第一型式的製程(例如：矽CMOS製程)所作成，而其他晶粒是使用不同型式的製程(例如：SiGe晶圓製程、類比或混合訊號IC製程、或記憶體IC製程，諸如：快閃記憶體IC、OTP記憶體IC、NV記憶體IC、或ROM)所作成。根據實施例的複合IC可利用不同型式的IC晶粒，其中種種晶粒是針對種種參數為最佳化。舉例來說，一個晶粒可能是針對SRAM功能性為最佳化，而另一個晶粒是針對邏輯功能性為最佳化。
晶粒邊緣是經選用式拋光(步驟704)。在一個特定實施例中，使用習用的單一化後邊緣拋光技術。晶粒邊緣是以沉積氧化物層所塗覆(步驟706)。在一個特定實施例中，沉積氧化物層是使用不超過約攝氏450度的保形沉積技術所沉積。在一個特定實施例中，沉積氧化物層是在約1微米與約3微米厚之間的二氧化矽。或者使用較厚的氧化物層。各個IC不必具有相同的邊緣氧化物厚度。晶粒是典型面對朝下置放在沉積載件上且沉積氧化物層是經選用式從晶粒背面所移除。塗覆邊緣的沉積氧化物層(“邊緣氧化物”)經活化以促進氧化物對氧化物邊緣接合(步驟708)。在一個特定實施例中，使用氨溶液技術來使邊緣氧化物活化。晶粒是根據複合IC設計在邊緣接合載件上以選擇圖型或順序而配置為面對朝下彼此接觸(步驟710)。舉例來說，複合IC可能經設計具有在二個FPGA晶粒之間的RAM晶粒。晶粒是配置在載件上，使得重建晶圓具有其形成複合IC的晶粒的期望圖型。在一些實施例中，數種不同型式的複合IC是被配置在單一個重建晶圓上。在邊緣接合載件上的晶粒是經加熱以將晶粒邊緣接合在一起(步驟712)。邊緣接合使用氧化物對氧化物接合，其在一個特定實施例為發生在小於約攝氏250度的溫度。在氧化物對氧化物接合過程期間可選用式施加力量以使晶粒保持為彼此接觸。
造模化合物是被形成在邊緣接合載件上的晶粒背面之上以形成重建晶圓底座(步驟714)。造模化合物是在半導體製造及封裝技術為眾所週知。重建晶圓是從邊緣接合載件所移除(步驟716)且重建晶圓的正面是經處理以附加晶片對晶片互連結構(步驟718)，其在一個特定實施例為一連串的圖型化金屬層、中間絕緣層、以及在圖型化金屬層與晶上接點之間的導電通孔。在一個特定實施例中，晶片對晶片互連結構包括四個圖型化金屬層。在一個特定實施例中，晶片對晶片互連結構是被耦合到其具有約30微米到約50微米的接點間距之晶片。複合IC的頂層互連間距是典型為約150微米到約200微米；然而，此等尺度僅為示範性質。典型而言，並非所有在晶粒階層的微凸塊接點均為暴露到頂層。舉例來說，晶片可能具有數千到數萬個晶片對晶片連接，且包括約五千到約一萬個頂層凸塊(電氣接點)。焊錫球塊或凸塊是經選用式形成在重建晶圓上(步驟720)，且從重建晶圓而使複合IC為單一化(步驟722)。
圖8是根據一個實施例之用於複合IC的IC晶片800的平面圖。此IC晶片是FPGA，其具有邊緣氧化物層888，氧化物層888是用以形成與在邊緣接合的複合IC中的一或多個其他IC晶片的氧化物對氧化物邊緣接合。納入FPGA的實施例包括其具有不同型式FPGA的複合IC，諸如：高性能FPGA是結合低成本FPGA，或者在複合IC內的不同FPGA是針對於不同功能性為最佳化。舉例來說，在複合IC中的一個FPGA是針對於記憶體性能為最佳化且另一個FPGA是針對於邏輯/DRAM設計規則為最佳化。其他實施例包括與其他型式的晶片作結合的FPGA，其他型式的晶片是諸如ROM晶片、SRAM晶片、或微處理器晶片。在特定實施例中，複合IC是本質為如同FPGA而操作。
FPGA架構包括大量不同的可程式磚塊(tile)，其包括多十億位元收發器(MGT,multi-gigabit transceiver) 801、可組態邏輯方塊(CLB,configurable logic block) 802、隨機存取記憶體方塊(BRAM,random access memory block) 803、輸入/輸出方塊(IOB,input/output block) 804、組態與時脈邏輯(CONFIG/CLOCK,configuration and clocking logic) 805、數位訊號處理方塊(DSP,digital signal processing block) 806、特定輸入/輸出方塊(I/O) 807(例如：組態埠與時脈埠)、及其他可程式邏輯808，諸如：數位時脈管理器、類比到數位轉換器、系統監視邏輯、等等。一些FPGA還包括專屬處理器方塊(PROC) 810。
在一些FPGA中，各個可程式磚塊包括可程式互連元件(INT) 811，其具有往返在各個相鄰磚塊中的對應互連元件的標準化連接。因此，一起被採取的可程式互連元件實施對於圖示FPGA的可程式互連結構。可程式互連元件(INT)811還包括往返在相同磚塊內的可程式邏輯元件的連接，如由圖8的頂部所包括的實例所示。
舉例來說，CLB 802可包括可組態邏輯元件(CLE,configurable logic element) 812，其可被程式規劃為加上單一個可程式互連元件(INT) 811來實施使用者邏輯。除了一或多個可程式互連元件之外，BRAM 803還可包括BRAM邏輯元件(BRL,BRAM logic element) 813。典型而言，納入在一個磚塊中的互連元件數目是取決於磚塊高度。在圖繪的實施例中，BRAM磚塊具有如同四個CLB的相同高度，但亦可使用其他數目(例如：五個)。除了適當數目個可程式互連元件之外，DSP磚塊806還可包括DSP邏輯元件(DSPL,DSP logic element) 814。舉例來說，除了一個實例的可程式互連元件(INT) 811之外，IOB 804還可包括二個實例的輸入/輸出邏輯元件(IOL,input/output logic element) 815。如將為熟悉此技術人士所明瞭，例如連接到差動I/O緩衝器818的實際I/O墊是使用在種種所示邏輯方塊之上的金屬層而製造，且典型為不侷限在輸入/輸出差動I/O緩衝器818的區域。在圖繪的實施例中，接近晶粒中央的柱狀區域是用於組態、時脈、與其他控制邏輯。水平區域809是被用以將來自組態、時脈、與其他控制邏輯的總體訊號分佈到整個晶粒888的方塊。
利用圖8所示架構的一些FPGA包括附加邏輯方塊，其使構成FPGA的大部分之規則柱狀結構瓦解。附加邏輯方塊可為可程式方塊及/或專屬邏輯。舉例來說，在圖8所示的處理器方塊(PROC) 810跨越數行(column)的CLB與BRAM。
注意，圖8是意圖說明僅為一個示範的FPGA架構。在一行中的邏輯方塊數目、行的相對寬度、行的數目與順序、納入在行中的邏輯方塊型式、邏輯方塊的相對大小、在圖8頂部所包括的互連/邏輯實施是純為示範性質。舉例來說，在實際FPGA中，超過一個相鄰行的CLB是無論CLB出現在何處而典型被納入以利於使用者邏輯的有效率實施。
儘管本發明已經關連於特定實施例所描述，此等實施例的變化將對於熟悉此技術人士為顯明。舉例來說，諸如矽晶圓結合造模化合物，替代的襯底材料或襯底材料組合是經使用以從晶粒來形成重建晶圓。因此，隨附申請專利範圍的精神與範疇不應受限於前文描述。
100．．．積體電路(IC)
102、104、106．．．晶片(晶粒)
108．．．重建晶圓底座
110．．．氧化物對氧化物接合
112．．．底面
114、115、117．．．晶上互連結構
118．．．晶片對晶片互連結構
119、121．．．圖型化金屬層
122．．．球塊或凸塊陣列
123、125．．．介電層
126．．．沉積氧化物層
127．．．沉積處理載件
128、130．．．晶粒邊緣
131．．．通孔
132、134．．．背面
136．．．邊緣接合載件
138．．．接合處理表面
140．．．力量
142、144、146．．．晶片(晶粒)
400．．．重建晶圓底座
402．．．代表接合晶片邊緣的虛線
500．．．重建晶圓
501、503．．．晶片對晶片互連結構
502、504．．．接觸陣列
505．．．球塊或凸塊
600．．．複合IC
602、604、606．．．晶粒
608．．．氧化物對氧化物接合
700．．．方法的流程圖
702-722．．．方法的步驟
800．．．IC晶片
801．．．多十億位元收發器(MGT)
802．．．可組態邏輯方塊(CLB)
803．．．隨機存取記憶體方塊(BRAM)
804．．．輸入/輸出方塊(IOB)
805．．．組態與時脈邏輯(CONFIG/CLOCK)
806．．．數位訊號處理方塊(DSP)
807．．．特定輸入/輸出方塊(I/O)
808．．．其他可程式邏輯
809．．．總體訊號分佈
810．．．處理器方塊(PROC)
811．．．可程式互連元件(INT)
812．．．可組態邏輯元件(CLE)
813．．．BRAM邏輯元件(BRL)
814．．．DSP邏輯元件(DSPL)
815．．．輸入/輸出邏輯元件(IOL)
888．．．邊緣氧化物層
圖1是根據一個實施例之IC的橫截面圖。
圖2是根據一個實施例在製造IC的步驟中之具有沉積氧化物層的晶粒的側視圖。
圖3是在邊緣接合載件上的晶粒的側視圖。
圖4是圖3的邊緣接合晶粒為具有重建晶圓底座的側視圖。
圖5是具有用於多個複合IC的晶片對晶片互連結構之重建晶圓的側視圖。
圖6是根據一個實施例之複合IC的平面圖。
圖7是根據一個實施例之製造積體電路方法的流程圖。
圖8是根據一個實施例之使用於複合IC的IC晶片的平面圖。
100．．．積體電路(IC)
102、104、106．．．晶片(晶粒)
108．．．重建晶圓底座
110．．．氧化物對氧化物接合
112．．．底面
114、115、117．．．晶上互連結構
118．．．晶片對晶片互連結構
119、121．．．圖型化金屬層
122．．．球狀或凸塊陣列
123、125．．．介電層
131．．．通孔

Claims (8)

  1. 一種積體電路(IC)，其包含：第一IC晶片，其具有相對的第一和第二表面、圍繞該第一和第二表面的邊緣以及第一晶上互連結構，第一IC晶片是被安裝在重建晶圓底座上並且該第一IC晶片的該第一表面面對重建晶圓底座；第二IC晶片，其具有相對的第一和第二表面、圍繞該第一和第二表面的邊緣以及第二晶上互連結構，第二IC晶片是被安裝在該重建晶圓底座上並且該第二IC晶片的該第一表面面對該重建晶圓底座；其中，該第一IC晶片具有第一氧化物層在該第一IC晶片之至少一個邊緣上，該第一氧化物層從該第一IC晶片的第一表面延伸至該第一IC晶片的該第二表面，該第二IC晶片具有第二氧化物層在該第二IC晶片之至少一個邊緣上，該第二氧化物層從該第二IC晶片的第一表面延伸至該第二IC晶片的該第二表面，並且該第一氧化物層和該第二氧化物層係彼此接觸且接合在一起；及晶片對晶片互連結構，其配置在第一IC晶片上及第二IC晶片上；其中該晶片對晶片互連結構將第一晶上互連結構電氣耦合到第二晶上互連結構。
  2. 如申請專利範圍第1項之IC，其更包含：在該晶片對晶片互連結構上的接觸陣列。
  3. 如申請專利範圍第2項之IC，其中該接觸陣列是球 柵陣列或凸塊陣列。
  4. 如申請專利範圍第1項之IC，其中該重建晶圓底座包含造模化合物。
  5. 如申請專利範圍第1項之IC，其中該氧化物層包含二氧化矽。
  6. 如申請專利範圍第1項之IC，其更包含：安裝在該重建晶圓底座上且具有第三晶上互連結構的第三IC晶片；其中第三晶上互連結構是透過該晶片對晶片互連結構而被耦合到第一晶上互連結構或第二晶上互連結構的至少一者。
  7. 如申請專利範圍第1項之IC，其中該晶片對晶片互連結構包含：第一圖型化金屬層；第一介電層，其在第一晶上互連結構與第二晶上互連結構與第一圖型化金屬層之間；第二圖型化金屬層；及第二介電層，其在第一圖型化金屬層與第二圖型化金屬層之間。
  8. 如申請專利範圍第7項之IC，其更包含：第一導電通孔，其從第一圖型化金屬層延伸透過第一介電層到第一晶上互連結構；及第二導電通孔，其從第二圖型化金屬層延伸透過第二介電層到第一圖型化金屬層。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110221053A1 (en) * 2010-03-11 2011-09-15 Qualcomm Incorporated Pre-processing to reduce wafer level warpage
US9269610B2 (en) * 2014-04-15 2016-02-23 Qualcomm Incorporated Pattern between pattern for low profile substrate
US9881896B2 (en) 2015-12-17 2018-01-30 International Business Machines Corporation Advanced chip to wafer stacking
CN109637564A (zh) 2018-12-20 2019-04-16 惠州Tcl移动通信有限公司 具有多存储晶粒储存装置及识别方法
US11515225B2 (en) 2020-09-10 2022-11-29 Rockwell Collins, Inc. Reconstituted wafer including mold material with recessed conductive feature
US11605570B2 (en) 2020-09-10 2023-03-14 Rockwell Collins, Inc. Reconstituted wafer including integrated circuit die mechanically interlocked with mold material

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037379A1 (en) * 2005-08-11 2007-02-15 Ziptronix 3D IC method and device
US20070096306A1 (en) * 2005-10-05 2007-05-03 Sony Corporation Semiconductor device and fabrication method thereof
US20090140421A1 (en) * 2005-10-29 2009-06-04 Stats Chippac, Ltd. Semiconductor Device and Method of Making Integrated Passive Devices

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2985484B2 (ja) * 1992-03-19 1999-11-29 株式会社日立製作所 半導体装置とその製造方法
US6379998B1 (en) * 1986-03-12 2002-04-30 Hitachi, Ltd. Semiconductor device and method for fabricating the same
JPH05335529A (ja) * 1992-05-28 1993-12-17 Fujitsu Ltd 半導体装置およびその製造方法
US6020633A (en) * 1998-03-24 2000-02-01 Xilinx, Inc. Integrated circuit packaged for receiving another integrated circuit
US6440849B1 (en) * 1999-10-18 2002-08-27 Agere Systems Guardian Corp. Microstructure control of copper interconnects
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TWI234253B (en) * 2002-05-31 2005-06-11 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP3938759B2 (ja) * 2002-05-31 2007-06-27 富士通株式会社 半導体装置及び半導体装置の製造方法
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
US7183643B2 (en) * 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
JP4370990B2 (ja) * 2004-07-12 2009-11-25 エプソントヨコム株式会社 圧電発振器及びその製造方法
JP2007048958A (ja) * 2005-08-10 2007-02-22 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7576435B2 (en) * 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7687895B2 (en) * 2007-04-30 2010-03-30 Infineon Technologies Ag Workpiece with semiconductor chips and molding, semiconductor device and method for producing a workpiece with semiconductors chips
US20090057885A1 (en) * 2007-08-30 2009-03-05 Infineon Technologies Ag Semiconductor device
US8136071B2 (en) * 2007-09-12 2012-03-13 Neal Solomon Three dimensional integrated circuits and methods of fabrication
US7518398B1 (en) * 2007-10-04 2009-04-14 Xilinx, Inc. Integrated circuit with through-die via interface for die stacking
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device
US7619441B1 (en) * 2008-03-03 2009-11-17 Xilinx, Inc. Apparatus for interconnecting stacked dice on a programmable integrated circuit
US8008764B2 (en) * 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
US7981730B2 (en) * 2008-07-09 2011-07-19 Freescale Semiconductor, Inc. Integrated conformal shielding method and process using redistributed chip packaging

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037379A1 (en) * 2005-08-11 2007-02-15 Ziptronix 3D IC method and device
US20070096306A1 (en) * 2005-10-05 2007-05-03 Sony Corporation Semiconductor device and fabrication method thereof
US20090140421A1 (en) * 2005-10-29 2009-06-04 Stats Chippac, Ltd. Semiconductor Device and Method of Making Integrated Passive Devices

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