WO2024051124A1 - 一种多层高带宽存储器及其制造方法 - Google Patents

一种多层高带宽存储器及其制造方法 Download PDF

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Publication number
WO2024051124A1
WO2024051124A1 PCT/CN2023/080074 CN2023080074W WO2024051124A1 WO 2024051124 A1 WO2024051124 A1 WO 2024051124A1 CN 2023080074 W CN2023080074 W CN 2023080074W WO 2024051124 A1 WO2024051124 A1 WO 2024051124A1
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layer
bandwidth memory
metal connection
connection layer
memory chip
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PCT/CN2023/080074
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English (en)
French (fr)
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吕锡明
苏梅英
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华进半导体封装先导技术研发中心有限公司
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Publication of WO2024051124A1 publication Critical patent/WO2024051124A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a multi-layer high-bandwidth memory and a manufacturing method thereof.
  • High Bandwidth Memory is a CPU/GPU memory chip, namely RAM.
  • HBM includes multiple vertically stacked DDR chips, which are connected to the CPU or GPU through an ultra-fast interconnect called an interposer or directly connected to the substrate, thereby realizing a large-capacity, high-bit-width DDR combination array.
  • the HBM is packaged and assembled into a specific module together with the CPU and GPU, and then connected to the circuit board.
  • each HBM usually also needs to be configured with a logic chip to perform DDR memory management tasks.
  • stacked DDR chips and logic chips are usually packaged separately and then attached to the substrate. The overall packaging efficiency is low.
  • the present invention on the one hand provides a multi-layer high-bandwidth memory, which integrates high-bandwidth memory and logic chips on a wafer.
  • the multi-layer high-bandwidth memory includes:
  • At least one high-bandwidth memory chip module including N vertically stacked high-bandwidth memory wafers
  • a first metal connection layer is provided on the surface of the high-bandwidth memory chip module and is electrically connected to the high-bandwidth memory chip module;
  • a second metal connection layer is provided on the surface of the logic chip and is electrically connected to the logic chip;
  • a first dielectric layer covering the surfaces and gaps of the first metal connection layer and the second metal connection layer, but exposing at least one external pad of the first metal connection layer and the second metal connection layer;
  • a second dielectric layer is provided below the first metal connection layer and the second metal connection layer;
  • a surface passivation layer is provided on the first surface of the plastic sealing layer, but exposes at least one external pad of the first metal connection layer and the second metal connection layer;
  • a redistribution layer is provided on the surface of the surface passivation layer and is electrically connected to the first metal connection layer and the second metal connection layer;
  • a bearing layer is provided on the second surface of the plastic sealing layer.
  • the high-bandwidth memory wafers in each of the high-bandwidth memory chip modules are connected through micro-bumps.
  • the number of high-bandwidth memory wafers in each of the high-bandwidth memory chip modules is the same or different.
  • the number of high-bandwidth memory wafers in each high-bandwidth memory chip module is 1 to 4.
  • the multi-layer high-bandwidth memory structure includes a plurality of the logic chips.
  • the high-bandwidth memory chip modules and the logic chips are arranged in a staggered manner.
  • the first metal connection layer implements a fan-out function for pins of the high-bandwidth memory chip module.
  • the second metal connection layer implements a fan-out function for the logic chip pins.
  • Another aspect of the present invention provides a method for manufacturing a multi-layer high-bandwidth memory as described above, including:
  • first metal connection layer Cover the temporary bonding layer on the carrier chip, and form a first metal connection layer, a first dielectric layer, a second metal connection layer and a second dielectric layer thereon;
  • plastic packaging material to cover the high-bandwidth memory chip module, logic chip, first metal connection layer, first dielectric layer, second metal connection layer and second dielectric layer to form a plastic packaging layer;
  • the manufacturing method further includes performing a power-on test on the multi-layer high-bandwidth memory.
  • the invention provides a multi-layer high-bandwidth memory and a manufacturing method thereof, which innovatively adopts a fan-out embedded component packaging method (Fan-out ECP) to integrate a high-bandwidth memory (HBM) and a logic chip on a single chip.
  • Fan-out ECP fan-out embedded component packaging method
  • HBM high-bandwidth memory
  • logic chip on a single chip.
  • the storage capacity of HBM is effectively improved.
  • wafer-level bumping technology greatly improves packaging efficiency.
  • Figure 1 shows a cross-sectional schematic diagram of a multi-layer high-bandwidth memory according to an embodiment of the present invention
  • Figure 2 shows a schematic top view of a multi-layer high-bandwidth memory according to an embodiment of the present invention
  • 3A to 3G illustrate cross-sectional schematic diagrams of a process of forming a multi-layer high-bandwidth memory according to embodiments of the present invention.
  • FIG. 4 shows a flow chart of forming a three-dimensional stacked packaging structure according to an embodiment of the present invention.
  • HBM high-bandwidth memory
  • the present invention provides a multi-layer high-bandwidth memory and a manufacturing method thereof, which utilizes fan-out embedded component packaging
  • Fan-out ECP can integrate HBM chips and logic chips at the same time. On the one hand, it can achieve the same function while improving packaging efficiency. On the other hand, it also allows the multi-layer high-bandwidth memory to be Achieve mass production.
  • FIG. 1 shows a cross-sectional schematic diagram of a multi-layer high-bandwidth memory according to an embodiment of the present invention.
  • a multi-layer high-bandwidth memory includes a high-bandwidth memory chip module 101 and a logic chip 102.
  • the high-bandwidth memory chip module 101 and the logic chip 102 are integrated on a wafer.
  • the multi-layer high-bandwidth memory includes K high-bandwidth memory chip modules and L logic chips, where K and L are both natural numbers.
  • Figure 2 shows a schematic top view of a multi-layer high-bandwidth memory according to an embodiment of the present invention. As shown in Figure 2, the K high-bandwidth memory chip modules and L logic chips are staggeredly distributed on the wafer, that is, between the carrier layer 105 superior.
  • the high-bandwidth memory chip module 101 and the logic chip 102 first realize the fan-out function of the pins through the first metal connection layer 111 and the second metal connection layer 121 respectively, and then further pass through the rewiring layer. 131 realizes electrical and/or signal interconnection, and finally realizes electrical connection with external components or structures through bumps 132 .
  • any of the high-bandwidth memory chip modules 101 includes N vertically stacked high-bandwidth memory wafers, where N is a natural number.
  • the N high-bandwidth memory wafers are stacked and formed through a vertical 3D TSV stacking process.
  • One high-bandwidth memory wafer can be regarded as a storage area, and each storage area is connected by micro-protrusions. Blocks (uBumps) are connected.
  • the number of high-bandwidth memory wafers contained in different high-bandwidth memory chip modules may be the same or different, but preferably, the number of high-bandwidth memory wafers contained in each high-bandwidth memory chip module
  • the number is 1 to 4, and the value range of N is 1 to 4.
  • the surface of the high-bandwidth memory chip module 101 is provided with a first metal connection layer 111, which is electrically connected to the high-bandwidth memory chip module 101 to enable the high-bandwidth memory chip module 101 to be connected. Fan-out function of the feet.
  • the material of the first metal connection layer 111 may be copper metal, aluminum metal, tungsten metal, etc.
  • the first metal connection layer 111 is formed on the surface of the second dielectric layer 162 .
  • the surface of the first metal connection layer 111 is also covered with a first dielectric layer 161.
  • the first dielectric layer 161 covers the surface and gaps of the first metal connection layer 111, but exposes the first metal connection layer. At least one external pad serves as insulation protection.
  • the materials of the first dielectric layer 161 and the second dielectric layer 162 may be organic materials such as resin and PI, or inorganic insulating materials such as silicon oxide and silicon nitride.
  • the logic chip 102 is mainly used to implement control functions such as logic operations on the high-bandwidth memory chip module.
  • a second metal connection layer 121 is provided on the surface of the logic chip 102 and is electrically connected to the logic chip 102 to realize the fan-out function for the pins of the logic chip 102 .
  • the material of the second metal connection layer 121 may be copper metal, aluminum metal, tungsten metal, etc.
  • the second metal connection layer 121 is formed on the surface of the second dielectric layer 162 .
  • the surface of the second metal connection layer 121 is also covered with a first dielectric layer 161.
  • the first dielectric layer 161 covers the surface and gaps of the second metal connection layer 121, but exposes the second metal connection layer. At least one external pad serves as insulation protection.
  • the high-bandwidth memory chip module 101 , logic chip 102 , first metal connection layer 111 , first dielectric layer 161 , second metal connection layer 121 and second dielectric layer 162 are wrapped in a plastic encapsulation layer 104 middle.
  • the plastic sealing layer 104 is made of resin material.
  • the redistribution layer 131 is formed on the first surface of the plastic encapsulation layer 104 and is electrically connected to the first metal connection layer 111 and the second metal connection layer 121 .
  • the rewiring layer 131 The material can be copper metal, aluminum metal, tungsten metal, etc. In one embodiment of the present invention, the rewiring layer 131 may have one or more layers, and the outermost layer may also be provided with a pad for connection with an external chip, chipset or circuit.
  • the first surface of the plastic sealing layer 104 is also provided with a surface passivation layer 133 , which covers the first surface of the plastic sealing layer 104 but exposes the first metal connection layer 111 and the second metal layer 111 .
  • a surface passivation layer 133 covers the first surface of the plastic sealing layer 104 but exposes the first metal connection layer 111 and the second metal layer 111 .
  • At least one external pad of the connection layer 121 enables the redistribution layer 131 to be electrically connected to the first metal connection layer and the second metal connection layer.
  • a load-bearing layer 105 is provided on the second surface of the plastic sealing layer 104 , and the thickness of the load-bearing layer 105 can be set according to actual requirements.
  • the carrier layer 105 is obtained by wafer thinning.
  • the bumps 132 are formed on the external pads of the redistribution layer 131 .
  • FIGS. 3A to 3N and FIG. 4 show a schematic cross-sectional view of the process of forming a multi-layer high-bandwidth memory according to an embodiment of the present invention
  • FIG. 4 shows a flow chart of forming a multi-layer high-bandwidth memory according to an embodiment of the present invention.
  • a manufacturing method of a multi-layer high-bandwidth memory as described above includes:
  • the high-bandwidth memory chip module 101 is formed.
  • multiple HBM wafers 1011 are stacked through vertical 3D TSV, and each HBM wafer is connected through uBump 1012;
  • a fan-out structure is formed.
  • the temporary bonding layer 002 is covered on the carrier chip 001, where the carrier chip 001 can be a carrier material such as a wafer or glass; the temporary bonding layer 002 can be detachably bonded by heating, illumination or other bonding materials.
  • a second dielectric layer 162 is formed according to the preset positions of the high-bandwidth memory chip module and logic chip.
  • the material of the second dielectric layer 162 can be organic materials such as resin, PI, or silicon oxide.
  • first metal connection layer 111 silicon nitride and other inorganic insulating materials
  • one or more layers of conductive materials are respectively formed on the second dielectric layer 162, and the areas that are not required to be conductive are removed through photolithography and etching techniques to form the first metal connection layer 111 and
  • the second metal connection layer 121 forms a first dielectric layer 161 on the first metal connection layer 111 and the second metal connection layer 121. Part of the first dielectric layer 161 is removed through photolithography and etching techniques to expose at least one first metal layer.
  • Connection layer 111 and the second gold Belonging to the external pads of the connection layer 121, the high-bandwidth memory chip module 101 and the logic chip 102 are respectively mounted on the preset external pads of the first metal connection layer 111 and the second metal connection layer 121;
  • a plastic sealing layer is formed.
  • the plastic encapsulation layer 104 covers the high-bandwidth memory chip module 101, the logic chip 102, the first metal connection layer 111, the first dielectric layer 161, the second metal connection layer 121 and the second dielectric layer 162;
  • a carrier layer is formed.
  • a carrier chip 105 is loaded on the second surface of the plastic sealing layer 104, that is, the side surface away from the temporary bonding layer 002.
  • the carrier chip 105 may be a carrier material such as a wafer or glass;
  • step 405 the carrier chip and the temporary bonding layer are removed.
  • the bonding can be debonded by heating, laser irradiation, etc., and the temporary bonding layer 002 can be completely removed by a cleaning process;
  • a rewiring structure is formed.
  • a surface passivation layer 133 is formed on the second surface of the plastic sealing layer 104, and a portion of the surface passivation layer 133 is removed to expose at least one external pad of the first metal connection layer 111 and the second metal connection layer 121.
  • a rewiring layer 131 is formed on the surface passivation layer 133 to electrically connect it to the first metal connection layer 111 and the second metal connection layer 121 , and bumps are formed on one or more external pads of the rewiring layer. Point 132; In one embodiment of the present invention, after the rewiring structure is completed, a power-on test of the connection structure can also be performed; and
  • step 407 as shown in Figure 3G, the backside is thinned.
  • the carrier sheet 105 is thinned to a certain thickness to form a final product.
  • the invention provides a multi-layer high-bandwidth memory and a manufacturing method thereof, which innovatively adopts a fan-out embedded component packaging method (Fan-out ECP) to integrate a high-bandwidth memory (HBM) and a logic chip on a single chip.
  • Fan-out ECP fan-out embedded component packaging method
  • HBM high-bandwidth memory
  • logic chip on a single chip.
  • the storage capacity of HBM is effectively improved.
  • wafer-level bumping technology greatly improves packaging efficiency.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

本发明提供一种多层高带宽存储器，采用扇出型嵌入式元器件封装方式将高带宽存储器与逻辑芯片集成于一片晶圆上，提升了存储能力，并通过晶圆级凸点工艺使得封装效率得到提升。其包括：至少一个高带宽存储器芯片模块，每个高带宽存储器芯片模块包括N个垂直堆叠的高带宽存储器晶圆，且表面设置有与其电连接的第一金属连接层；逻辑芯片，其表面设置有与其电连接的第二金属连接层；塑封层，包覆高带宽存储器芯片模块、逻辑芯片、第一金属连接层、以及第二金属连接层，其第一表面设置有与第一、第二金属连接层电连接的重布线层及表面钝化层，第二表面设置有承载层；以及与重布线层电连接的凸点。

Description

一种多层高带宽存储器及其制造方法 技术领域
本发明涉及半导体技术领域，特别涉及一种多层高带宽存储器及其制造方法。
背景技术
高带宽存储器(High Bandwidth Memory，HBM)是一种CPU/GPU内存芯片，即RAM。HBM包括垂直堆叠的多个DDR芯片，所述DDR芯片通过称为中介层(Interposer)的超快速互联方式连接至CPU或GPU或者直接与基板相连，进而实现大容量，高位宽的DDR组合阵列。
通常，所述HBM会与CPU、GPU一起封装组装成特定模块，然后连接至电路板上。在实际应用中，每个HBM中通常还需要配置一个逻辑芯片以执行DDR存储器管理任务。传统的HBM封装中，通常是将堆叠的DDR芯片与逻辑芯片各自单独封装后在贴到基板上，整体封装效率较低。
发明内容
针对现有技术中的部分或全部问题，为了在保证功能的前提下提高封装效率，本发明一方面提供一种多层高带宽存储器，其将高带宽存储器与逻辑芯片集成于一片晶圆上，所述多层高带宽存储器包括：
至少一个高带宽存储器芯片模块，包括N个垂直堆叠的高带宽存储器晶圆；
逻辑芯片；
第一金属连接层，设置于所述高带宽存储器芯片模块的表面，与所述高带宽存储器芯片模块电连接；
第二金属连接层，设置于所述逻辑芯片的表面，与所述逻辑芯片电连接；
第一介质层，覆盖所述第一金属连接层及第二金属连接层的表面和间隙，但露出所述第一金属连接层及第二金属连接层的至少一个外接焊盘；
第二介质层，设置于所述第一金属连接层及第二金属连接层的下方；
塑封层，包覆所述高带宽存储器芯片模块、逻辑芯片、第一金属连接层、第一介质层、第二金属连接层以及第二介质层；
表面钝化层，设置于所述塑封层的第一表面，但露出所述第一金属连接层及第二金属连接层的至少一个外接焊盘；
重布线层，设置于所述表面钝化层表面，与所述第一金属连接层及第二金属连接层电连接；
凸点，电连接至所述重布线层；以及
承载层，设置于所述塑封层的第二表面。
进一步地，每个所述高带宽存储器芯片模块中的高带宽存储器晶圆之间通过微凸块相连。
进一步地，每个所述高带宽存储器芯片模块中的高带宽存储器晶圆数量相同或不同。
进一步地，每个所述高带宽存储器芯片模块中的高带宽存储器晶圆数量为1至4个。
进一步地，所述多层高带宽存储器结构包括多个所述逻辑芯片。
进一步地，所述高带宽存储器芯片模块与所述逻辑芯片交错布置。
进一步地，所述第一金属连接层实现对所述高带宽存储器芯片模块引脚的扇出功能。
进一步地，所述第二金属连接层实现对所述逻辑芯片引脚的扇出功能。
本发明另一方面提供一种如前所述的多层高带宽存储器的制造方法，包括：
形成高带宽存储器芯片模块；
在载片上覆盖临时键合层，并在其上形成第一金属连接层、第一介质层、第二金属连接层及第二介质层；
将所述高带宽存储器芯片模块及逻辑芯片分别贴装至所述第一金属连接层及第二金属连接层；
采用塑封材料包覆所述高带宽存储器芯片模块、逻辑芯片、第一金属连接层、第一介质层、第二金属连接层以及第二介质层，形成塑封层；
在所述塑封层的表面形成承载载片；
去除所述临时键合层及载片；
在所述塑封层的第二表面形成表面钝化层，去除部分表面钝化层，以暴露第一金属连接层及第二金属连接层的至少一个外接焊盘；
在所述表面钝化层上形成重布线层，使其与所述第一金属连接层及第二金属连接层电连接；
在一个或多个所述重布线层的外接焊盘上制作凸点；以及
减薄所述承载载片。
进一步地，所述制造方法还包括，对所述多层高带宽存储器进行通电测试。
本发明提供的一种多层高带宽存储器及其制造方法，创新性地采用了扇出型嵌入式元器件封装方式(Fan-out ECP)将高带宽存储器(HBM)与逻辑芯片集成于一片晶圆上，有效提升了HBM的存储能力，此外，其采用晶圆级凸点工艺(bumping)使得封装效率得到了较大的提升。
附图说明
为进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出本发明一个实施例的多层高带宽存储器的横截面示意图；
图2示出本发明一个实施例的多层高带宽存储器的俯视图示意图；
图3A至图3G示出根据本发明的实施例形成多层高带宽存储器的过程的剖面示意图；以及
图4示出根据本发明的实施例形成三维叠层型封装结构的流程图。
具体实施方式
以下的描述中，参考各实施例对本发明进行描述。然而，本领域的技术人员将认识到可在没有一个或多个特定细节的情况下或者与其它替换和/或附加方法、材料或组件一起实施各实施例。在其它情形中，未示出或未详细描述公知的结构、材料或操作以免模糊本发明的发明点。类似地，为了解释的目的，阐述了特定数量、材料和配置，以便提供对本发明的实施例的全面理解。然而，本发明并不限于这些特定细节。 此外，应理解附图中示出的各实施例是说明性表示且不一定按正确比例绘制。
在本说明书中，对“一个实施例”或“该实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。在本说明书各处中出现的短语“在一个实施例中”并不一定全部指代同一实施例。
需要说明的是，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了阐述该具体实施例，而不是限定各步骤的先后顺序。相反，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。
传统的高带宽存储器(High Bandwidth Memory，HBM)通常是将HBM芯片与逻辑芯片各自单个封装后贴到基板之上，当需要大容量HBM芯片时，这种封装形式的效率较低。为了在效提高封装效率的同时，保证甚至额外增加存储芯片的数量以实现更高的单元存储能力，本发明提供一种多层高带宽存储器及其制造方法，利用扇出型嵌入式元器件封装方式(Fan-out ECP)的形式可以将HBM芯片与逻辑芯片两种芯片同时整合在一起，一方面使得在实现同样功能的同时提高封装效率，另一方面还使得所述多层高带宽存储器可以实现批量生产。
下面结合实施例附图对本发明的方案做进一步描述。
图1示出本发明一个实施例的多层高带宽存储器的横截面示意图。如图1所示，一种多层高带宽存储器，其包括高带宽存储器芯片模块101以及逻辑芯片102，所述高带宽存储器芯片模块101与逻辑芯片102集成于一片晶圆上。在本发明的一个实施例中，所述多层高带宽存储器包括K个高带宽存储器芯片模块以及L个逻辑芯片，其中K、L均为自然数。图2示出本发明一个实施例的多层高带宽存储器的俯视图示意图，如图2所示，所述K个高带宽存储器芯片模块以及L个逻辑芯片交错分布于晶圆，即承载层105之上。
如图1所示，所述高带宽存储器芯片模块101与逻辑芯片102首先分别通过第一金属连接层111及第二金属连接层121实现对引脚的扇出功能，然后进一步地通过重布线层131实现电和/或信号互连，最后通过凸点132实现与外部元器件或结构的电连接。
在本发明的实施例中，任一所述高带宽存储器芯片模块101中包括 N个垂直堆叠的高带宽存储器晶圆，其中N为自然数。在本发明的一个实施例中，所述N个高带宽存储器晶圆通过垂直3D TSV堆叠工艺堆叠形成，一个高带宽存储器晶圆可被视为一个存储区域，每个存储区域之间通过微凸块(uBump)相连。在本发明的一个实施例中，不同高带宽存储器芯片模块中所包含的高带宽存储器晶圆数量可以相同或不同，但优选地，每个高带宽存储器芯片模块中所包含的高带宽存储器晶圆数量为1至4个，及所述N的取值范围为1到4。
如图1所示，所述高带宽存储器芯片模块101的表面设置有第一金属连接层111，其与所述高带宽存储器芯片模块101电连接，以实现对所述高带宽存储器芯片模块101引脚的扇出功能。在本发明的一个实施例中，所述第一金属连接层111的材料可以为铜金属、铝金属、钨金属等。所述第一金属连接层111形成于第二介质层162的表面。所述第一金属连接层111的表面还覆盖有第一介质层161，所述第一介质层161覆盖所述第一金属连接层111的表面和间隙，但露出所述第一金属连接层的至少一个外接焊盘，起到绝缘保护作用。在本发明的一个实施例中，所述第一介质层161及第二介质层162的材料可以为树脂、PI等有机材料，或者为氧化硅、氮化硅等无机绝缘材料。
所述逻辑芯片102主要用于实现对所述高带宽存储器芯片模块的逻辑运算等控制功能。所述逻辑芯片102的表面设置有第二金属连接层121，其与所述逻辑芯片102电连接，以实现对逻辑芯片102引脚的扇出功能。在本发明的一个实施例中，所述第二金属连接层121的材料可以为铜金属、铝金属、钨金属等。所述第二金属连接层121形成于第二介质层162的表面。所述第二金属连接层121的表面还覆盖有第一介质层161，所述第一介质层161覆盖所述第二金属连接层121的表面和间隙，但露出所述第二金属连接层的至少一个外接焊盘，起到绝缘保护作用。
如图1所示，所述高带宽存储器芯片模块101、逻辑芯片102、第一金属连接层111、第一介质层161、第二金属连接层121以及第二介质层162包覆于塑封层104中。在本发明的一个实施例中，所述塑封层104为树脂材料。
所述重布线层131形成于所述塑封层104的第一表面，其与所述第一金属连接层111及第二金属连接层121电连接。所述重布线层131的 材料可以为铜金属、铝金属、钨金属等。在本发明的一个实施例中，所述重布线层131可以有一层或多层，其中最外层还可以设置有焊盘，以用于和外部芯片、芯片组或电路连接。
如图1所示，所述塑封层104的第一表面还设置有表面钝化层133，其覆盖所述塑封层104的第一表面，但露出所述第一金属连接层111及第二金属连接层121的至少一个外接焊盘，使得所述重布线层131能够与所述第一金属连接层及第二金属连接层电连接。
如图1所示，所述塑封层104的第二表面设置有承载层105，所述承载层105的厚度可根据实际需求设置。在本发明的一个实施例中，所述承载层105为晶圆减薄得到。
所述凸点132形成于所述重布线层131的外接焊盘上。
应当理解的是，为了实现多种功能的同步整合，也可根据实际需求添加其他类型的芯片，所述其他类型的芯片的封装与所述逻辑芯片一致。
下面结合图3A至图3N以及图4来详细描述形成该种多层高带宽存储器的过程。图3A至图3N示出根据本发明的一个实施例形成多层高带宽存储器的过程剖面示意图；图4示出根据本发明的一个实施例形成多层高带宽存储器的流程图。如图所示，一种如前所述的多层高带宽存储器的制造方法，包括：
首先，在步骤401，如图3A所示，形成高带宽存储器芯片模块101。在本发明的一个实施例中，通过垂直3D TSV堆叠多个HBM晶圆1011，并通过uBump 1012使得每个HBM晶圆相连；
接下来，在步骤402，如图3B所示，形成扇出结构。在载片001上覆盖临时键合层002，其中，载片001可以为晶圆、玻璃等载片材料；临时粘合层002位加热、光照等可拆键合粘接材料。在所述临时键合成上根据预设的高带宽存储器芯片模块及逻辑芯片位置，形成第二介质层162，所述第二介质层162的材料可以为树脂、PI等有机材料，或者为氧化硅、氮化硅等无机绝缘材料，在所述第二介质层162上分别形成一层或多层导电材料，通过光刻和刻蚀技术去除不需导电的区域，形成第一金属连接层111以及第二金属连接层121，在第一金属连接层111以及第二金属连接层121上形成第一介质层161，通过光刻和刻蚀技术去除部分第一介质层161，暴露至少一个第一金属连接层111以及第二金 属连接层121的外接焊盘，将所述高带宽存储器芯片模块101及逻辑芯片102分别贴装至所述第一金属连接层111及第二金属连接层121预设的外接焊盘上；
接下来，在步骤403，如图3C所示，形成塑封层。塑封层104包覆所述高带宽存储器芯片模块101、逻辑芯片102、第一金属连接层111、第一介质层161、第二金属连接层121以及第二介质层162；
接下来，在步骤404，如图3D所示，形成承载层。在所述塑封层104的第二表面，即远离所述临时键合层002的一侧表面负载承载载片105，所述承载载片105可以为晶圆、玻璃等载片材料；
接下来，在步骤405，如图3E所示，去除载片及临时键合层。在本发明的一个具体实施例中，可以依据临时键合层002的特性，采用加热拆键合、激光照射拆键合等方式实现，并可进一步采用清洗工艺彻底清除掉临时键合层002；
接下来，在步骤406，如图3F所示，形成重布线结构。在所述塑封层104的第二表面形成表面钝化层133，去除部分表面钝化层133，以暴露第一金属连接层111及第二金属连接层121的至少一个外接焊盘，在所述表面钝化层133上形成重布线层131，使其与所述第一金属连接层111及第二金属连接层121电连接，在一个或多个所述重布线层的外接焊盘上制作凸点132；在本发明的一个实施例中，在重布线结构完成后，还可进行连接结构通电测试；以及
最后，在步骤407，如图3G所示，背面减薄。根据需求，将所述承载载片105减薄至一定厚度，形成最终产品。
本发明提供的一种多层高带宽存储器及其制造方法，创新性地采用了扇出型嵌入式元器件封装方式(Fan-out ECP)将高带宽存储器(HBM)与逻辑芯片集成于一片晶圆上，有效提升了HBM的存储能力，此外，其采用晶圆级凸点工艺(bumping)使得封装效率得到了较大的提升。
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。

Claims (10)

  1. 一种多层高带宽存储器，其特征在于，包括：
    至少一个高带宽存储器芯片模块，每个所述高带宽存储器芯片模块包括N个垂直堆叠的高带宽存储器晶圆，其中N为自然数；
    逻辑芯片，其被配置为控制所述高带宽存储器芯片模块；
    第一金属连接层，设置于所述高带宽存储器芯片模块的表面，与所述高带宽存储器芯片模块电连接；
    第二金属连接层，设置于所述逻辑芯片的表面，与所述逻辑芯片电连接；
    第一介质层，覆盖所述第一金属连接层及第二金属连接层的表面和间隙，但露出所述第一金属连接层及第二金属连接层的至少一个外接焊盘；
    第二介质层，设置于所述第一金属连接层及第二金属连接层的下方；
    塑封层，包覆所述高带宽存储器芯片模块、逻辑芯片、第一金属连接层、第一介质层、第二金属连接层以及第二介质层；
    表面钝化层，设置于所述塑封层的第一表面，但露出所述第一金属连接层及第二金属连接层的至少一个外接焊盘；
    重布线层，设置于所述表面钝化层表面，与所述第一金属连接层及第二金属连接层电连接；
    凸点，电连接至所述重布线层；以及
    承载层，设置于所述塑封层的第二表面。
  2. 如权利要求1所述的多层高带宽存储器，其特征在于，每个所述高带宽存储器芯片模块中的高带宽存储器晶圆之间通过微凸块相连。
  3. 如权利要求1所述的多层高带宽存储器，其特征在于，每个所述高带宽存储器芯片模块中的高带宽存储器晶圆数量相同或不同。
  4. 如权利要求1所述的多层高带宽存储器，其特征在于，每个所述高带宽存储器芯片模块中的高带宽存储器晶圆数量为1至4个。
  5. 如权利要求1所述的多层高带宽存储器，其特征在于，所述多层高带宽存储器结构包括多个所述逻辑芯片。
  6. 如权利要求5所述的多层高带宽存储器，其特征在于，所述高带宽存储器芯片模块与所述逻辑芯片交错布置。
  7. 如权利要求1所述的多层高带宽存储器，其特征在于，所述第一金属连接层实现对所述高带宽存储器芯片模块引脚的扇出功能。
  8. 如权利要求1所述的多层高带宽存储器，其特征在于，所述第二金属连接层实现对所述逻辑芯片引脚的扇出功能。
  9. 一种如权利要求1至8任一所述的多层高带宽存储器的制造方法，其特征在于，包括步骤：
    形成高带宽存储器芯片模块；
    在载片上覆盖临时键合层，并在其上形成第一金属连接层、第一介质层、第二金属连接层及第二介质层；
    将所述高带宽存储器芯片模块及逻辑芯片分别贴装至所述第一金属连接层及第二金属连接层；
    采用塑封材料包覆所述高带宽存储器芯片模块、逻辑芯片、第一金属连接层、第一介质层、第二金属连接层以及第二介质层，形成塑封层；
    在所述塑封层的第二表面形成承载载片；
    去除所述临时键合层及载片；
    在所述塑封层的第一表面形成表面钝化层，去除部分表面钝化层，以暴露第一金属连接层及第二金属连接层的至少一个外接焊盘；
    在所述表面钝化层上形成重布线层，使其与所述第一金属连接层及第二金属连接层电连接；
    在一个或多个所述重布线层的外接焊盘上制作凸点；以及
    减薄所述承载载片。
  10. 如权利要求9所述的制造方法，其特征在于，还包括步骤：对所 述多层高带宽存储器进行通电测试。
PCT/CN2023/080074 2022-09-06 2023-03-07 一种多层高带宽存储器及其制造方法 WO2024051124A1 (zh)

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