CN102812548B - 多芯片集成电路 - Google Patents

多芯片集成电路 Download PDF

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Publication number
CN102812548B
CN102812548B CN201080065118.2A CN201080065118A CN102812548B CN 102812548 B CN102812548 B CN 102812548B CN 201080065118 A CN201080065118 A CN 201080065118A CN 102812548 B CN102812548 B CN 102812548B
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integrated
interconnection structure
chip
compound
circuit die
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CN102812548A (zh
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阿利弗·瑞曼
帆特桑·穆拉立
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Xilinx Inc
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Xilinx Inc
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Abstract

一种复合集成电路(IC，100)在重建晶圆底座上结合具有第一晶上互连结构(114)的第一IC晶粒(芯片，102)与具有第二晶上互连结构(115)的第二IC晶粒(104)。第二IC晶粒是以氧化物对氧化物边缘接合(110)而被边缘接合到第一IC晶粒。芯片对芯片互连结构(118)电气耦合第一IC晶粒与第二IC晶粒。制造所述种复合集成电路的方法亦被描述于此。

Description

多芯片集成电路
技术领域
本发明概括关于集成电路，且更特别关于由多个晶粒(die)来制造大的集成电路。
背景技术
针对于已知的节点技术，增大集成电路(IC,integratedcircuit)尺寸典型提高可在芯片(chip)所纳入的功能性。不幸的是，缺陷经常随着芯片面积而按比例增减。大的芯片是相较于较小芯片者而更有可能纳入缺陷。缺陷影响良率，且良率损失经常随着增大芯片尺寸而提高。已经开发种种技术以提供大IC至期望良率程度。
提供大IC的一种方式是从在硅置入件上的多个较小IC(晶粒)来构成大IC。硅置入件是本质为基板，在硅置入件已经处理以提供金属接线与接点之后，晶粒是覆晶式接合到硅置入件。举例来说，如通称为“后端处理”，硅晶圆是经制造以形成一或多个硅置入件，其具有连接到通孔的数个图型化金属层与中间绝缘层。习知之导电通孔通过绝缘层而与图型化金属层连接在一起，且晶粒是以微凸块阵列而物性地且电性地连接到置入件。
这些图型化金属层提供对IC晶粒的高密度互连图型(pattern)。硅置入件是将细间距的晶粒连接到置入件相对面上的较粗的凸块阵列，且提供在晶粒之间的互连。导电贯穿硅通孔(TSV，through-siliconvia)延伸通过硅置入件以将晶粒电气连接到硅置入件相对面上的凸块阵列。此凸块阵列是被用以将大IC电气且机械连接到图型化电路板或封装基板。
不幸的是，要制造导电TSV是相当昂贵的且诸如电镀TSV之对于TSV的一些技术引入显著的处理延迟。举例来说，贯穿电镀TSV的使用可能对大IC的处理流程增加二到三个小时。
避免先前技术的缺点来提供大IC是期望的。
发明内容
一种复合或多芯片集成电路(IC)具有：第一IC晶粒(芯片)，其被安装在重建晶圆底座上且具有第一晶上(on-chip)互连结构；及第二IC晶粒，其被安装在重建晶圆底座上且具有第二晶上互连结构。第二IC晶粒是以氧化物对氧化物(oxide-to-oxide)边缘接合而被边缘接合到第一IC晶粒。被配置在第一IC晶粒上且在第二IC晶粒上的芯片对芯片(chip-to-chip)互连结构将第一晶上互连结构电气耦合到第二晶上互连结构。在又一个实施例中，所述IC具有在芯片对芯片互连结构上的接触阵列，诸如：球栅阵列或凸块阵列。在一个特定实施例中，重建晶圆底座包含造模化合物。在一个特定实施例中，氧化物对氧化物边缘接合包含二氧化硅。
在又一个实施例中，所述IC包括其安装在重建晶圆底座上且具有第三晶上互连结构的第三IC芯片，第三晶上互连结构是通过芯片对芯片互连结构而被耦合到第一晶上互连结构或第二晶上互连结构的至少一个。
在一个特定实施例中，芯片对芯片互连结构包括第一图型化金属层、在第一晶上互连结构与第二晶上互连结构与第一图型化金属层之间的第一介电层、第二图型化金属层以及在第一图型化金属层与第二图型化金属层之间的第二介电层。在再一个实施例中，第一导电通孔是从第一图型化金属层延伸通过第一介电层到第一晶上互连结构，且第二导电通孔是从第二图型化金属层延伸通过第二介电层到第一图型化金属层。
在另一个实施例中，一种复合IC是藉由生产IC晶粒所制造，各个IC晶粒具有晶上互连结构。IC晶粒的边缘是被抛光，且氧化物层是被沉积来涂覆IC晶粒的边缘以形成边缘氧化物层。在一些实施例中，即将成为复合IC周边边缘的晶粒之边缘系为未抛光。
边缘氧化物层是诸如藉由以氨溶液或氧电浆处理而被活化，且IC晶粒是以一或多个复合IC图型而配置在边缘接合载件上。IC晶粒为边缘接合在一起，例如：使用低温接合方法，其在特定方法中包括：将IC晶粒加热到不大于摄氏250度的温度。力量是被选用式施加在边缘接合过程期间以使IC晶粒保持为彼此接触。
重建晶圆底座是形成在IC晶粒上以形成重建晶圆。在一个特定实施例中，重建晶圆底座是由造模化合物所作成。在重建晶圆上的芯片对芯片互连结构电气耦合载晶互连结构。若重建晶圆具有超过一个复合IC，所述复合IC是从重建晶圆经单一化。
在一个特定实施例中，氧化物层包含沉积的二氧化硅且为以不大于摄氏450度的温度而沉积。在一个特定实施例中，制造芯片对芯片互连结构包括：在重建晶圆上形成至少二个图型化金属层具有中间介电层。在一个特定实施例中，中间介电层包含沉积的二氧化硅层，且二个图型化金属层中的第一个包含金属镶嵌(damascene)或双金属镶嵌图型化金属层。
在又一个实施例中，在制造芯片对芯片互连结构之后而在使复合IC单一化之前，第一接触阵列(例如：球栅阵列或焊锡凸块阵列)是形成在重建晶圆的第一复合IC上，且第二接触阵列是形成在重建晶圆的第二复合IC上。在一些实施例中，在重建晶圆上的复合IC是均为相同型式(图型)。或者是，IC晶粒是以不同图型所配置来产生不同型式的复合IC。举例来说，第一多个IC晶粒是以第一复合IC图型所配置，且第二多个IC晶粒是以不同于第一复合IC图型的第二复合IC图型所配置。
附图说明
图1是根据一个实施例之IC的横截面图。
图2是根据一个实施例在制造IC的步骤中之具有沉积氧化物层的晶粒的侧视图。
图3是在边缘接合载件上的晶粒的侧视图。
图4是图3的边缘接合晶粒为具有重建晶圆底座的侧视图。
图5是具有用于多个复合IC的芯片对芯片互连结构之重建晶圆的侧视图。
图6是根据一个实施例之复合IC的平面图。
图7是根据一个实施例之制造集成电路方法的流程图。
图8是根据一个实施例之使用于复合IC的IC芯片的平面图。
具体实施方式
图1是根据一个实施例之IC100的横截面图。所述种IC包括多个芯片(晶粒)102、104、106，其彼此为边缘接合且被安装在诸如硅晶圆或造模化合物的重建晶圆底座108之上。在一些实施例中，所述载件是多晶或单晶硅载件。或者是，载件是由造模化合物所形成。在一个特定实施例中，在造模材料中纳入硅粒子或其他粒子以改良热膨胀匹配或导热性。
晶粒102、104、106是诸如场可程序门阵列(FPGA,field-programmablegatearray)、处理器、特殊应用IC(ASIC,application-specifcIC)、或存储器芯片(例如：RAM)的IC。所述晶粒可为相同型式者(例如：均为FPGA芯片)或为不同型式者(例如：一些为FPGA且一些为RAM芯片)。所述晶粒是小于IC100的IC，且将被称作为晶粒，使得这些实际芯片在后续描述中为与较大的IC100作区别。晶粒102、104、106已经被测试且经挑选来确保有缺陷的晶粒不会被使用在IC100中，且为以氧化物对氧化物接合110而边缘接合在一起。氧化物对氧化物接合110的厚度是为了说明而经夸大。
为了便于讨论，晶粒102、104、106及IC100的顶面将指主要处理表面(即：图型化金属互连层与中间介电层为以通称为后端IC制造顺序者而被形成在其上的表面，亦被称为面)。所述晶粒及IC的底面将指晶粒电路为形成在其上的硅晶圆背面。举例来说，晶粒102的底面112是被附接到重建晶圆底座108。如在IC芯片制造技术中为通常已知，晶粒102的晶上互连结构114已使用一连串的图型化金属层、中间介电层以及导电通孔而被形成在晶粒102的顶面上。举例来说，FPGA晶粒可能具有十一个图型化金属层，其通常从硅芯片基板为按其顺序所描述(例如：M1、M2、...、M11)。晶上互连结构115、117亦已经被形成在其他晶粒104、106的顶面上。
芯片对芯片互连结构118是在晶粒102、104、106已经边缘接合且牢固到重建晶圆底座108之后而被形成在复合IC之上。芯片对芯片互连结构118包括第二组的图型化金属层119、121、中间介电层123、125以及通孔131。图型化金属层119、121是为了清楚说明而显示为整层。在一个特定实施例中，使用金属镶嵌或双金属镶嵌、或对于熟悉后端晶圆处理技术人士为已知的诸多其他技术来形成图型化金属层。在一个特定实施例中，芯片对芯片互连结构包括四个图型化金属层(例如：M12-M14)具有中间介电层。芯片对芯片互连结构118是与球块或凸块阵列122为接口连接，球块或凸块阵列122提供电气连接到IC100的晶粒102、104、106。举例来说，IC100可为覆晶式接合到印刷接线板或到封装基板或载件(未显示)。
在示范实施例中，二氧化硅是使用诸如化学气相沉积技术的低温(低于摄氏450度且或者是低于约摄氏400度)沉积技术而被沉积在晶粒的抛光边缘上。使用低温的沉积技术允许在没有损坏芯片内金属层的情况下而处理晶粒。已知数种二氧化硅处理，其形成保形的(conformal)二氧化硅层，基本为以二氧化硅层覆盖所述晶粒。适用于一个实施例的典型二氧化硅层厚度是大约数微米。在上方金属层中(例如：在M11到M14图型化金属层中)的接线宽度是典型为数个微米的间距。
图2是根据一个实施例在制造IC的步骤中之具有沉积氧化物层126的晶粒102、104、106的侧视图。氧化物层126是典型为在约1微米与约3微米厚之间的一层二氧化硅。所述晶粒是顶面朝下置放在沉积处理载件127之上且具有在晶粒间的充分间距以允许沉积氧化物涂覆所述晶粒的边缘128、130。
晶粒102、104、106是被制造在(未显示的)一或多个半导体基板(晶圆)上且藉由锯切或其他技术而被单一化。个别晶粒的边缘是在单一化后而选用式抛光来改良晶粒边缘的质量以供后续的氧化物沉积及边缘接合。单一化可能产生具有碎屑或突出的晶粒边缘，且抛光可改良表面平滑度与晶粒边缘的垂直性。在将氧化物层126沉积在晶粒102、104的背面132、134与边缘128、130之后，氧化物层是使用氨基溶液或诸如电浆活化或微洗涤技术的其他适合技术而选用式活化以利于低温的氧化物对氧化物接合。在又一个实施例中，沉积氧化物层是从晶粒背面所移除。举例来说，用于移除此背面氧化物的适合技术包括各向同性电浆蚀刻技术。移除背面氧化物降低芯片弯曲且可改良在复合IC中的晶粒的热耦合。
图3是在边缘接合载件136之上的晶粒102、104、106、142、144、146的侧视图。晶粒102、104、106、142、144、146是顶面朝下置放在接合处理表面138之上而彼此接触。随着所述晶粒是针对在晶粒的氧化物涂覆边缘之间的低温氧化物对氧化物接合而被加热，可选用式施加由箭头140所代表的力量以将所述晶粒保持在一起。在一个示范实施例中，附加晶粒是远离观者延伸以形成砖块状表面的晶粒阵列(参阅例如：图6)。还可选用式施加在平面正交方向(未显示)的力量以网格方式将所述晶粒保持在一起。在一个实施例中，在化学活化(即：氨溶液处理)的化学汽相沉积二氧化硅之间的氧化物对氧化物接合是以在约摄氏150度与约摄氏200度之间的温度而进行，此温度为充分低于约摄氏400度到约摄氏450度的期望最大温度极限。
图4是图3的边缘接合晶粒为具有重建晶圆底座400的侧视图。在一个特定实施例中，造模化合物或其他材料是形成在接合晶粒上以形成重建晶圆底座400。所述晶粒的顶面是在处理表面138上为共平面。造模化合物形成其将从载件136被移除且经单一化为多个复合IC的重建晶圆。在芯片边缘上的沉积氧化物层已经接合在一起，如由虚线402所代表。氧化物-氧化物边缘接合是在复合IC的晶粒间提供无间隙的边界，接着在用于芯片对芯片互连结构中的金属线的晶粒间提供平滑的过渡。
图5是具有用于多个复合IC的芯片对芯片互连结构501、503之重建晶圆500的侧视图。举例来说，芯片对芯片互连结构是附加的图型化金属层及中间介电层，其形成在重建晶圆上以将一个芯片102的晶上互连结构114上的接点电气耦合到另一个芯片104的晶上互连结构115。球块或凸块505(通称为“焊锡球块”或“焊锡凸块”)的接触阵列502、504是被形成在最后将成为复合IC者的芯片对芯片互连结构501、503之上。在一个特定实施例中，芯片对芯片互连结构501使在晶上互连结构114、115上的接点之相当细的间距转变为在接触阵列502中的球块或凸块之相当粗的间距。在重建晶圆形成凸块后，复合IC是从重建晶圆而经单一化。复合IC是根据期望应用而进一步处理或组装。
图6是根据一个实施例之复合IC600的平面图。复合IC600是为了说明而显示为不具有芯片对芯片互连结构或球栅阵列。晶粒102、104、106、602、604、606以氧化物对氧化物接合608而为边缘接合在一起。晶粒数目是仅为示范性质。替代的复合IC具有较多或较少个晶粒。在替代实施例中，并非所有在复合IC之上的晶粒均为相同尺寸。所述晶粒是均为相同型式的IC芯片(例如：六个FPGA)、或者是不同型式的IC芯片(例如：一或多个FPGA、数字信号处理器、或存储器芯片)。
图7是根据一个实施例之制造集成电路的方法700的流程图。一或多个晶圆是经制造、测试及挑选以产生已知良好的IC晶粒(步骤702)。在一些实施例中，IC晶粒均为相同型式的IC。举例来说，晶粒均为FPGA。在替代实施例中，不同型式的IC被纳入在晶粒中。举例来说，晶粒可能包括FPGA与存储器IC(例如：RAM)。在一些实施例中，一些晶粒是使用第一型式的制程(例如：硅CMOS制程)所作成，而其他晶粒是使用不同型式的制程(例如：SiGe晶圆制程、模拟或混合讯号IC制程、或存储器IC制程，诸如：闪存IC、OTP存储器IC、NV存储器IC、或ROM)所作成。根据实施例的复合IC可利用不同型式的IC晶粒，其中种种晶粒是针对种种参数为优化。举例来说，一个晶粒可能是针对SRAM功能性为优化，而另一个晶粒是针对逻辑功能性为优化。
晶粒边缘是经选用式抛光(步骤704)。在一个特定实施例中，使用习用的单一化后边缘抛光技术。晶粒边缘是以沉积氧化物层所涂覆(步骤706)。在一个特定实施例中，沉积氧化物层是使用不超过约摄氏450度的保形沉积技术所沉积。在一个特定实施例中，沉积氧化物层是在约1微米与约3微米厚之间的二氧化硅。或者使用较厚的氧化物层。各个IC不必具有相同的边缘氧化物厚度。晶粒是典型面对朝下置放在沉积载件上且沉积氧化物层是经选用式从晶粒背面所移除。涂覆边缘的沉积氧化物层(“边缘氧化物”)经活化以促进氧化物对氧化物边缘接合(步骤708)。在一个特定实施例中，使用氨溶液技术来使边缘氧化物活化。晶粒是根据复合IC设计在边缘接合载件上以选择图型或顺序而配置为面对朝下彼此接触(步骤710)。举例来说，复合IC可能经设计具有在二个FPGA晶粒之间的RAM晶粒。晶粒是配置在载件上，使得重建晶圆具有其形成复合IC的晶粒的期望图型。在一些实施例中，数种不同型式的复合IC是被配置在单一个重建晶圆上。在边缘接合载件上的晶粒是经加热以将晶粒边缘接合在一起(步骤712)。边缘接合使用氧化物对氧化物接合，其在一个特定实施例为发生在小于约摄氏250度的温度。在氧化物对氧化物接合过程期间可选用式施加力量以使晶粒保持为彼此接触。
造模化合物是被形成在边缘接合载件上的晶粒背面之上以形成重建晶圆底座(步骤714)。造模化合物是在半导体制造及封装技术为众所周知。重建晶圆是从边缘接合载件所移除(步骤716)且重建晶圆的正面是经处理以附加芯片对芯片互连结构(步骤718)，其在一个特定实施例为一连串的图型化金属层、中间绝缘层、以及在图型化金属层与晶上接点之间的导电通孔。在一个特定实施例中，芯片对芯片互连结构包括四个图型化金属层。在一个特定实施例中，芯片对芯片互连结构是被耦合到其具有约30微米到约50微米的接点间距之芯片。复合IC的顶层互连间距是典型为约150微米到约200微米；然而，这些尺度仅为示范性质。典型而言，并非所有在晶粒阶层的微凸块接点均为暴露到顶层。举例来说，芯片可能具有数千到数万个芯片对芯片连接，且包括约五千到约一万个顶层凸块(电气接点)。焊锡球块或凸块是经选用式形成在重建晶圆上(步骤720)，且从重建晶圆而使复合IC为单一化(步骤722)。
图8是根据一个实施例之用于复合IC的IC芯片800的平面图。此IC芯片是FPGA，其具有边缘氧化物层888，氧化物层888是用以形成与在边缘接合的复合IC中的一或多个其他IC芯片的氧化物对氧化物边缘接合。纳入FPGA的实施例包括其具有不同型式FPGA的复合IC，诸如：高性能FPGA是结合低成本FPGA，或者在复合IC内的不同FPGA是针对于不同功能性为优化。举例来说，在复合IC中的一个FPGA是针对于存储器性能为优化且另一个FPGA是针对于逻辑/DRAM设计规则为优化。其他实施例包括与其他型式的芯片作结合的FPGA，其他型式的芯片是诸如ROM芯片、SRAM芯片、或微处理器芯片。在特定实施例中，复合IC是本质为如同FPGA而操作。
FPGA架构包括大量不同的可程序砖块(tile)，其包括多千兆位收发器(MGT，multi-gigabittransceiver)801、可组态逻辑方块(CLB,configurablelogicblock)802、随机存取存储器方块(BRAM,randomaccessmemoryblock)803、输入/输出方块(IOB,input/outputblock)804、组态与时脉逻辑(CONFIG/CLOCK,configurationandclockinglogic)805、数字讯号处理方块(DSP，digitalsignalprocessingblock)806、特定输入/输出方块(I/O)807(例如：组态埠与时脉埠)、及其他可程序逻辑808，诸如：数字时脉管理器、模拟到数字转换器、系统监视逻辑、等等。一些FPGA还包括专属处理器方块(PROC)810。
在一些FPGA中，各个可程序砖块包括可程序互连组件(INT)811，其具有往返在各个相邻砖块中的对应互连组件的标准化连接。因此，一起被采取的可程序互连组件实施对于图标FPGA的可程序互连结构。可程序互连组件(INT)811还包括往返在相同砖块内的可程序逻辑组件的连接，如由图8的顶部所包括的实例所示。
举例来说，CLB802可包括可组态逻辑组件(CLE,configurablelogicelement)812，其可被程序规划为加上单一个可程序互连组件(INT)811来实施用户逻辑。除了一或多个可程序互连组件之外，BRAM803还可包括BRAM逻辑组件(BRL,BRAMlogicelement)813。典型而言，纳入在一个砖块中的互连组件数目是取决于砖块高度。在图绘的实施例中，BRAM砖块具有如同四个CLB的相同高度，但亦可使用其他数目(例如：五个)。除了适当数目个可程序互连组件之外，DSP砖块806还可包括DSP逻辑组件(DSPL,DSPlogicelement)814。举例来说，除了一个实例的可程序互连组件(INT)811之外，IOB804还可包括二个实例的输入/输出逻辑组件(IOL,input/outputlogicelement)815。输入/输出差动I/O缓冲器818亦为IOB814的部份。如将为熟悉此技术人士所明了，例如连接到差动I/O缓冲器818的实际I/O垫是使用在种种所示逻辑方块之上的金属层而制造，且典型为不局限在输入/输出差动I/O缓冲器818的区域。在图绘的实施例中，接近晶粒中央的柱状区域是用于组态、时脉、与其他控制逻辑。
利用图8所示架构的一些FPGA包括附加逻辑方块，其使构成FPGA的大部分之规则柱状结构瓦解。附加逻辑方块可为可程序方块及/或专属逻辑。举例来说，在图8所示的处理器方块(PROC)810跨越数列(column)的CLB与BRAM。
注意，图8是意图说明仅为一个示范的FPGA架构。在一列中的逻辑方块数目、列的相对宽度、列的数目与顺序、纳入在列中的逻辑方块型式、逻辑方块的相对大小、在图8顶部所包括的互连/逻辑实施是纯为示范性质。举例来说，在实际FPGA中，超过一个相邻列的CLB是无论CLB出现在何处而典型被纳入以利于用户逻辑的有效率实施。
尽管本发明已经关连于特定实施例所描述，这些实施例的变化将对于熟悉此技术人士为显明。举例来说，诸如硅晶圆结合造模化合物，替代的衬底材料或衬底材料组合是经使用以从晶粒来形成重建晶圆。因此，随附申请专利范围的精神与范畴不应受限于前文描述。

Claims (15)

1.一种复合集成电路，其包含：
第一集成电路晶粒，其具有相对的第一表面和第二表面、围绕所述第一表面和所述第二表面的边缘以及第一晶上互连结构，所述第一集成电路晶粒是被安装在重建晶圆底座上，且所述第一集成电路晶粒的所述第一表面面对所述重建晶圆底座；
第二集成电路晶粒，其具有相对的第一表面和第二表面、围绕所述第一表面和所述第二表面的边缘以及第二晶上互连结构，所述第二集成电路晶粒是被安装在所述重建晶圆底座上，且所述第二集成电路晶粒的所述第一表面面对所述重建晶圆底座；
其中在所述第一集成电路晶粒的所述边缘的至少一者上设置第一氧化物层，所述第一氧化物层从所述第一集成电路晶粒的所述第一表面延伸至所述第二表面，在所述第二集成电路晶粒的所述边缘的至少一者上设置第二氧化物层，所述第二氧化物层从所述第二集成电路晶粒的所述第一表面延伸至所述第二表面，并且所述第一氧化物层和所述第二氧化物层彼此接触且接合在一起；及
芯片对芯片互连结构，其配置在所述第一集成电路晶粒上及所述第二集成电路晶粒上；
其中所述芯片对芯片互连结构将所述第一晶上互连结构电气耦合到所述第二晶上互连结构。
2.如权利要求1所述的复合集成电路，其还包含：在所述芯片对芯片互连结构上的接触阵列。
3.如权利要求2所述的复合集成电路，其中所述接触阵列是球栅阵列或凸块阵列。
4.如权利要求1所述的复合集成电路，其中所述重建晶圆底座包含造模化合物。
5.如权利要求1所述的复合集成电路，其中所述氧化物对氧化物边缘接合包含二氧化硅。
6.如权利要求1所述的复合集成电路，其还包含：安装在所述重建晶圆底座上且具有第三晶上互连结构的第三集成电路晶粒；
其中第三晶上互连结构是通过所述芯片对芯片互连结构而被耦合到第一晶上互连结构或第二晶上互连结构的至少一个。
7.如权利要求1所述的复合集成电路，其中所述芯片对芯片互连结构包含：
第一图型化金属层；
第一介电层，其在第一晶上互连结构与第二晶上互连结构与第一图型化金属层之间；
第二图型化金属层；及
第二介电层，其在第一图型化金属层与第二图型化金属层之间。
8.如权利要求7所述的复合集成电路，其还包含：
第一导电通孔，其从第一图型化金属层延伸通过第一介电层到第一晶上互连结构；及
第二导电通孔，其从第二图型化金属层延伸通过第二介电层到第一图型化金属层。
9.一种制造复合集成电路的方法，所述方法包含：
生产集成电路晶粒，各个集成电路晶粒具有晶上互连结构；
将所述集成电路晶粒边缘抛光；
沉积氧化物层来涂覆所述集成电路晶粒边缘以形成边缘氧化物层；
使所述边缘氧化物层活化；
在边缘接合载件上的一或多个复合集成电路图型中配置所述集成电路晶粒为彼此接触；
将所述集成电路晶粒边缘接合在一起以在所述复合的集成电路中的所述晶粒间提供无间隙的边界；
在所述集成电路晶粒上形成重建晶圆底座以形成重建晶圆；
在所述重建晶圆上制造芯片对芯片互连结构以电气耦合所述晶上互连结构；且
从所述晶圆而使一或多个复合集成电路为单一化。
10.如权利要求9所述的方法，其中将所述集成电路晶粒边缘接合包括：施加力量以使所述集成电路晶粒保持为彼此接触以及将所述集成电路晶粒加热到不大于摄氏250度的温度。
11.如权利要求9所述的方法，其中所述形成重建晶圆底座包括：将造模化合物施加到在所述边缘接合载件上的边缘接合晶粒的背面。
12.如权利要求9所述的方法，其中所述制造芯片对芯片互连结构包括：在所述重建晶圆上形成具有中间介电层的至少二个图型化金属层。
13.如权利要求12所述的方法，其中：
所述中间介电层包含沉积的二氧化硅层；且
所述至少二个图型化金属层中的第一个包含金属镶嵌或双金属镶嵌图型化金属层。
14.如权利要求9所述的方法，其在所述制造芯片对芯片互连结构之后且在所述单一化之前，还包含：
在所述重建晶圆的第一复合集成电路上形成第一接触阵列；且
在所述重建晶圆的第二复合集成电路上形成第二接触阵列。
15.如权利要求9所述的方法，其中所述集成电路晶粒的配置包含配置第一多个集成电路晶粒于第一复合集成电路图型中以及配置第二多个集成电路晶粒于与所述第一复合集成电路图型不同的第二复合集成电路图型中。
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