TWI461125B - 組裝構造及組裝方法 - Google Patents

組裝構造及組裝方法 Download PDF

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Publication number
TWI461125B
TWI461125B TW100142265A TW100142265A TWI461125B TW I461125 B TWI461125 B TW I461125B TW 100142265 A TW100142265 A TW 100142265A TW 100142265 A TW100142265 A TW 100142265A TW I461125 B TWI461125 B TW I461125B
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Taiwan
Prior art keywords
electrode
metal
wiring substrate
electronic component
assembly structure
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Application number
TW100142265A
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English (en)
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TW201236520A (en
Inventor
Masahiro Kubo
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Nec Corp
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Publication of TW201236520A publication Critical patent/TW201236520A/zh
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Publication of TWI461125B publication Critical patent/TWI461125B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/4201Packages, e.g. shape, construction, internal or external details
    • G02B6/4219Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236Fixing or mounting methods of the aligned elements
    • G02B6/4239Adhesive bonding; Encapsulation with polymer material
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/4201Packages, e.g. shape, construction, internal or external details
    • G02B6/4274Electrical aspects
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    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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Description

組裝構造及組裝方法
本發明係關於電子零件之組裝構造及組裝方法。
近年來,電子設備之輕量化、薄型化、小型化急速獲得進展,業界對所組裝之電子零件亦要求輕量化、薄型化、小型化。
另一方面,現在許多電子設備中,作為連接電子零件與配線基板之材料,使用固體焊錫。將電子零件組裝於配線基板時,於形成鎳或金的薄膜之電極焊墊將焊料糊劑印刷之。又,以焊錫之熔融溫度以上之溫度,使焊錫加熱熔融,連接電極焊墊與焊錫。將電子零件搭載於配線基板時,在常溫下,對準電子零件之電極焊墊與配線基板之電極焊墊。其後,昇溫至電子零件與配線基板上的預備焊錫熔融之溫度。又,於電子零件以及配線基板焊錫濕潤擴散後,使溫度降低。如此,藉由使電子零件以及配線基板之溫度降低,焊錫凝固,在電子零件與配線基板之間形成固體連接部。
又,作為電子零件之封裝體構造,有稱為QFP(Quad Flat Package)之構造。QFP將電子零件之連接端子配置於封裝體外周,連接該連接端子與配線基板,藉此在電子零件與配線基板之間發送接收電信號。
然而,QFP中,僅可於封裝體外周部配置輸入輸出端子。因此,於封裝體中央附近,會產生連接端子不存在之無效區域。因此,有不適應近年來伴隨資訊量擴大輸入輸出端子數之增加,對高密度化而言不合適之缺點。
為解決如此之課題,可利用於電子零件外周部與中央部雙方設置外部連接端子,稱為BGA(Ball Grid Array;球柵陣列)之構造。BGA構造於半導體元件全面形成外部連接端子,可高密度組裝。然而,於如此之高密度組裝構造,亦有如以下之問題。
一般而言,電子零件之線膨脹係數與配線基板之線膨脹係數不同。因此,因電子零件動作時之發熱與冷卻,會發生電子零件與配線基板線膨脹係數不一致。又,因此線膨脹係數之不一致,於連接電子零件與配線基板之固化之焊錫會產生應力,發生可見於固體金屬材料之蠕變現象。因此蠕變現象所產生之應變於配線基板與電子零件之連接部分累積,故會在配線基板與電子零件之連接部分產生裂縫。又,有因此裂縫之成長,導致電子零件與配線基板之連接部分斷線之問題。
另一方面,近年來伴隨著汽車之電子化,於汽車引擎室等內,在130℃以上之高溫環境下使用電子設備之情況增加。在如此之環境下,蠕變現象特別易於發生。因此,需在如此之高溫環境下亦可維持高精度連接可靠度之電子設備。
與可維持高精度連接可靠度之電子設備關連之技術記載於例如日本特開平11-1630449號公報(以下稱專利文獻1),日本特開2003-020404號公報(以下稱專利文獻2)及日本特開平4-240741號公報(以下稱專利文獻3)。
專利文獻1中記載有下列方法:在電子零件與配線基板之間之焊錫連接部分,使稱為底部填充樹脂之液狀樹脂填充、硬化,藉此補強焊錫連接部分。此方法使電子零件與配線基板之間所產生之應力不僅在焊錫連接部更在底部填充樹脂全面分散。
專利文獻2中記載有下列技術:於電子零件與配線基板之間之連接部分形成柔軟的應力紓解層,使蠕變應變減少。
專利文獻3中記載有下列構造:於連接部分塗布低融點金屬。更具體而言,記載有下列構造:作為半導體側之凸塊使用金屬凸塊,於其前端塗布低融點金屬,連接半導體元件與配線基板。藉此,可紓解低融點金屬熔融之溫度條件範圍內之應力,可期待可靠度之提升。
【先前技術文獻】 【專利文獻】
【專利文獻1】日本特開平11-163049號公報
【專利文獻2】日本特開2003-020404號公報
【專利文獻3】日本特開平4-240741號公報
然而,專利文獻1所記載之方法雖可延長至斷線為止之壽命,但無法防止蠕變現象發生。因此,無法完全防止裂縫發生及進展。因此,假定在汽車引擎室之易於呈高溫之場所使用之電子設備之用途中,有連接可靠度不充分之課題。
且專利文獻2所記載之方法中,雖可延長至斷線為止之壽命,但亦無法完全防止包含絕緣層裂縫之發生及進展。
且專利文獻3所記載之連接部及半導體元件整體係由樹脂所密封。使用低融點金屬連接半導體元件與配線基盤時,就防止低融點金屬於熔融時流出,以及耐撞性、對環境之耐受性之觀點而言,需以樹脂密封。另一方面,近年來,業界要求半導體封裝體之薄型化 、高密度化,半導體元件與配線基板之間之間隙非常狹窄。且封裝樹脂中為紓解半導體元件與配線基板間之熱膨脹差,無機填料呈高填充。因此,封裝樹脂之流動性被阻礙,令封裝樹脂填充所有狹窄之間隙間有其困難,難以提供高可靠度之連接部。
鑑於如此之問題,本發明之目的在於提供一種組裝構造及組裝方法,即使在使用環境溫度呈高溫之情形下,亦可維持高精度之連接可靠度。
本發明之組裝構造包含電子零件、金屬、配線基盤與抑制構造。電子零件具有第一電極。金屬其融點在130℃以下。配線基板具有經由金屬電性連接第一電極之第二電極。抑制構造抑制熔融狀態金屬朝形成第一電極及第二電極之區域外部流出。且抑制構造形成於電子零件及配線基板其中至少一方。
本發明之組裝方法係依將具有第一電極之電子零件組裝於具有第二電極之配線基板之組裝方法。此態樣中,包含下列程序:對第一電極上及第二電極上其中至少任一方供給融點在130℃以下之金屬;及於配線基板組裝電子零件。
第一電極與第二電極經由金屬電性連接。於電子零件及配線基板其中至少一方,形成有用來抑制金屬朝形成第一電極及第二電極之區域外部流出之抑制構造。
依本發明中之組裝構造及組裝方法,即使在使用環境溫度呈高溫之情形下,亦可維持高精度之連接可靠度。
參照圖式並同時說明關於本發明之實施形態例。然而,相關形態不限定本發明之技術性範圍。
(第1實施形態例)
使用圖1說明關於本發明第1實施形態例中之組裝構造。
本實施形態例中之組裝構造10包含電子零件11、金屬12與配線基板13。電子零件11具有第一電極14。金屬12其融點在130℃以下。因此,本實施形態例中之金屬12在組裝構造10之使用環境溫度在130℃以上時呈熔融狀態。
且第一電極14經由金屬12電性連接第二電極15。
且電子零件11及配線基板13其中至少一方具有抑制金屬12朝形成有第一電極14及第二電極15之區域外部流出之抑制構造。又,本實施形態例中之抑制構造係形成於配線構造13之段差16。
其次,描述關於組裝構造10之製造方法。
一開始,在配線基板13之第二電極15上供給金屬12。此時,因應所需進行重熔程序。
其次,於配線基板13組裝電子零件11。此時,藉由第一電極14與第二電極15分別接觸金屬12,第一電極14電性連接第二電極15。且藉由段差16抑制熔融狀態之金屬12流出,故可維持第一電極14與第二電極15之電性連接狀態。如以上製造本實施形態例中之組裝構造10。
如以上,於本實施形態例中之組裝構造10,經由金屬12連接電子零件11與配線基板13。
一般而言,使用環境溫度若呈高溫即易於發生發生在固體金屬之蠕變現象,若超過130℃即會特別易於發生發生在固體金屬之蠕變現象。然而,本實施形態例中之金屬12融點在130℃以下,故組裝構造10之使用環境溫度在130℃以上時呈熔融狀態。因此,第一電極14與第二電極15在使用環境溫度呈高溫時,經由處於熔融狀態之金屬電性連接,故於連接部分不發生蠕變現象。因此,可抑制於連接部分發生應變或裂縫。藉此,本實施形態例中之組裝構造即使在使用環境溫度呈高溫時,亦可維持高精度之連接可靠度。
且藉由段差16抑制熔融狀態之金屬12朝形成有第一電極14及第二電極15之區域外部流出。
因此,經由處於熔融狀態之金屬維持第一電極14與第二電極15之間電性連接之狀態。且亦可防止因金屬12接觸除第一電極14及第二電極15外其他金屬而發生短路。
且本實施形態例中,雖使用段差16作為抑制金屬12流出之抑制構造,但抑制構造不限於此。亦即,亦可如以下第2實施形態例中所述,作為抑制構造,不使用段差16而代之以於電子零件11及配線基板13其中至少任一表面形成規則配置之微細柱狀構造(pillar),或是除段差16外更於電子零件11及配線基板13其中至少任一表面形成規則配置之微細柱狀構造(pillar)。
又,本實施形態例中,雖使用融點在130℃以下之金屬12,但使用融點在40℃以下之金屬更佳。此因如後述第2實施形態例中所述,具有例如可省略重熔程序等優點。
(第2實施形態例)
使用圖2說明關於本發明第2實施形態例中之組裝構造。
本實施形態例中之組裝構造20包含電子零件21、金屬22與配線基板23。
電子零件21具有第一電極24。又,作為電子零件21,可使用例如0.3mm間距,228腳的CSP(Chip Size Package)等。
金屬22其融點在40℃以下。製造組裝構造20時之溫度除加熱處理時外,一般在約40℃之環境下進行。且使用組裝構造20時之溫度多半在40℃以上。因此,本實施形態例中之金屬22一般在製造及使用組裝構造20時處於熔融狀態。
配線基板23包含第二電極25、凹部26、段差27與奈米柱構造28。又,奈米柱構造28由規則配置之微細柱狀構造所構成,形成於第二電極25周圍。
凹部26注入金屬22,於底面具有第二電極25。
且段差27與奈米柱構造28分別係用來將處於熔融狀態之金屬22朝形成有第一電極24及第二電極25之區域外部流出加以抑制之抑制構造。
亦即,段差27扮演防止處於熔融狀態之金屬22因落下撞擊等外力流出,接觸其他金屬而導致引起短路之角色。且段差27亦具有調整電子零件21與配線基板23間間隙之作用。因此,段差27之高度小於第一電極24相對於電子零件21表面垂直方向之長度。
且形成於配線基板23表面之奈米柱構造28表現出有斥水、斥油性。藉由奈米柱構造28,熔融之金屬難以朝奈米柱構造28外側濕潤擴散。因此與段差27相同,可藉由奈米柱構造28防止短路發生。
且第一電極24接觸注入凹部26之金屬22。藉此,第一電極24與第二電極25經由處於熔融狀態之金屬22電性連接。
其次,說明關於本實施形態例中組裝構造20之製造方法。
一開始,描述關於在配線基板23形成奈米柱構造28之方法。作為形成奈米柱構造28之手法,可舉出使用奈米壓印法等手段成型之方法。具體而言,係操作員或製造裝置準備Ni之金屬或Si、石英玻璃等成形模具,將其加熱並同時推壓被成形材料之方法。作為被成型材料,可使用樹脂。
又,奈米柱構造28之寬高比宜在1以上。此因為使奈米柱構造28表現出有如上述之斥水、斥油性,需至少1以上之寬高比。
且奈米柱構造28之寬高比宜在5以下。其理由有2個。
第1個理由來自奈米柱構造28強度之觀點。亦即,奈米柱構造28之寬高比會對成型之樹脂之物理性強度造成影響。又,若使用寬高比高於5之成形模具使樹脂推壓成型,自成形模具卸除樹脂時,樹脂本身之強度即無法勝過在成形模具與樹脂之間產生之剪切力,樹脂會被切碎。
第2個理由來自壓紋時產出之觀點。亦即,形成奈米柱構造時使用之成形模具製造程序中,包含以藉由蝕刻Si獲得之母版作為模型對Ni等施行電鑄電鍍後,將Ni電鍍自Si模型剝離之程序。因此, 產生Si蝕刻之產出,及自Si模型剝離Ni電鍍時之產出。又,寬高比高於5時,上述之產出顯著惡化。
依如以上之理由,奈米柱構造28之寬高比宜在5以下。
且奈米柱構造28柱狀構造中心間之間距宜在500nm以下,在100nm以下更佳。此因柱狀構造間之間距狹窄時斥水、斥油性優異,故更可抑制處於熔融狀態之金屬流出。例如,藉由使寬高比為1之奈米柱構造柱狀構造間之間距自270nm微細化至100nm,可使奈米柱構造相對於純水之接觸角自100°未滿提高至150°。
其次,描述關於在配線基板23形成段差27之方法。
作為形成段差27之方法,有使位於配線基板23表面之阻銲劑材料成型加工之方法。或是,有使用熱熔黏接劑、膜壓經控制之膠帶形狀黏接劑之方法,或組合此等者而加以使用之方法。又,作為段差27之材料,可舉出熱硬化樹脂或熱可塑性樹脂等。
形成奈米柱構造28及段差27後,將熔融狀態之金屬22注入配線基板23之凹部26。金屬22中,可使用例如GaIn合金(Ga75.5In24.5)等。
此GaIn合金相較於水銀之其他代表性之處於熔融狀態之金屬表面張力低。因此,於金屬22使用GaIn合金時,可例如保持接觸第一電極24上的金屬22之寬高比在3以上。且因表面張力低,會產生即使在於製造過程產生之配線基板23發生翹曲或起伏時,電極間亦易於連接之效果。
且GaIn合金相較於水銀亦有毒性低之特徵。且Ga75.5In24.5合金之融點為15.7℃,低於一般製造線之環境溫度(約30~40℃)。因 此,GaIn合金於一般製造線,可藉由用於供給封裝樹脂,附有加溫功能之注射器等穩定供給。
又,金屬22不限定於Ga75.5In24.5,亦可使用Ga68.5In21.5 Sn10(融點-19℃)、Ga61In25 Sn13Zn1(融點7.6℃)、Ga(融點29.8℃)、其他Al與Ga之合金、Ag與Ga之合金等融點在40℃以下之各種金屬。
其次,操作員或製造裝置對準電子零件21與供給有金屬22之配線基板23。其後,操作員或製造裝置使用倒裝晶片接合器在配線基板23上搭載電子零件21。此時,藉由第一電極24與第二電極25分別接觸金屬22,第一電極24與第二電極25電性連接。且藉由段差27及奈米柱構造28抑制金屬22流出。
如以上,製造本實施形態例中之組裝構造20。
本實施形態例中,為連接第一電極24與第二電極25,使用融點在40℃以下之金屬22。因此,第一電極24與第二電極25即使在使用組裝構造20時,亦藉由處於熔融狀態之金屬電性連接。因此,不發生於連接部分使用固體金屬時發生之蠕變現象,可抑制因連接部分斷線導致不良發生。因此,即使在使用環境溫度呈高溫時,亦可維持高精度之連接可靠度。
且使用熔融狀態之金屬22,故於製造過程無需重熔金屬22。因此,可防止以固體金屬連接2個電極時成為問題,因重熔時產生之熱而發生之電子零件21與配線基板23之偏位,或配線基板23之翹曲。
且本實施形態例中,藉由段差27及奈米柱構造28抑制熔融狀態之金屬22流出。因此,可維持第一電極24與第二電極25之電性 連接狀態。且有抑制處於熔融狀態之金屬接觸其他電極而導致短路發生之效果。
且於金屬22使用GaIn合金時,於第一電極24表面亦可形成約數μm之薄膜鋁層。
GaIn合金具有熔融鋁之性質。因此,若在第一電極24上供給作為金屬22之GaIn合金,GaIn合金即會溶解於第一電極24表面形成之鋁層,與第一電極24未氧化之表面易於形成接點。亦即,藉由在第一電極24表面形成鋁層,可抑制第一電極24氧化,並可提升GaIn合金之濕潤,降低連接電阻。
同樣地,於第二電極25表面亦可形成約數μm之薄膜鋁層。
且為提高組裝構造20之耐落下撞擊性及耐振動性,於電子零件21外周部,亦可供給固定配線基板23用之樹脂。作為固定用樹脂,宜使用具有對應組裝構造20使用溫度環境之耐熱性,於室溫可硬化之封裝樹脂。此因若使用如此之樹脂,即不會因樹脂之加熱程序使翹曲發生於配線基板23。作為如此之樹脂,可舉出例如環氧樹脂、矽氧樹脂、胺酯樹脂、丙烯樹脂等。
且於此固定用樹脂使用熱可塑性樹脂時,當在組裝後發現失效之際,可交換不良零件。因此,使用如需交換不良零件之高附加價值之電子零件,或高多層配線基板時,宜使用發生失效時可去除之熱可塑性樹脂。且使用熱可塑性樹脂時,亦可吸收使用組裝構造20時所受之熱衝擊之影響。作為如此之樹脂,可舉出例如胺酯樹脂、丙烯樹脂以及使熱可塑性樹脂粒子分散於熱硬化性樹脂之樹脂等。
且本實施形態例中,雖於配線基板23形成凹部26,但不限於 此。亦即,亦可在電子零件21形成於底面具有第一電極24之凹部。又,在製造組裝構造時,亦可將金屬22注入該凹部。
又,本實施形態例中,段差27雖形成於配線基板23,但不限於此。亦即,亦可於電子零件21形成段差。
且本實施形態例中,雖於配線基板23形成奈米柱構造28,但不限於此。亦即,奈米柱構造28亦可形成於電子零件21第一電極24周圍。此時,奈米柱構造28亦表現出有斥水、斥油性,故可防止熔融之金屬朝奈米柱構造28外側濕潤擴散。
或是,亦可於電子零件21第一電極24周圍及配線基板23第二電極25周圍中任一者皆形成奈米柱構造28。此時,在形成於電子零件21表面之奈米柱構造28與形成於配線基板23表面之奈米柱構造28之間形成空隙,作為整體表現出有斥水、斥油性。
且本實施形態例中,雖使用融點在40℃以下之金屬22,但不限於此。亦即,只要是融點在130℃以下之金屬,即可防止使用環境溫度呈在130℃以上之高溫時發生之蠕變現象。又,所謂融點在130℃以下之金屬係例如In66Bi34(融點約72℃)、Sn16In30Bi54(融點約81℃)、Sn16Bi52Pb32(融點約95℃)、Sn48In52(融點約117℃)。
(第3實施形態例)
說明關於本發明第3實施形態例中之組裝構造。本實施形態例之組裝構造30中,於第2實施形態例中之組裝構造20段差27之材料包含熱可塑性樹脂。且奈米柱構造28不僅形成於第二電極25周圍,亦形成於第一電極24周圍。關於其他構成與第2實施形態例相同,故說明省略。
一般而言,於配線基板組裝電子零件後,為偵測電子零件與 配線基板連接狀態之失效,會進行導通測試等動作試驗。然而,組裝用於超級電腦或高級伺服器等之大型多腳電子零件時,為進行動作試驗,需以環氧樹脂等熱硬化樹脂密封固定電子零件與配線基板之間。此因不密封固定電子零件與配線基板之間時,對電子零件與配線基板之焊錫連接部之物理性負載會非常大,難以進行動作試驗。
然而,以熱硬化樹脂密封固定電子零件與配線基板之間時,熱硬化樹脂會強固地密接電子零件及配線基板。因此,即使已藉由動作試驗確認失效,亦無法去除熱硬化樹脂,無法再利用配線基板。特別是近年來的高多層配線基板多半以生產力優異之有機材料製造。有機配線基板相較於陶瓷基板耐熱性低,對熱硬化性樹脂去除作業之承受性低。
另一方面,本實施形態例中之組裝構造30內,第一電極24與第二電極25藉由處於熔融狀態之金屬22電性連接。因此,不需如上述以熱硬化樹脂密封固定電子零件與配線基板之間。
又,藉由使段差27之材料中包含熱可塑性樹脂,於配線基板組裝電子零件後以動作試驗確認失效時,可卸除或交換電子零件。
一般而言,於超級電腦等所利用之電子零件或高多層配線基板非常昂貴。因此,如本實施形態例,當動作試驗時偵測到失效之際可卸除或交換電子零件,藉此可間接大幅削減成本。
且熱可塑性樹脂一般係低彈性樹脂。因此,即使假設於配線基板或電子零件發生翹曲,亦可藉由低彈性樹脂部分紓解該翹曲,抑制處於熔融狀態之金屬流出。
作為係段差27之材料之熱可塑性樹脂之具體例,可舉出丙烯 樹脂、胺酯樹脂、矽氧樹脂等。且亦可令熱可塑性樹脂粒子分散至熱硬化性樹脂,於段差27使用可在玻璃轉移溫度以上之溫度去除樹脂之材料。
又,於配線基板23表面形成之阻銲劑之玻璃轉移溫度多半約為100~120℃。因此,作為用於段差27之熱可塑性樹脂,玻璃轉移溫度宜低於該阻銲劑之玻璃轉移溫度。
且自配線基板23卸除電子零件21時,亦可使用降低包含熱可塑性樹脂之段差27與配線基板23之密接力,使兩者之接合易於解除之有機溶劑。
且於圖2,第一電極24及第二電極25之表面形狀雖係柱形,但於本實施形態例不限於柱形。亦即,第一電極24及第二電極25之表面形狀亦可係圓錐形或中空形狀等。
使用圖3說明關於本發明第4實施形態例中之組裝構造。
本實施形態例中之組裝構造40相較於第2實施形態例中之組裝構造20第一電極24之形狀不同。且奈米柱構造28不僅形成於第二電極25周圍,亦形成於第一電極24周圍。關於其他構成,與第2實施形態例相同,故省略說明。
本實施形態例中之組裝構造40第一電極41形成於電子零件21中與配線基板23對向之面42。又,第一電極41中,相對於面42垂直方向之長度大於相對於面42平行方向之長度。
亦即,加工第一電極41為係以相對於面42平行方向之長度除相對於面42垂直方向之長度之值之寬高比高之形狀。
又,本實施形態例中之第一電極41與第二電極25經由處於熔融狀態之金屬22電性連接。且本實施形態例中,如圖4所示,呈如處於熔融狀態之金屬22將第一電極41包在裡面之狀態。
一般而言,電極若因熔融狀態之金屬濕潤,即使假設於電極發生變形,熔融狀態之金屬亦會如麥芽糖拔絲般變形。因此,可維持電子零件與配線基板之連接狀態。
然而,於製造過程發生之配線基板翹曲或平坦性差異若大,有時電子零件之電極即會無法接觸熔融之金屬。此時,會發生電子零件21與配線基板23之連接不良。
另一方面,本實施形態例中,形成第一電極41,俾相對於面42垂直方向之長度大於相對於面42平行方向之長度。因此,因第一電極41易於接觸熔融之金屬22,即使發生配線基板23翹曲或平坦性差異,亦難以發生電子零件21與配線基板23之接觸不良。
又,作為使第一電極41為寬高比高之形狀之手法,可使用以奈米壓印法等進行之機械式成型加工,或以蝕刻、雷射加工進行之方法。
且第一電極41之寬高比宜在5以下。例如作為第一電極41,使用0.8mm間距之CSP時,第一電極41之寬(相對於面42平行方向之長度)約400~500um。因此,第一電極41之高度(相對於面42垂直方向之長度)宜在約2.5mm以下。
寬高比宜在5以下係因若寬高比大於5,如於第2實施形態例所述,就第一電極41之強度及壓紋時產出之觀點而言會發生問題。
如以上,本實施形態例中,第一電極41為寬高比高之形狀。 因此,即使在因配線基板23翹曲或平坦性差異等,電子零件21與配線基板23之距離非一定時,亦可抑制兩者連接不良發生。
又,第一電極41亦可由電極焊墊43與預備焊錫44形成。作為製造方法,有例如於電極焊墊43表面藉由網版印刷法形成預備焊錫之方法。此時,如圖5(a)所示,電極焊墊43亦可自面42突出。或是,亦可如圖5(b),電極焊墊43不自面42突出。又,作為電極焊墊43表面之素材,例如可使用Ni、金、鋁等。且作為預備焊錫44,例如可使用Pb95Sn5、Sn-Ag-Cu合金焊錫。
(第5實施形態例)
使用圖6說明關於本發明第5實施形態例中之組裝構造。
本實施形態例中之組裝構造50分別於電子零件21具有之第一電極51,與配線基板23具有之第二電極52表面形成凹凸形狀。因此,相較於第2實施形態例,接觸金屬22之第一電極51表面積,及接觸金屬22之第二電極52表面積大。且奈米柱構造28不僅形成於第二電極52周圍,亦形成於第一電極51周圍。關於其他構成與第2實施形態例相同,故省略說明。
作為於第一電極51及第二電極52表面形成凹凸形狀之手法,可舉出以奈米壓印法等進行之機械式成型加工或蝕刻、雷射加工等方法。
於第一電極51及第二電極52表面形成微細柱狀構造時,柱狀構造中心間之間距宜在500nm以上。此因柱狀構造之間距愈狹窄,斥水性愈獲得提升,金屬22之濕潤性降低。已知例如若在呈間距相對較狹窄(約150nm)的柱狀構造之樹脂上滴入水,即會呈像是水銀在玻璃上滾動的狀態。且尚有一原因:施行寬高比大的加工時,柱狀構造中心間之間距若未滿500nm,即會發生產出惡化等問題。
又,於第一電極51及第二電極52表面形成之凹凸形狀之寬高比宜在0.01以下。此因寬高比愈高電極表面之斥水性即愈高,於電極表面金屬22難以濕潤擴散。
如以上,於本實施形態例,接觸金屬22之第一電極51表面積,及接觸金屬22之第二電極52表面積大。因此,於使用組裝構造50時,可降低處於熔融狀態之金屬22,與第一電極51及第二電極52之連接抵抗。
又,使接觸金屬22之第一電極51表面積,及接觸金屬22之第二電極52表面積變大的第一電極51或第二電極52之形狀不限於形成於第一電極51與第二電極52表面之凹凸形狀。
亦可例如圖7(a)所示,於第一電極51加工形成中空形狀之孔。或是亦可如圖7(b)所示,使第一電極51由平面狀電極焊墊與中空形狀之預備焊錫構成。又,圖7中自斜下方觀察形成於電子零件21之第一電極51。
同樣地,於第二電極52亦可施行中空形狀之孔的加工。
(第6實施形態例)
使用圖8說明關於本發明第6實施形態例中之組裝構造。
本實施形態例中之組裝構造60內,使第4實施形態例之組裝構造40構造之凹部26呈如圖8所示之凹部61之形狀。關於其他構造,與組裝構造40相同,故省略說明。
如圖8所示,本實施形態例中之凹部61係呈:在配線基板23表面之面內方向的面積自配線基板23表面朝深度方向變大之形狀。 本實施形態例中,凹部61側面沿垂直於配線基板23表面之方向傾斜。
藉由使凹部61呈如此之形狀,即使當在振動劇烈之環境下使用組裝構造60時,亦可抑制處於熔融狀態之金屬22自凹部61流出。其結果,可防止因金屬22接觸其他區域之金屬而發生短路。所謂其他區域之金屬係例如第一電極41及第二電極25以外之電極,或接觸該電極之金屬。
又,本實施形態例中,凹部61雖呈凹部61側面傾斜之構造,但不限於如此之構造。例如凹部61側面亦可具有段差,凹部61呈配線基板23表面沿面內方向之面積自配線基板23表面朝深度方向階段性地變大的形狀。即使在呈如此之形狀時,亦可呈處於熔融狀態之金屬22難以自凹部61流出之構造,故即使在振動劇烈之環境下使用時,亦可防止短路發生。
(第7實施形態例)
使用圖9說明關於本發明第7實施形態例中之組裝構造。
本實施形態例中之組裝構造70包含晶片71、金屬72、配線基板73與波導管構造74。
晶片71包含發光區域75與第一電極76。金屬72其融點在40℃以下。因此,金屬72於製造及使用組裝構造70時處於熔融狀態。配線基板73包含凹部77與形成於凹部77底面之第二電極78。金屬72注入凹部77。波導管構造74具有光波導管79,在配線基板73上形成。且第一電極76與第二電極78經由金屬72電性連接。
又,固定晶片71,俾自發光區域75發出的光結合光波導管79。藉由樹脂80固定晶片71與波導管構造74,俾於晶片71與波導管 構造74之位置關係不發生偏離。
又,波導管構造74端面中,位於發光區域75正下方之端面81係相對於配線基板73表面之垂直方向傾斜形成之傾斜端面。因此,相較於端面81未傾斜時,自發光區域75發出的光朝光波導管79之結合效率獲得提升。
本實施形態例中,藉由處於熔融狀態之金屬72實現晶片71與配線基板73之連接。因此,於製造過程無需重熔金屬72。因此,不會發生因於重熔時產生之熱導致晶片71與波導管構造74偏位,易於進行光軸調整。光軸調整完畢後,藉由樹脂80固定晶片71與波導管構造74。
又,作為樹脂80,例如可使用硬化收縮率低之紫外線硬化型黏接劑。
本實施形態例中之組裝構造70雖呈配線基板73具有凹部77,金屬72注入凹部77之構造,但不限於如此之構造。例如亦可呈晶片71包含於底面具有第一電極76之凹部之構造。又,亦可將金屬72注入該凹部。或是,晶片71與配線基板73其中任一者亦可皆具有用來注入金屬72之凹部。或是,晶片71及配線基板73其中任一者亦可皆不具有凹部。
且本實施形態例中之第一電極76及第二電極78中至少一方亦可由電極焊墊與預備焊錫構成。
且於本實施形態例中之端面81亦可形成金屬膜。藉此,自發光區域75發出的光朝光波導管79之結合效率更獲得提升。
且亦可就本實施形態例組裝構造70圖9所示黑圓內之區域適 用第1實施形態例至第6實施形態例所記載之組裝構造。
上述實施形態例之一部分或全部雖亦可如以下附記記載,但不限於以下者。
(附記1)
一種組裝構造,包含:電子零件,具有第一電極;金屬,融點在130℃以下;及配線基板,具有第二電極;該第一電極與該第二電極經由該金屬電性連接,於該電子零件及該配線基板其中至少一方,形成有用來抑制該金屬朝形成該第一電極及該第二電極之區域外部流出之抑制構造。
(附記2)
如附記1之組裝構造,其中,該金屬之融點在40℃以下。
(附記3)
如附記1或2之組裝構造,其中,該抑制構造中包含於該電子零件及該配線基板其中至少任一方表面所形成之段差。
(附記4)
如附記3之組裝構造,該第一電極相對於該電子零件表面垂直方向之長度較該段差高度高。
(附記5)
如附記1至4中任一項之組裝構造,其中,該抑制構造內包含於該電子零件及該配線基板其中至少任一方表面所形成,經規則配置之柱狀構造。
(附記6)
如附記5之組裝構造,其中,該柱狀構造中心間之間距在500nm以下。
(附記7)
如附記5或6之組裝構造,其中,該柱狀構造寬高比在1以上。
(附記8)
如附記1至7中任一項之組裝構造,其中,該電子零件與該配線基板其中至少一方具有注入該金屬之凹部,於該凹部底面形成該第一電極或是該第二電極。
(附記9)
如附記8之組裝構造,其中,該配線基板具有該凹部,該凹部沿該配線基板表面面內方向之面積自該配線基板表面朝深度方向增大。
(附記10)
如附記1至9中任一項之組裝構造,其中,該電子零件與該配線基板於該金屬外周部以樹脂黏接。
(附記11)
如附記1至10中任一項之組裝構造,其中,該金屬材料係包含鎵及銦其中至少一者之合金。
(附記12)
如附記1至11中任一項之組裝構造,其中,該第一電極由第一電極焊墊,與形成於該第一電極焊墊表面之第一焊錫所構成。
(附記13)
如附記1至12中任一項之組裝構造,其中,該第一電極形成於該電子零件中,與該配線基板對向之第一面,該第一電極中,相對於該第一面垂直方向之長度大於相對於該第一面平行方向之長度。
(附記14)
如附記1至13中任一項之組裝構造,其中,該第一電極之形狀係中空形狀。
(附記15)
如附記1至14中任一項之組裝構造,其中於該第一電極及該第二電極中至少一方表面,形成寬高比在0.01以下之凹凸形狀。
(附記16)
如附記1至15中任一項之組裝構造,其中於該第一電極及該第二電極中至少一方表面形成鋁層。
(附記17)
如附記1至16中任一項之組裝構造,其中於該配線基板表面形成具有光波導管之波導管構造,該電子零件具有發光區域,該電子零件與該波導管構造由樹脂黏接之,自該發光區域發出之光結合該波導管。
(附記18)
如附記17之組裝構造,其中,該波導管構造之端面中,位於該發光區域正下方之端面係相對於該配線基板表面垂直方向傾斜形成之傾斜端面。
(附記19)
如附記18之組裝構造,其中於該傾斜端面形成金屬膜。
(附記20)
一種組裝方法,將具有第一電極之電子零件組裝於具有第二電極之配線基板,其特徵在於包含下列程序:對該第一電極上及該第二電極上其中至少任一方供給融點在130℃以下之金屬;及於該配線基板組裝該電子零件;且該第一電極與該第二電極經由該金屬電性連接,於該電子零件及該配線基板其中至少一方,形成有用來抑制該金屬朝形成該第一電極及該第二電極之區域外部流出之抑制構造。
(附記21)
如附記20之組裝方法,其中,該金屬之融點在40℃以下。
本申請案主張以於2010年11月22日所申請之日本申請案特願2010-259727號為基礎之優先權,將其所有揭示導入於此。
10、20、40、50、60、70‧‧‧組裝構造
11、21‧‧‧電子零件
12、22、72‧‧‧金屬
13、23、73‧‧‧配線基板
14、24、41、51、76‧‧‧第一電極
15、25、52、78‧‧‧第二電極
16、27‧‧‧段差
26、61、77‧‧‧凹部
28‧‧‧奈米柱構造
42‧‧‧面
43‧‧‧電極焊墊
44‧‧‧預備焊錫
71‧‧‧晶片
74‧‧‧波導管構造
75‧‧‧發光區域
79‧‧‧光波導管
80‧‧‧樹脂
81‧‧‧端面
圖1顯示本發明第1實施形態例中組裝構造構成之一例。
圖2顯示本發明第2實施形態例中組裝構造構成之一例。
圖3顯示本發明第4實施形態例中組裝構造構成之一例。
圖4顯示本發明第4實施形態例中組裝構造構成之一例。
圖5(a)、(b)顯示本發明第4實施形態例中組裝構造構成之變形例。
圖6顯示本發明第5實施形態例中組裝構造構成之一例。
圖7顯示本發明第5實施形態例中組裝構造電極之變形例。
圖8顯示本發明第6實施形態例中組裝構造構成之一例。
圖9顯示本發明第7實施形態例中組裝構造構成之一例。
10‧‧‧組裝構造
11‧‧‧電子零件
12‧‧‧金屬
13‧‧‧配線基板
14‧‧‧第一電極
15‧‧‧第二電極
16‧‧‧段差

Claims (9)

  1. 一種組裝構造,包含:電子零件,具有第一電極;金屬,融點在130℃以下;配線基板,具有經由該金屬電性連接該第一電極之第二電極;及抑制構造,備於形成有該電子零件及該配線基板其中至少任一方之該第一電極及該第二電極之區域外部,抑制熔融狀態之該金屬流出;該配線基板具有注入該金屬之凹部,於該凹部底面形成該第一電極或是該第二電極,且該抑制構造包含形成於該電子零件及該配線基板其中至少一方之表面,呈規則配置之柱狀構造。
  2. 如申請專利範圍第1項之組裝構造,其中,該金屬之融點在40℃以下。
  3. 如申請專利範圍第1或2項之組裝構造,其中,該抑制構造包含於該電子零件及該配線基板其中至少任一方之表面所形成之段差。
  4. 如申請專利範圍第1或2項之組裝構造,其中,該凹部沿該配線基板表面之面內方向的面積,係自該配線基板表面朝深度方向增大。
  5. 如申請專利範圍第1或2項之組裝構造,其中,該金屬材料係包含鎵及銦其中至少一者之合金。
  6. 如申請專利範圍第1或2項之組裝構造,其中,該第一電極形成於該電子零件中,與該配線基板對向之第一面,該第一電極中,垂直於該第一面的方向之長度大於平行於該 第一面的方向之長度。
  7. 如申請專利範圍第1或2項之組裝構造,其中,該配線基板表面形成具有光波導管之波導管構造,該電子零件具有發光區域,該電子零件與該波導管構造由樹脂黏接之,自該發光區域發出之光結合該波導管。
  8. 如申請專利範圍第1或2項之組裝構造,其中於該第一電極及該第二電極中至少一方之表面形成寬高比在0.01以下之凹凸形狀。
  9. 一種組裝方法,將具有第一電極之電子零件,組裝於具有第二電極之配線基板,其特徵在於包含下列程序:對該第一電極上及該第二電極上其中至少任一方供給融點在130℃以下之金屬;及於該配線基板組裝該電子零件;且該第一電極與該第二電極經由該金屬電性連接,於該電子零件及該配線基板其中至少一方之形成有該第一電極及該第二電極之區域外部,形成用來抑制該金屬流出之抑制構造,該配線基板具有注入該金屬之凹部,於該凹部底面形成該第一電極或是該第二電極,且該抑制構造包含形成於該電子零件及該配線基板其中至少一方之表面,呈規則配置之柱狀構造。
TW100142265A 2010-11-22 2011-11-18 組裝構造及組裝方法 TWI461125B (zh)

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5662386B2 (ja) * 2012-07-26 2015-01-28 日本電信電話株式会社 集積型光モジュール
US11282717B2 (en) 2018-03-30 2022-03-22 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
US10340249B1 (en) * 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513496A (ja) * 1991-06-28 1993-01-22 Toshiba Corp 半導体素子の実装方法
JPH0550777U (ja) * 1991-12-12 1993-07-02 ケル株式会社 表面実装用プリント基板
CN1475824A (zh) * 2002-07-29 2004-02-18 ������������ʽ���� 二维光导波装置和使用该装置的光电融合布线基板
TW200903758A (en) * 2007-06-26 2009-01-16 Shinko Electric Ind Co Semiconductor device and method of manufacturing the same
TW200918287A (en) * 2007-08-28 2009-05-01 Agency Science Tech & Res A method of manufacturing an organic electronic or optoelectronic device
JP2010103161A (ja) * 2008-10-21 2010-05-06 Fujitsu Microelectronics Ltd 半導体装置及び電子部品

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685771B2 (ja) 1985-09-30 1994-11-02 ジーイー横河メディカルシステム株式会社 X線断層撮影装置
JPS6274335U (zh) * 1985-10-29 1987-05-13
JPH0423388A (ja) 1990-05-14 1992-01-27 Matsushita Electric Ind Co Ltd プリント基板
JPH04240741A (ja) 1991-01-24 1992-08-28 Matsushita Electric Ind Co Ltd 半導体装置
JPH0550777A (ja) 1991-08-28 1993-03-02 Fujitsu General Ltd 印刷マスク構造
JPH07221421A (ja) 1994-02-01 1995-08-18 Fujitsu Ltd 電気的接続方法及び装置
US6365500B1 (en) * 1994-05-06 2002-04-02 Industrial Technology Research Institute Composite bump bonding
JP3446508B2 (ja) 1996-12-03 2003-09-16 松下電器産業株式会社 バンプ付きワークの実装方法および実装基板
JPH11163049A (ja) 1997-11-28 1999-06-18 Matsushita Electric Ind Co Ltd バンプ付電子部品の実装構造および実装方法
US6392144B1 (en) * 2000-03-01 2002-05-21 Sandia Corporation Micromechanical die attachment surcharge
JP2003020404A (ja) 2001-07-10 2003-01-24 Hitachi Ltd 耐熱性低弾性率材およびそれを用いた装置
JP3727582B2 (ja) 2001-12-20 2005-12-14 シチズン電子株式会社 半導体装置
JP4672576B2 (ja) 2006-03-09 2011-04-20 富士通株式会社 電子デバイス及びその製造方法
JP2008047655A (ja) * 2006-08-11 2008-02-28 Mitsui Mining & Smelting Co Ltd 配線基板およびその製造方法
JP4969379B2 (ja) * 2007-09-14 2012-07-04 新光電気工業株式会社 光導波路搭載基板及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513496A (ja) * 1991-06-28 1993-01-22 Toshiba Corp 半導体素子の実装方法
JPH0550777U (ja) * 1991-12-12 1993-07-02 ケル株式会社 表面実装用プリント基板
CN1475824A (zh) * 2002-07-29 2004-02-18 ������������ʽ���� 二维光导波装置和使用该装置的光电融合布线基板
TW200903758A (en) * 2007-06-26 2009-01-16 Shinko Electric Ind Co Semiconductor device and method of manufacturing the same
TW200918287A (en) * 2007-08-28 2009-05-01 Agency Science Tech & Res A method of manufacturing an organic electronic or optoelectronic device
JP2010103161A (ja) * 2008-10-21 2010-05-06 Fujitsu Microelectronics Ltd 半導体装置及び電子部品

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