TWI456714B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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Publication number
TWI456714B
TWI456714B TW097144932A TW97144932A TWI456714B TW I456714 B TWI456714 B TW I456714B TW 097144932 A TW097144932 A TW 097144932A TW 97144932 A TW97144932 A TW 97144932A TW I456714 B TWI456714 B TW I456714B
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TW
Taiwan
Prior art keywords
pattern
insulating film
semiconductor substrate
rewiring
region
Prior art date
Application number
TW097144932A
Other languages
English (en)
Chinese (zh)
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TW200941664A (en
Inventor
小出優樹
南正隆
Original Assignee
瑞薩電子股份有限公司
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Publication date
Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW200941664A publication Critical patent/TW200941664A/zh
Application granted granted Critical
Publication of TWI456714B publication Critical patent/TWI456714B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW097144932A 2008-02-14 2008-11-20 半導體裝置及半導體裝置之製造方法 TWI456714B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008033012A JP5007250B2 (ja) 2008-02-14 2008-02-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200941664A TW200941664A (en) 2009-10-01
TWI456714B true TWI456714B (zh) 2014-10-11

Family

ID=40954354

Family Applications (1)

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TW097144932A TWI456714B (zh) 2008-02-14 2008-11-20 半導體裝置及半導體裝置之製造方法

Country Status (4)

Country Link
US (3) US7812456B2 (https=)
JP (1) JP5007250B2 (https=)
CN (1) CN101510536B (https=)
TW (1) TWI456714B (https=)

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JP5415710B2 (ja) * 2008-04-10 2014-02-12 ルネサスエレクトロニクス株式会社 半導体装置
US8610283B2 (en) 2009-10-05 2013-12-17 International Business Machines Corporation Semiconductor device having a copper plug
US8759209B2 (en) 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
JP5587702B2 (ja) * 2010-08-26 2014-09-10 株式会社テラプローブ 半導体装置及び半導体装置の製造方法
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
US8581389B2 (en) * 2011-05-27 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Uniformity control for IC passivation structure
JP5605520B2 (ja) * 2012-03-22 2014-10-15 株式会社村田製作所 半導体装置および半導体モジュール
JP5826716B2 (ja) 2012-06-19 2015-12-02 株式会社東芝 半導体装置及びその製造方法
US9136221B2 (en) * 2012-09-28 2015-09-15 Intel Corporation Methods of providing dielectric to conductor adhesion in package structures
JP6435860B2 (ja) 2012-11-05 2018-12-19 大日本印刷株式会社 配線構造体
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JP6221074B2 (ja) * 2013-03-22 2017-11-01 パナソニックＩｐマネジメント株式会社 半導体装置
JP2015018958A (ja) 2013-07-11 2015-01-29 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 実装構造体および実装構造体製造方法
JP6299406B2 (ja) * 2013-12-19 2018-03-28 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
JP6658782B2 (ja) * 2013-12-19 2020-03-04 ソニー株式会社 半導体装置の製造方法
EP3220410A4 (en) * 2014-11-13 2018-07-18 Renesas Electronics Corporation Semiconductor device and manufacturing method for same
JP2017045865A (ja) * 2015-08-26 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN105575935A (zh) * 2016-02-25 2016-05-11 中国电子科技集团公司第十三研究所 Cmos驱动器晶圆级封装及其制作方法
US9922920B1 (en) 2016-09-19 2018-03-20 Nanya Technology Corporation Semiconductor package and method for fabricating the same
JP6814698B2 (ja) * 2017-06-05 2021-01-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6872991B2 (ja) * 2017-06-29 2021-05-19 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2019114750A (ja) 2017-12-26 2019-07-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102432627B1 (ko) 2018-01-11 2022-08-17 삼성전자주식회사 반도체 패키지
JP7063027B2 (ja) * 2018-03-19 2022-05-09 Tdk株式会社 薄膜コンデンサおよび薄膜コンデンサの製造方法
US11302734B2 (en) 2018-06-29 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench isolation structures resistant to cracking
US20200058646A1 (en) * 2018-08-14 2020-02-20 Intel Corporation Structures and methods for large integrated circuit dies
JP2020077743A (ja) * 2018-11-07 2020-05-21 日立化成株式会社 積層体及び半導体パッケージ
KR102565831B1 (ko) 2019-01-28 2023-08-09 양쯔 메모리 테크놀로지스 씨오., 엘티디. 더미 패턴을 설계하는 시스템 및 방법
KR102494920B1 (ko) 2019-05-21 2023-02-02 삼성전자주식회사 반도체 패키지
US10971447B2 (en) * 2019-06-24 2021-04-06 International Business Machines Corporation BEOL electrical fuse
TWI754997B (zh) 2019-07-31 2022-02-11 日商村田製作所股份有限公司 半導體裝置及高頻模組
JP2021197474A (ja) 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置
KR20230013677A (ko) 2021-07-16 2023-01-27 삼성전자주식회사 더미 패턴을 포함하는 반도체 패키지
CN121002653A (zh) * 2023-07-13 2025-11-21 株式会社力森诺科 配线基板的制造方法、半导体装置的制造方法、配线基板及半导体装置

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Also Published As

Publication number Publication date
US20090206490A1 (en) 2009-08-20
US8274157B2 (en) 2012-09-25
US8558391B2 (en) 2013-10-15
CN101510536B (zh) 2012-07-18
US20110001236A1 (en) 2011-01-06
CN101510536A (zh) 2009-08-19
US20130001772A1 (en) 2013-01-03
JP5007250B2 (ja) 2012-08-22
TW200941664A (en) 2009-10-01
JP2009194144A (ja) 2009-08-27
US7812456B2 (en) 2010-10-12

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