TWI456580B - 積體電路架構 - Google Patents

積體電路架構 Download PDF

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Publication number
TWI456580B
TWI456580B TW099110304A TW99110304A TWI456580B TW I456580 B TWI456580 B TW I456580B TW 099110304 A TW099110304 A TW 099110304A TW 99110304 A TW99110304 A TW 99110304A TW I456580 B TWI456580 B TW I456580B
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Taiwan
Prior art keywords
power supply
supply line
memory
data retention
integrated circuit
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TW099110304A
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English (en)
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TW201037720A (en
Inventor
Cheng Hung Lee
Hung Jen Liao
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Taiwan Semiconductor Mfg
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Publication of TW201037720A publication Critical patent/TW201037720A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Claims (19)

  1. 一種積體電路架構，包括：一主動電源供應線；一資料保持電源供應線；以及一記憶體巨集，連接至該主動電源供應線與該資料保持電源供應線，該記憶體巨集包括：一記憶體晶格陣列；一開關，用以切換該記憶體晶格陣列，而使其連接至該主動電源供應線，或使其連接至該資料保持電源供應線，其中該資料保持電源供應線位於該記憶體巨集之外部；一低漏電流模式控制腳位，由該記憶體巨集之內部連接至該記憶體巨集之外部；以及一控制邏輯電路，連接於該低漏電流模式控制腳位與該開關，其中該控制邏輯電路用以依據該低漏電流模式控制腳位上之一訊號操作該開關。
  2. 如申請專利範圍第1項所述之積體電路架構，其中該資料保持電源供應線與該主動電源供應線連接至複數個記憶體巨集。
  3. 如申請專利範圍第2項所述之積體電路架構，其中一半導體晶片上之所有記憶體巨集皆連接至該資料保持電源供應線與該主動電源供應線。
  4. 如申請專利範圍第1項所述之積體電路架構，其中該等記憶體巨集係位於一記憶體編譯晶片之中。
  5. 如申請專利範圍第1項所述之積體電路架構，其中該資料保持電源供應線具有一第一截面積，其小於該主動電源供應線之一第二截面積。
  6. 如申請專利範圍第5項所述之積體電路架構，其中該第二截面積是該第一截面積的十倍以上。
  7. 如申請專利範圍第1項所述之積體電路架構，其中該資料保持電源供應線承載一第一正電壓，其低於該主動電源供應線所承載的一第二正電壓。
  8. 如申請專利範圍第1項所述之積體電路架構，其中該開關包括：一第一開關，將該主動電源供應線連接至該記憶體陣列；以及一第二開關，將該資料保持電源供應線連接該記憶體陣列。
  9. 一種積體電路架構，包括：一主動電源供應線；一資料保持電源供應線；以及一第一記憶體巨集與一第二記憶體巨集，連接至該主動電源供應線與該資料保持電源供應線，其中該第一記憶體巨集包括：一第一記憶體晶格陣列；一第一開關，用以切換該第一記憶體晶格陣列，而使其連接至該主動電源供應線，或使其連接至該資料保持電源供應線；以及一第一低漏電流模式控制腳位，耦接至該第一開 關，其中該第一開關用以依據該第一低漏電流模式控制腳位上之一第一訊號將該主動電源供應線與該資料保持電源供應線連接至該第一記憶體晶格陣列；以及其中該第二記憶體巨集包括：一第二記憶體晶格陣列；一第二開關，用以切換該第二記憶體晶格陣列，而使其連接至該主動電源供應線，或使其連接至該資料保持電源供應線；以及一第二低漏電流模式控制腳位，耦接至該第二開關，其中該第二開關用以依據該第二低漏電流模式控制腳位上之一第二訊號將該主動電源供應線與該資料保持電源供應線連接至該第二記憶體晶格陣列。
  10. 如申請專利範圍第9項所述之積體電路架構，其中該第一記憶體巨集與該第二記憶體巨集完全相同。
  11. 如申請專利範圍第9項所述之積體電路架構，其中該第一記憶體巨集不同於該第二記憶體巨集。
  12. 如申請專利範圍第9項所述之積體電路架構，其中該資料保持電源供應線具有一第一截面積，其小於該主動電源供應線之一第二截面積。
  13. 如申請專利範圍第12項所述之積體電路架構，其中該第二截面積是該第一截面積的一百倍以上。
  14. 如申請專利範圍第9項所述之積體電路架構，其中該資料保持電源供應線承載較該主動電源供應線所承載低的電壓。
  15. 如申請專利範圍第9項所述之積體電路架構，其 中該第一記憶體巨集與該第二記憶體巨集皆是一記憶體編譯晶片之一部分。
  16. 一種積體電路架構，包括：一第一主動電源供應線；一第二主動電源供應線，與該第一主動電源供應線分離；一第一資料保持電源供應線；一第二資料保持電源供應線，與該第一資料保持電源供應線分離；一第一記憶體巨集，連接至該第一主動電源供應線與該第一資料保持電源供應線，其中該第一記憶體巨集包括：一第一記憶體晶格陣列；以及一第一開關，將該第一記憶體晶格陣列連接至該第一主動電源供應線與該第一資料保持電源供應線，其中該第一資料保持電源供應線位於該第一記憶體巨集之外部；以及一第二記憶體巨集，連接至該第二主動電源供應線與該第二資料保持電源供應線，其中該第二記憶體巨集包括：一第二記憶體晶格陣列；以及一第二開關，將該第二記憶體晶格陣列連接至該第二主動電源供應線與該第二資料保持電源供應線，其中該第二資料保持電源供應線位於該第二記憶體巨集之外部。
  17. 如申請專利範圍第16項所述之積體電路架構，其中該第一主動電源供應線與該第一資料保持電源供應線連接至一第一記憶體巨集群組，而其中該第二主動電源供應線與該第二資料保持電源供應線係連接至一第二記憶體巨集群組。
  18. 如申請專利範圍第16項所述之積體電路架構，其中該第一主動電源供應線之截面積大於該第一資料保持電源供應線之截面積。
  19. 如申請專利範圍第16項所述之積體電路架構，其中該第一資料保持電源供應線承載與該第二資料保持電源供應線不同之電壓。
TW099110304A 2009-04-03 2010-04-02 積體電路架構 TWI456580B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16655609P 2009-04-03 2009-04-03
US12/694,032 US8406075B2 (en) 2009-04-03 2010-01-26 Ultra-low leakage memory architecture

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TW201037720A TW201037720A (en) 2010-10-16
TWI456580B true TWI456580B (zh) 2014-10-11

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US (1) US8406075B2 (zh)
JP (1) JP5574365B2 (zh)
KR (1) KR20100110752A (zh)
CN (1) CN101859600B (zh)
TW (1) TWI456580B (zh)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8139436B2 (en) 2009-03-17 2012-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits, systems, and methods for reducing leakage currents in a retention mode
JP2011123970A (ja) * 2009-12-14 2011-06-23 Renesas Electronics Corp 半導体記憶装置
US20130135955A1 (en) * 2011-11-29 2013-05-30 Edward M. McCombs Memory device including a retention voltage resistor
JP2013191262A (ja) * 2012-03-15 2013-09-26 Elpida Memory Inc 半導体装置
TWI498892B (zh) * 2013-09-27 2015-09-01 Univ Nat Cheng Kung 靜態隨機存取記憶體之自適應性資料保持電壓調節系統
US8929169B1 (en) * 2014-05-13 2015-01-06 Sandisk Technologies Inc. Power management for nonvolatile memory array
US9343119B2 (en) * 2014-09-05 2016-05-17 Intel Corporation Bus circuits for memory devices
JP2016092536A (ja) * 2014-10-31 2016-05-23 ルネサスエレクトロニクス株式会社 半導体装置
US9350332B1 (en) * 2015-02-11 2016-05-24 SK Hynix Inc. Semiconductor device including retention circuit
US10102899B2 (en) * 2015-03-31 2018-10-16 Renesas Electronics Corporation Semiconductor device
US9977480B2 (en) 2015-04-15 2018-05-22 Qualcomm Incorporated Selective coupling of power rails to a memory domain(s) in a processor-based system
US10050448B2 (en) 2015-04-15 2018-08-14 Qualcomm Incorporated Providing current cross-conduction protection in a power rail control system
US9690359B2 (en) * 2015-08-26 2017-06-27 Qualcomm Incorporated Power multiplexer for integrated circuit power grid efficiency
US10684671B2 (en) 2016-05-27 2020-06-16 Qualcomm Incorporated Adaptively controlling drive strength of multiplexed power from supply power rails in a power multiplexing system to a powered circuit
US10394471B2 (en) 2016-08-24 2019-08-27 Qualcomm Incorporated Adaptive power regulation methods and systems
US10199091B2 (en) * 2016-12-08 2019-02-05 Intel Corporation Retention minimum voltage determination techniques
KR102685346B1 (ko) * 2017-02-17 2024-07-15 에스케이하이닉스 주식회사 파워 메쉬 구조를 갖는 반도체 메모리 장치
US10396778B1 (en) * 2017-05-31 2019-08-27 Apple Inc. Method for power gating for wide dynamic voltage range operation
US10607660B2 (en) * 2017-07-20 2020-03-31 Samsung Electronics Co., Ltd. Nonvolatile memory device and operating method of the same
US10664035B2 (en) * 2017-08-31 2020-05-26 Qualcomm Incorporated Reconfigurable power delivery networks
US11133039B2 (en) * 2018-10-12 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Power switch control in a memory device
DE102019126972A1 (de) * 2018-10-12 2020-04-16 Taiwan Semiconductor Manufacturing Co., Ltd. Netzschaltersteuerung in einer Speichervorrichtung
US11790978B2 (en) * 2019-09-23 2023-10-17 Intel Corporation Register file with write pre-charge
US11689204B1 (en) * 2022-08-23 2023-06-27 Ambiq Micro, Inc. Memory module with fine-grained voltage adjustment capabilities

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6836175B2 (en) * 2002-12-06 2004-12-28 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit with sleep memory
US20070070769A1 (en) * 2005-09-26 2007-03-29 International Business Machines Corporation Circuit and method for controlling a standby voltage level of a memory
US7327630B2 (en) * 2005-01-13 2008-02-05 Samsung Electronics Co., Ltd. Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage
US7362646B2 (en) * 2006-03-13 2008-04-22 Kabushiki Kaisha Toshiba Semiconductor memory device
US7436206B2 (en) * 2006-10-18 2008-10-14 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit
US7436205B2 (en) * 2006-02-24 2008-10-14 Renesas Technology Corp. Semiconductor device reducing power consumption in standby mode

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247386A (ja) * 1997-03-03 1998-09-14 Mitsubishi Electric Corp 昇圧電位供給回路及び半導体記憶装置
KR100269643B1 (ko) * 1997-11-27 2000-10-16 김영환 전력소비 억제회로
JP3080062B2 (ja) * 1998-04-06 2000-08-21 日本電気株式会社 半導体集積回路
JP2000021169A (ja) 1998-04-28 2000-01-21 Mitsubishi Electric Corp 同期型半導体記憶装置
JP3982915B2 (ja) 1998-07-15 2007-09-26 芝浦メカトロニクス株式会社 ペレットボンディング装置
KR100582380B1 (ko) * 1999-06-30 2006-05-23 주식회사 하이닉스반도체 동작모드에 따라 선별적으로 파워를 공급하는 파워공급장치
JP2001052476A (ja) * 1999-08-05 2001-02-23 Mitsubishi Electric Corp 半導体装置
JP2002064150A (ja) * 2000-06-05 2002-02-28 Mitsubishi Electric Corp 半導体装置
US6343044B1 (en) * 2000-10-04 2002-01-29 International Business Machines Corporation Super low-power generator system for embedded applications
US6434076B1 (en) * 2001-01-22 2002-08-13 International Business Machines Corporation Refresh control circuit for low-power SRAM applications
DE10120790A1 (de) * 2001-04-27 2002-11-21 Infineon Technologies Ag Schaltungsanordnung zur Verringerung der Versorgungsspannung eines Schaltungsteils sowie Verfahren zum Aktivieren eines Schaltungsteils
JP2007251173A (ja) * 2001-06-05 2007-09-27 Renesas Technology Corp 半導体装置の製造方法
JP2003110022A (ja) * 2001-09-28 2003-04-11 Mitsubishi Electric Corp 半導体集積回路
JP2003168735A (ja) * 2001-11-30 2003-06-13 Hitachi Ltd 半導体集積回路装置
DE10218339B4 (de) * 2002-04-24 2005-04-21 Südrad GmbH Radtechnik Scheibenrad aus Blech für Kraftfahrzeuge und Verfahren für dessen Herstellung
WO2004013909A1 (ja) * 2002-08-02 2004-02-12 Hitachi, Ltd. メモリを内蔵した半導体集積回路
US7170327B2 (en) * 2003-06-27 2007-01-30 Intel Corporation System and method for data retention with reduced leakage current
US7227804B1 (en) * 2004-04-19 2007-06-05 Cypress Semiconductor Corporation Current source architecture for memory device standby current reduction
DE102004036956B3 (de) * 2004-07-30 2006-03-23 Infineon Technologies Ag Logik-Aktivierungsschaltung
US7372764B2 (en) * 2004-08-11 2008-05-13 Stmicroelectronics Pvt. Ltd. Logic device with reduced leakage current
KR100667931B1 (ko) * 2004-11-15 2007-01-11 삼성에스디아이 주식회사 플라즈마 디스플레이 패널
US7274217B2 (en) * 2005-04-07 2007-09-25 International Business Machines Corporation High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs
US7394687B2 (en) * 2005-05-09 2008-07-01 Nantero, Inc. Non-volatile-shadow latch using a nanotube switch
JP2006332423A (ja) * 2005-05-27 2006-12-07 Kawasaki Microelectronics Kk メモリマクロおよび半導体集積回路設計装置
US7852113B2 (en) * 2005-08-16 2010-12-14 Novelics, Llc. Leakage control
KR100776738B1 (ko) * 2006-04-06 2007-11-19 주식회사 하이닉스반도체 반도체 메모리 장치
CN101060007B (zh) * 2006-04-17 2010-10-06 科统科技股份有限公司 复合存储器芯片
KR100718046B1 (ko) * 2006-06-08 2007-05-14 주식회사 하이닉스반도체 반도체 메모리 장치
JP4199793B2 (ja) * 2006-09-13 2008-12-17 エルピーダメモリ株式会社 半導体装置
CN100589207C (zh) * 2006-10-12 2010-02-10 中兴通讯股份有限公司 一种电荷泵输出高压的控制装置
US7408830B2 (en) * 2006-11-07 2008-08-05 Taiwan Semiconductor Manufacturing Co. Dynamic power supplies for semiconductor devices
US7863971B1 (en) * 2006-11-27 2011-01-04 Cypress Semiconductor Corporation Configurable power controller
JP2008146784A (ja) * 2006-12-13 2008-06-26 Elpida Memory Inc 半導体記憶装置
US7447101B2 (en) * 2006-12-22 2008-11-04 Fujitsu Limited PG-gated data retention technique for reducing leakage in memory cells
JP2008159145A (ja) 2006-12-22 2008-07-10 Elpida Memory Inc 半導体記憶装置
US7623405B2 (en) * 2007-02-15 2009-11-24 Stmicroelectronics, Inc. SRAM with switchable power supply sets of voltages
JP4951786B2 (ja) * 2007-05-10 2012-06-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7570537B2 (en) * 2007-07-12 2009-08-04 Sun Microsystems, Inc. Memory cells with power switch circuit for improved low voltage operation
JP5333219B2 (ja) * 2007-08-09 2013-11-06 富士通株式会社 半導体集積回路
US7760011B2 (en) * 2007-08-10 2010-07-20 Texas Instruments Incorporated System and method for auto-power gating synthesis for active leakage reduction
US7848172B2 (en) * 2008-11-24 2010-12-07 Agere Systems Inc. Memory circuit having reduced power consumption
KR101020293B1 (ko) * 2009-02-12 2011-03-07 주식회사 하이닉스반도체 반도체 메모리 장치
KR101612298B1 (ko) * 2009-03-13 2016-04-14 삼성전자주식회사 파워 게이팅 회로 및 이를 포함하는 집적 회로

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6836175B2 (en) * 2002-12-06 2004-12-28 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit with sleep memory
US7327630B2 (en) * 2005-01-13 2008-02-05 Samsung Electronics Co., Ltd. Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage
US20070070769A1 (en) * 2005-09-26 2007-03-29 International Business Machines Corporation Circuit and method for controlling a standby voltage level of a memory
US7436205B2 (en) * 2006-02-24 2008-10-14 Renesas Technology Corp. Semiconductor device reducing power consumption in standby mode
US7362646B2 (en) * 2006-03-13 2008-04-22 Kabushiki Kaisha Toshiba Semiconductor memory device
US7436206B2 (en) * 2006-10-18 2008-10-14 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit

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CN101859600B (zh) 2017-06-09
JP5574365B2 (ja) 2014-08-20
CN101859600A (zh) 2010-10-13
TW201037720A (en) 2010-10-16
US8406075B2 (en) 2013-03-26
JP2010263194A (ja) 2010-11-18
US20100254209A1 (en) 2010-10-07
KR20100110752A (ko) 2010-10-13

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