TWI455256B - 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻 - Google Patents

以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻 Download PDF

Info

Publication number
TWI455256B
TWI455256B TW101129758A TW101129758A TWI455256B TW I455256 B TWI455256 B TW I455256B TW 101129758 A TW101129758 A TW 101129758A TW 101129758 A TW101129758 A TW 101129758A TW I455256 B TWI455256 B TW I455256B
Authority
TW
Taiwan
Prior art keywords
heat
semiconductor package
active layer
lead
layer
Prior art date
Application number
TW101129758A
Other languages
English (en)
Other versions
TW201318115A (zh
Inventor
Richard K Williams
Original Assignee
Advanced Analogic Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Analogic Tech Inc filed Critical Advanced Analogic Tech Inc
Publication of TW201318115A publication Critical patent/TW201318115A/zh
Application granted granted Critical
Publication of TWI455256B publication Critical patent/TWI455256B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻
本申請案與標題為「Bump-on-Leadframe(BOL)Package Technology with Reduced Parasitics」之於2006年5月2日提出申請之第11/381,292號申請案相關，該申請案之全文以引用之方式併入本文中。
絕緣物上矽半導體晶粒用於其中期望在形成於晶粒中之半導體裝置之間提供一極有效之絕緣障壁之應用中。一絕緣物上矽(SOI)晶粒由三層組成：(1)一作用層，其中形成有半導體裝置，(2)一絕緣層，及(3)一處置層。絕緣層夾在作用層與處置層之間。作用層及處置層由矽形成；絕緣層通常由二氧化矽(經常簡單地稱為「氧化物」)形成。絕緣層亦可由熱生長氧化物與經沈積玻璃或氧化物之一夾層組成。處置層通常係三個層中最厚的。由於作用層及處置層由矽形成且因此具有相同溫度膨脹係數，因此晶粒係極熱穩定的。此外，由於絕緣層提供一強絕緣障壁，因此形成於作用層中之裝置可使用延伸穿過作用層之隔離結構極有效地彼此電絕緣。
圖1A展示含有一SOI晶粒3之一習用SOT狀半導體封裝1之一剖面圖。SOT或「小型電晶體」係用於封裝離散電晶體或低接針計數積體電路之一行業標準封裝。SOI晶粒3包含一作用層3A、一絕緣層3I及一處置層3H。SOI晶粒3經由處置層3H之經曝露表面安裝至一引線2B。作用層3A中之裝置(未展示)經由作用層3A之表面處之接觸襯墊(未展 示)且經由接合線4A及4B電連接至引線2A及2B。「鷗翼」引線2A及2B自模製化合物5突出。引線2A及2B之下部表面安裝至一印刷電路板(PCB)6。
圖1B展示含有一SOI晶粒13之一習用雙邊扁平無引線(DFN)半導體封裝11之一剖面圖。SOI晶粒13包含一作用層13A、一絕緣層13I及一處置層13H。SOI晶粒13經由處置層13H之經曝露表面安裝至一散熱塊12B。作用層13A中之裝置(未展示)經由作用層13A之表面處之接觸襯墊(未展示)且經由接合線14A及14B電連接至引線12A及12C。引線12A及12C具有與模製化合物15之側表面及底部表面共面之外部表面，亦即，不同於圖1A中之引線2A及2B，引線12A及12C不自模製化合物15突出。引線12A及12C以及散熱塊12B之下部表面用以將封裝11安裝至一PCB 16。
不幸地，一SOI晶粒之良好電絕緣性質形成熱問題，此乃因由形成於作用層中之裝置產生之熱被絕緣層陷獲。在封裝1及11中，舉例而言，SOI晶粒3及13之作用層藉由絕緣層及處置層而與引線實體及熱分離(接合線通常極薄且不轉移顯著熱量)。用於絕緣層之材料(諸如二氧化矽)經常係良好熱絕緣物。因此，作用層中之溫度可達到不可接受之高位準且可損壞或毀壞形成於SOI晶粒中之裝置。
因此，給一SOI晶粒提供促進移除由形成於晶粒中之半導體裝置產生之熱之一半導體封裝將係極有用的。自一電及熱兩者之觀點，此一解決方案將允許SOI晶粒達到其全部潛力。
在根據本發明之一半導體封裝中，一絕緣物上矽(SOI)晶粒以一引線架上凸塊(BOL)或「覆晶」方式定向使得在作用層面向一引線且一焊料或其他金屬凸塊連接該作用層之一表面處之一接觸襯墊與該引線。焊料可包括一合金、二元或三元金屬化合物(諸如鉛-錫(Pb-Sn)或錫-銀(Sn-Ag))，或者可包括任何軟金屬(諸如金、銀或錫)。此形成一熱路徑，透過該熱路徑產生於作用層中之熱可容易地轉移至封裝所安裝於其上之一印刷電路板或其他結構。
本發明可應用於各種各樣的封裝，包含SOT狀及DFN封裝。
在某些實施例中，SOI晶粒之作用層由絕緣溝渠分離成熱島，每一熱島藉助一或多個焊料凸塊連接至一引線。
藉由參考以下圖式將更佳地理解本發明，該等圖式未必按比例繪製且其中相似組件具有類似元件符號。
圖2A圖解說明根據本發明之一經模製SOT狀封裝30。封裝30含有具有一處置層22、一絕緣層23及一作用層24之一SOI晶粒21。SOI晶粒21分別藉助焊料凸塊34A及34B以引線架上凸塊(BOL)或「覆晶」樣式安裝於引線2A及2B上。SOI晶粒21經定向以使得作用層24面向引線2A及2B。焊料凸塊34A及34B分別與位於作用層24之表面處之接觸襯墊25A及25B進行電接觸且自其向下延伸。焊料凸塊34A及34B可由用於半導體封裝中之任何類型之焊料製成，舉例 而言，一鉛-錫(Pb-Sn)或錫-銀(Sn-Ag)焊料或者一軟金屬(諸如純錫(Sn)、純銀(Ag)或金(Au))。
SOI晶粒21、焊料凸塊34A及34B以及引線2A及2B之部分圍封於通常由塑膠製成之一模製化合物5中。通常由一金屬(諸如鋁)製成之「鷗翼」形引線2A及2B自模製化合物5突出且安裝至一印刷電路板(PCB)6。
作用層24通常含有複數個半導體裝置(MOSFET、雙極電晶體、二極體等)，當作用層24中之電路操作時，該複數個半導體裝置中之某些裝置可產生實質熱量。如圖2A中所展示，存在產生於作用層24中之熱可藉由其傳導至PCB 6之兩個熱路徑：第一路徑包含接觸襯墊25A、焊料凸塊34A及引線2A，且第二路徑包含接觸襯墊25B、焊料凸塊34B及引線2B。此等熱路徑中之每一者亦可用作連接SOI晶粒中之電路與PCB 6之一電路徑。
封裝30之熱轉移特性遠優於圖1A中所展示之可比較之先前技術封裝1之彼等熱轉移特性，此乃因存在兩個高度傳導熱路徑，透過該兩個高度傳導熱路徑可將產生於SOI晶粒21中之熱轉移至PCB 6。此外，藉由輻射及對流自引線2A及2B移除產生於SOI晶粒21中之熱中之某些熱。
用於製作封裝30之製程係此項技術中眾所周知的。在一例示性製程中，最初將焊料球放置於接觸襯墊25A及25B上且將其充分加熱以致使焊料黏附至該等接觸襯墊。可藉由穿過一「模板」遮罩將焊料球滴落至晶粒上以使得該等球僅落至該等球意欲黏附至其之接合襯墊之頂部上或緊鄰 處之晶粒上來配置該等球之放置。然後，將SOI晶粒21倒置，且使得焊料球分別與引線2A及2B接觸，彼時引線2A及2B仍係一引線架之部分。然後，將焊料再次加熱(回流)以使得焊料球形成黏附至接觸襯墊25A及引線2A之焊料凸塊34A以及黏附至接觸襯墊25B及引線2B之焊料凸塊34B。一旦焊料凸塊34A及34B黏附至SOI晶粒21以及引線2A及2B，便藉由一注射模製製程將總成圍封於模製化合物5中，然後將該等引線與引線架中之其他引線單粒化。
圖2B圖解說明安裝於一雙邊扁平無引線(DFN)封裝40中之SOI晶粒21。SOI晶粒21分別藉助焊料凸塊44A及44B以BOL樣式安裝於引線12A及12B上。焊料凸塊44A及44B分別與接觸襯墊25A及25B進行電接觸且自其向下延伸。
SOI晶粒21、焊料凸塊44A及44B以及引線12A及12B圍封於通常由塑膠製成之一模製化合物15中。不同於自模製化合物5突出的封裝30中之鷗翼形引線2A及2B，引線12A及12B具有與模製化合物15之一底部表面15B共面之底部表面12AB及12BB以及與模製化合物15之橫向表面15A及15C共面之橫向表面12AL及12BL。引線12A及12B之底部表面12AB及12BB安裝至印刷電路板(PCB)6。
如圖2B中所展示，存在產生於作用層24中之熱可藉由其傳導至PCB 6之兩個熱路徑：第一路徑包含接觸襯墊25A、焊料凸塊44A及引線12A，且第二路徑包含接觸襯墊25B、焊料凸塊44B及引線12B。此等熱路徑中之每一者亦可用作連接SOI晶粒21中之電路與PCB 6之一電路徑。
封裝40之熱轉移特性遠優於圖1B中所展示之可比較之先前技術封裝11之彼等熱轉移特性，此乃因存在兩個高度傳導熱路徑，藉由該兩個高度傳導熱路徑可將產生於SOI晶粒21中之熱轉移至PCB 6。
圖3A圖解說明根據本發明之一經模製SOT狀封裝50。封裝50含有具有一處置層22A、一絕緣層23A及一作用層24A之一SOI晶粒21A以及一經曝露晶粒襯墊或散熱塊2C。接觸襯墊25A、25B及25C位於作用層24A之經曝露表面處。在其他方面，封裝50類似於圖2A中所展示之封裝30，惟封裝50中之模製化合物5之一底部表面29與引線2A及2B之安裝表面2AM及2BM共面除外。在封裝50中，SOI晶粒21A分別藉助焊料凸塊34A、34B及34C以BOL樣式安裝於引線2A及2B以及散熱塊2C上。焊料凸塊34A、34B及34C分別與位於作用層24A之表面處之接觸襯墊25A、25B及25C進行電接觸且自其向下延伸。
SOI晶粒21A，焊料凸塊34A、34B及34C，散熱塊2C以及引線2A及2B之部分圍封於模製化合物5中。散熱塊2C具有與模製化合物5之一底部表面29共面且由底部表面29環繞之一經曝露表面28。散熱塊2C之底部表面28與PCB 6接觸。
如圖3A中所展示，存在產生於作用層24A中之熱可藉由其傳導至PCB 6之三個熱路徑：第一路徑包含接觸襯墊25A、焊料凸塊34A及引線2A，第二路徑包含接觸襯墊25B、焊料凸塊34B及引線2B，且第三路徑包含接觸襯墊 25C、焊料凸塊34C及散熱塊2C。此等熱路徑中之每一者亦可用作連接SOI晶粒中之電路與PCB 6之一電路徑。
為促進透過散熱塊2C之熱轉移，穿過一水平剖面截取之散熱塊2C之面積實質上大於(例如，三至五倍或更大)分別穿過與引線2A或2B之壁垂直之一剖面截取之引線2A或2B之面積。
圖3B圖解說明安裝於一雙邊扁平無引線(DFN)封裝60中之SOI晶粒21A。封裝60類似於圖2B中所展示之封裝40，惟封裝60亦含有一經曝露晶粒襯墊或散熱塊12C除外。在封裝60中，SOI晶粒21A分別藉助焊料凸塊44A、44B及44C以BOL樣式安裝於引線12A及12B以及散熱塊12C上。焊料凸塊44A、44B及44C分別與位於作用層24A之表面處之接觸襯墊25A、25B及25C進行電接觸且自其向下延伸。
SOI晶粒21A，焊料凸塊44A、44B及44C，引線12A及12B以及散熱塊12C圍封於模製化合物15中。引線12A及12B具有與模製化合物15之一底部表面39共面之底部表面12AB及12BB以及與模製化合物15之橫向表面15A及15C共面之橫向表面12AL及12BL。引線12A及12B之底部表面12AB及12BB以及散熱塊12C之底部表面38安裝至PCB 6。
如圖3B中所展示，存在產生於作用層24A中之熱可藉由其傳導至PCB 6之三個熱路徑：第一路徑包含接觸襯墊25A、焊料凸塊44A及引線12A，第二路徑包含接觸襯墊25B、焊料凸塊44B及引線12B，且第三路徑包含接觸襯墊25C、焊料凸塊44C及散熱塊12C。此等熱路徑中之每一者 亦可用作連接SOI晶粒21A中之電路與PCB 6之一電路徑。
為促進透過散熱塊12C之熱轉移，穿過一水平剖面截取之散熱塊12C之面積實質上大於(例如，五倍或更大)分別穿過與引線12A或12B之壁垂直之一剖面截取之引線12A或12B之面積。
在某些實施例中，將SOI晶粒之作用層劃分成「熱島」，以使得一個熱島中之裝置與由另一熱島中之裝置產生之熱絕緣。圖4係圖3B之DFN封裝60之一詳細剖面圖，其展示作用層24A由絕緣溝渠72A、72B、72C及72D刺穿，從而形成熱島71A、71D及71E。溝渠72A、72B、72C及72D通常填充有一絕緣電介質，諸如氧化矽、氮化矽、具有一經沈積玻璃之熱生長二氧化矽或者含有或環繞一經沈積多晶矽層之熱生長二氧化矽。
圖5係圖3B之封裝中之SOI晶粒21A之一平面圖。指示了在其處截取圖4之剖面4-4。如所展示，溝渠72A、72B、72C及72D中之每一者形成為環繞一熱島之一閉合圖之形狀，亦即，溝渠72C環繞熱島71D，溝渠72D環繞熱島71E，且雙重溝渠72A與72B環繞熱島71A。熱島71D含有一MOSFET M1，熱島71A含有MOSFET M2及MOSFET M3，且熱島71E含有一MOSFET M4。亦展示了未由溝渠72A、72B、72C及72D中之一者環繞之一島間區71C。
一起觀察圖4及圖5，可看出熱島71D透過接觸襯墊25A連接至包含焊料凸塊44A及引線12A之一熱路徑，熱島71E透過接觸襯墊25B連接至包含焊料凸塊44B及引線12B之一 熱路徑，且熱島71A透過接觸襯墊25C連接至包含焊料凸塊44C及散熱塊12C之一熱路徑。如圖5中所展示，熱島71A亦經由在圖4之剖面外側之焊料凸塊44D、44E及44K連接至散熱塊。
溝渠72A、72B、72C及72D可藉由習用光微影及蝕刻製程形成於作用層24A中。舉例而言，一溝渠遮罩可形成且圖案化於作用層24A之經曝露表面上，其中開口在溝渠將位於其中之區上方。可使用一反應離子蝕刻(舉例而言，使用溴化氫(HBr)或六氟化硫(SF6)或類似氣體)透過溝渠遮罩中之開口蝕刻作用層24A向下到達絕緣層23A以形成溝渠。然後將該等溝渠熱氧化且然後可藉由化學汽相沈積用一絕緣材料(諸如二氧化矽)或一半絕緣材料(諸如未經摻雜多晶矽)填充該等溝渠。如此項技術中已知，其他材料及製程可用於填充溝渠。
上文說明意欲係圖解說明性而非限制性。熟習此項技術者將明瞭本發明之諸多替代實施例。僅在以下申請專利範圍中定義本發明之寬廣原理。
1‧‧‧習用小型電晶體狀半導體封裝/封裝/先前技術封裝
2A‧‧‧引線/「鷗翼」引線/「鷗翼」形引線/鷗翼形引線
2AM‧‧‧安裝表面
2B‧‧‧引線/「鷗翼」引線/「鷗翼」形引線/鷗翼形引線
2BM‧‧‧安裝表面
2C‧‧‧散熱塊
3‧‧‧絕緣物上矽晶粒
3A‧‧‧作用層
3H‧‧‧處置層
3I‧‧‧絕緣層
4A‧‧‧接合線
4B‧‧‧接合線
5‧‧‧模製化合物
6‧‧‧印刷電路板
11‧‧‧習用雙邊扁平無引線半導體封裝/封裝/先前技術封裝
12A‧‧‧引線
12AB‧‧‧底部表面
12AL‧‧‧橫向表面
12B‧‧‧散熱塊/引線
12BB‧‧‧底部表面
12BL‧‧‧橫向表面
12C‧‧‧引線/散熱塊
13‧‧‧絕緣物上矽晶粒
13A‧‧‧作用層
13H‧‧‧處置層
13I‧‧‧絕緣層
14A‧‧‧接合線
14B‧‧‧接合線
15‧‧‧模製化合物
15A‧‧‧橫向表面
15B‧‧‧底部表面
15C‧‧‧橫向表面
16‧‧‧印刷電路板
21‧‧‧絕緣物上矽晶粒
21A‧‧‧絕緣物上矽晶粒
22‧‧‧處置層
22A‧‧‧處置層
23‧‧‧絕緣層
23A‧‧‧絕緣層
24‧‧‧作用層
24A‧‧‧作用層
25A‧‧‧接觸襯墊
25B‧‧‧接觸襯墊
25C‧‧‧接觸襯墊
28‧‧‧經曝露表面/底部表面
29‧‧‧底部表面
30‧‧‧經模製小型電晶體狀封裝/封裝
34A‧‧‧焊料凸塊
34B‧‧‧焊料凸塊
34C‧‧‧焊料凸塊
38‧‧‧底部表面
39‧‧‧底部表面
40‧‧‧雙邊扁平無引線封裝/封裝
44A‧‧‧焊料凸塊
44B‧‧‧焊料凸塊
44C‧‧‧焊料凸塊
44D‧‧‧焊料凸塊
44E‧‧‧焊料凸塊
44K‧‧‧焊料凸塊
50‧‧‧經模製小型電晶體狀封裝/封裝
60‧‧‧雙邊扁平無引線封裝/封裝
71A‧‧‧熱島
71C‧‧‧島間區
71D‧‧‧熱島
71E‧‧‧熱島
72A‧‧‧絕緣溝渠/溝渠
72B‧‧‧絕緣溝渠/溝渠
72C‧‧‧絕緣溝渠/溝渠
72D‧‧‧絕緣溝渠/溝渠
M1‧‧‧金屬氧化物半導體場效電晶體
M2‧‧‧金屬氧化物半導體場效電晶體
M3‧‧‧金屬氧化物半導體場效電晶體
M4‧‧‧金屬氧化物半導體場效電晶體
圖1A展示含有一絕緣物上矽(SOI)晶粒之一習用SOT狀封裝之一剖面圖。
圖1B展示含有一SOI晶粒之一習用DFN封裝之一剖面圖。
圖2A展示不具有一散熱塊之含有一引線架上凸塊(BOL)安裝式SOI晶粒之經模製SOT狀半導體封裝之一剖面圖。
圖2B展示不具有一散熱塊之含有BOL安裝式SOI晶粒之一雙邊扁平無引線(DFN)半導體封裝之一剖面圖。
圖3A展示具有一經曝露散熱塊之含有一BOL安裝式SOI晶粒之經模製SOT狀半導體封裝之一剖面圖。
圖3B展示具有一經曝露散熱塊之含有一BOL安裝式SOI晶粒之一雙邊扁平無引線(DFN)半導體封裝之一剖面圖。
圖4係圖3B中所展示之DFN封裝之一更詳細剖面圖。
圖5係圖3B之封裝中之SOI晶粒之一平面圖，其展示由溝渠隔離之熱島及自每一熱島延伸之一或多個熱通孔。
6‧‧‧印刷電路板
12A‧‧‧引線
12AB‧‧‧底部表面
12AL‧‧‧橫向表面
12B‧‧‧散熱塊/引線
12BB‧‧‧底部表面
12BL‧‧‧橫向表面
12C‧‧‧引線/散熱塊
15‧‧‧模製化合物
15A‧‧‧橫向表面
15C‧‧‧橫向表面
21A‧‧‧絕緣物上矽晶粒
22A‧‧‧處置層
23A‧‧‧絕緣層
24A‧‧‧作用層
25A‧‧‧接觸襯墊
25B‧‧‧接觸襯墊
25C‧‧‧接觸襯墊
38‧‧‧底部表面
39‧‧‧底部表面
44A‧‧‧焊料凸塊
44B‧‧‧焊料凸塊
44C‧‧‧焊料凸塊
60‧‧‧雙邊扁平無引線封裝/封裝

Claims (11)

  1. 一種半導體封裝，其包括：一引線；一絕緣物上矽(SOI)晶粒，該SOI晶粒包含夾在一處置層與一作用層之間的一絕緣層，該處置層具有與該絕緣層接觸之一第一表面及與該第一表面相對之一第二表面，該SOI晶粒在該封裝中經定向使得該作用層面向該引線；及一金屬凸塊，其連接該作用層之一表面處之一接觸襯墊與該引線，該接觸襯墊係形成於該作用層中之一熱島中，該熱島由在該作用層中之至少一溝渠所定義，該至少一溝渠在該作用層之該表面與該絕緣層之間延伸且橫向地封入該作用層中，該至少一溝渠係以一介電材料填充，該SOI晶粒、該金屬凸塊及該引線之至少一部分圍封於一模製化合物中，該模製化合物完全覆蓋該處置層之該第二表面。
  2. 如請求項1之半導體封裝，其中該熱島由一雙重溝渠環繞。
  3. 如請求項1之半導體封裝，其中該熱島含有至少一個半導體裝置。
  4. 如請求項1之半導體封裝，其中該引線自該模製化合物之一外側表面突出。
  5. 如請求項4之半導體封裝，其進一步包括一散熱塊及一第二金屬凸塊，該第二金屬凸塊連接該作用層之該表面 處之一第二接觸襯墊與該散熱塊，該散熱塊具有與該模製化合物之一底部表面共面且由該底部表面環繞之一經曝露表面。
  6. 如請求項5之半導體封裝，其中該散熱塊之一水平剖面面積比在與該引線之一壁垂直之一剖面處截取之該引線之一面積大至少五倍。
  7. 如請求項1之半導體封裝，其中該半導體封裝包括一DFN型封裝，該引線具有與該模製化合物之一外側表面共面之至少一個表面。
  8. 如請求項7之半導體封裝，其進一步包括一散熱塊及一第二金屬凸塊，該第二金屬凸塊連接該作用層之該表面處之一第二接觸襯墊與該散熱塊，該散熱塊具有與該模製化合物之一底部表面共面且由該底部表面環繞之一經曝露表面。
  9. 如請求項8之半導體封裝，其中該散熱塊之一水平剖面面積比在與該引線之一壁垂直之一剖面處截取之該引線之一面積大至少五倍。
  10. 如請求項8之半導體封裝，其中該第二接觸襯墊形成於該作用層中之一第二熱島中，該第二熱島由在該作用層之該表面與氧化物層之間延伸之至少一個第二溝渠所定義，該至少一個第二溝渠填充有該介電材料。
  11. 如請求項10之半導體封裝，其中該熱島含有至少一個半導體裝置。
TW101129758A 2011-08-16 2012-08-16 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻 TWI455256B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/210,592 US8502362B2 (en) 2011-08-16 2011-08-16 Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance

Publications (2)

Publication Number Publication Date
TW201318115A TW201318115A (zh) 2013-05-01
TWI455256B true TWI455256B (zh) 2014-10-01

Family

ID=47712074

Family Applications (2)

Application Number Title Priority Date Filing Date
TW103129755A TWI497654B (zh) 2011-08-16 2012-08-16 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻
TW101129758A TWI455256B (zh) 2011-08-16 2012-08-16 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW103129755A TWI497654B (zh) 2011-08-16 2012-08-16 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻

Country Status (6)

Country Link
US (2) US8502362B2 (zh)
KR (1) KR102012989B1 (zh)
CN (1) CN103890904B (zh)
HK (1) HK1194204A1 (zh)
TW (2) TWI497654B (zh)
WO (1) WO2013025575A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8502362B2 (en) 2011-08-16 2013-08-06 Advanced Analogic Technologies, Incorporated Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance
CN102484097B (zh) * 2009-07-15 2016-05-25 斯兰纳半导体美国股份有限公司 具有背侧支撑层的绝缘体上半导体
TWI515878B (zh) 2009-07-15 2016-01-01 西拉娜半導體美國股份有限公司 絕緣體上半導體結構、自絕緣體上半導體主動元件之通道去除無用積聚多數型載子之方法、及製造積體電路之方法
US8921168B2 (en) 2009-07-15 2014-12-30 Silanna Semiconductor U.S.A., Inc. Thin integrated circuit chip-on-board assembly and method of making
US9390974B2 (en) 2012-12-21 2016-07-12 Qualcomm Incorporated Back-to-back stacked integrated circuit assembly and method of making
US9466719B2 (en) 2009-07-15 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator with back side strain topology
WO2011008893A1 (en) 2009-07-15 2011-01-20 Io Semiconductor Semiconductor-on-insulator with backside heat dissipation
US9496227B2 (en) 2009-07-15 2016-11-15 Qualcomm Incorporated Semiconductor-on-insulator with back side support layer
JP2015177080A (ja) * 2014-03-15 2015-10-05 新日本無線株式会社 リード内蔵型回路パッケージ及びその製造方法
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features
US9564409B2 (en) * 2015-01-27 2017-02-07 Semiconductor Components Industries, Llc Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
US10163812B2 (en) 2016-10-19 2018-12-25 Infineon Technologies Ag Device having substrate with conductive pillars
TWI770880B (zh) * 2020-12-04 2022-07-11 立錡科技股份有限公司 晶片封裝方法以及晶片封裝單元
US11973010B2 (en) 2020-12-04 2024-04-30 Richtek Technology Corporation Chip packaging method and chip package unit
CN112838011B (zh) * 2021-04-12 2021-08-24 浙江集迈科微电子有限公司 散热芯片及其制作方法
US20230059142A1 (en) * 2021-08-17 2023-02-23 Texas Instruments Incorporated Flip chip packaged devices with thermal interposer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070105277A1 (en) * 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US20080242003A1 (en) * 2007-03-26 2008-10-02 National Semiconductor Corporation Integrated circuit devices with integral heat sinks
US7932132B2 (en) * 2008-03-07 2011-04-26 Denso Corporation Semiconductor device and method of manufacturing the same
US20110141696A1 (en) * 2009-12-15 2011-06-16 Intersil Americas Inc. Thermal matching in semiconductor devices using heat distribution structures

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145364A (ja) * 1997-11-12 1999-05-28 Denso Corp 樹脂封止型半導体装置及びその製造方法
JP4549491B2 (ja) * 2000-03-13 2010-09-22 大日本印刷株式会社 樹脂封止型半導体装置
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
US6914332B2 (en) * 2002-01-25 2005-07-05 Texas Instruments Incorporated Flip-chip without bumps and polymer for board assembly
SG111935A1 (en) * 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US6750082B2 (en) * 2002-09-13 2004-06-15 Advanpack Solutions Pte. Ltd. Method of assembling a package with an exposed die backside with and without a heatsink for flip-chip
US9530857B2 (en) * 2003-06-20 2016-12-27 Tessera Advanced Technologies, Inc. Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect
KR100631403B1 (ko) * 2004-09-23 2006-10-09 삼성전자주식회사 방열판을 장착한 반도체 패키지 및 그 제조 방법
US20060191351A1 (en) * 2005-02-25 2006-08-31 Meehan Peter G Sealed capacitive sensor
US7967184B2 (en) 2005-11-16 2011-06-28 Sandisk Corporation Padless substrate for surface mounted components
JP2007188916A (ja) * 2006-01-11 2007-07-26 Renesas Technology Corp 半導体装置
US20070216026A1 (en) 2006-03-20 2007-09-20 Adams Zhu Aluminum bump bonding for fine aluminum wire
US8502362B2 (en) 2011-08-16 2013-08-06 Advanced Analogic Technologies, Incorporated Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance
JP4957158B2 (ja) * 2006-10-02 2012-06-20 株式会社デンソー 電子装置の製造方法
RU2402107C2 (ru) 2006-10-12 2010-10-20 Дмитрий Евгеньевич Миловзоров Устройство памяти на тонкопленочной структуре кремния на стекле
JP5522917B2 (ja) 2007-10-10 2014-06-18 株式会社半導体エネルギー研究所 Ｓｏｉ基板の製造方法
JP4894910B2 (ja) * 2009-01-15 2012-03-14 株式会社デンソー 半導体装置の製造方法及び半導体装置並びにその半導体装置を内蔵する多層基板
CN102157461A (zh) 2010-02-11 2011-08-17 飞思卡尔半导体公司 制作半导体封装的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070105277A1 (en) * 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US20080242003A1 (en) * 2007-03-26 2008-10-02 National Semiconductor Corporation Integrated circuit devices with integral heat sinks
US7932132B2 (en) * 2008-03-07 2011-04-26 Denso Corporation Semiconductor device and method of manufacturing the same
US20110141696A1 (en) * 2009-12-15 2011-06-16 Intersil Americas Inc. Thermal matching in semiconductor devices using heat distribution structures

Also Published As

Publication number Publication date
US8916965B2 (en) 2014-12-23
TWI497654B (zh) 2015-08-21
US8502362B2 (en) 2013-08-06
US20140035133A1 (en) 2014-02-06
HK1194204A1 (zh) 2014-10-10
WO2013025575A1 (en) 2013-02-21
TW201503297A (zh) 2015-01-16
KR102012989B1 (ko) 2019-08-21
CN103890904A (zh) 2014-06-25
US20130043595A1 (en) 2013-02-21
KR20140054049A (ko) 2014-05-08
TW201318115A (zh) 2013-05-01
CN103890904B (zh) 2016-09-28

Similar Documents

Publication Publication Date Title
TWI455256B (zh) 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻
JP5149178B2 (ja) 熱放散が高められたパッケージ化集積回路
JP4698225B2 (ja) ドレインクリップを備えた半導体ダイパッケージ
TWI395277B (zh) 晶圓水準的晶片級封裝
TWI485817B (zh) 微電子封裝及其散熱方法
US9305859B2 (en) Integrated circuit die with low thermal resistance
US11837528B2 (en) Method of manufacturing a semiconductor device having a bond wire or clip bonded to a bonding pad
JP3905580B2 (ja) 冷却改善用の熱伝達構造を有する高密度ｃｍｏｓ集積回路
WO2007124410A2 (en) Thermally enhanced bga package with ground ring
CN103681609A (zh) 集成电路、芯片封装以及用于制造集成电路的方法
CN114823597A (zh) 半导体器件封装和制造半导体器件封装的方法
US8536701B2 (en) Electronic device packaging structure
JP2022523671A (ja) 露出したクリップを備える電子デバイスフリップチップパッケージ
US20140264805A1 (en) Semiconductor Package And Fabrication Method Thereof
US20220384286A1 (en) Chip package structure with heat conductive layer
TW202226485A (zh) 半導體裝置
JP6984753B2 (ja) 半導体装置
US8729632B2 (en) Semiconductor structure with low resistance of substrate and low power consumption
TWI489601B (zh) 電子元件封裝結構
KR20220064662A (ko) 반도체 소자 패키지 및 그 제조방법
KR100317128B1 (ko) 전계 효과 트랜지스터 및 그 제조 방법