CN102157461A - 制作半导体封装的方法 - Google Patents

制作半导体封装的方法 Download PDF

Info

Publication number
CN102157461A
CN102157461A CN2010101136903A CN201010113690A CN102157461A CN 102157461 A CN102157461 A CN 102157461A CN 2010101136903 A CN2010101136903 A CN 2010101136903A CN 201010113690 A CN201010113690 A CN 201010113690A CN 102157461 A CN102157461 A CN 102157461A
Authority
CN
China
Prior art keywords
encapsulating material
temperature
weld pad
encapsulation
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010101136903A
Other languages
English (en)
Inventor
田斌
许南
姚晋钟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to CN2010101136903A priority Critical patent/CN102157461A/zh
Priority to US13/004,029 priority patent/US8216886B2/en
Publication of CN102157461A publication Critical patent/CN102157461A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种制作半导体封装的方法,涉及装配半导体封装的方法,所述方法包括在对包封材料进行模制后固化之后的快速冷却步骤。该快速冷却步骤包括对该封装吹送大约两分钟冷冻压缩空气。该快速冷却步骤不需要同时对封装施加任何夹紧压力。该快速冷却步骤在最长不到5分钟的时间内将包封材料的温度从固化温度降低至冷却温度。与在夹紧压力下用环境空气对封装进行冷却相比,通过使用快速冷却,因CTE失配所致的封装扭曲可以得以防止。

Description

制作半导体封装的方法
技术领域
本发明涉及用于装配半导体封装的方法以及由该方法所装配的半导体封装。特别地,本发明涉及包封作为该封装的组件之一的半导体单元片(semiconductor die)的包封材料的固化以及快速冷却。
背景技术
典型的半导体封装以被安装到引脚框架或可去除的支持衬底(例如,可去除的条带(tape))的半导体单元片来形成,其中该支持衬底支持着外部连接焊垫及可选的标记板(flag)的布局。当半导体封装由安装到支持衬底的半导体单元片形成时,该半导体封装通常称作扁平无引脚封装,例如方形扁平无引脚(QFN)封装或双排扁平无引脚(DFN)封装。
扁平无引脚半导体封装的制造包括用包封材料(encapsulationmaterial)来包封半导体单元片和外部连接焊垫。包装材料典型地是被固化以及然后从固化温度逐渐冷却到室内或环境温度的模制化合物(molding compound)。这两个步骤被称为固化(cure)和模制后固化(post-mold cure)。在模制后固化过程中,封装被用夹持装置保持于受压状态并使用环境空气逐渐进行冷却。但是,已经发现,由于半导体单元片、衬底及模制化合物的热膨胀系数(CTE)的差异,半导体封装在这样的逐渐冷却的过程中会变形。更特别地,这些CTE失配能够引起包封材料的上表面变得轻微拱曲(凸的)以及包封材料的对应的基表面也变得轻微拱曲(凹的)。不幸的是,轻微拱曲的上表面是不希望的,因为理想的上表面应该是平坦的以使得抽吸式机械手臂能够拾起封装以进行后固化处理。此外,轻微拱曲的基表面能够引起外部连接焊垫成为非平面的,导致外部连接焊垫与电路板的安装焊垫的质量低劣的焊接连接。因而,能够装配在模制后固化过程中没有被扭曲的半导体封装将是有利的。
附图说明
本发明,连同其目的及优点,可以参考关于优选的实施方案的下列描述以及附图得到最佳的理解,在附图中:
图1是常规的扁平无引脚半导体封装的截面侧视图;
图2是根据本发明的实施方案的扁平无引脚半导体封装的截面侧视图;
图3是已去除支持衬底的图2的扁平无引脚半导体封装的底部视图;
图4是根据本发明的另一种实施方案的扁平无引脚半导体封装的截面侧视图;
图5是已去除支持衬底的图4的扁平无引脚半导体封装的底部视图;
图6示出了一种制造根据本发明的实施方案的图2或图4的扁平无引脚半导体包装的方法;
图7示出了一种根据本发明的一种实施方案实行模制后固化的步骤的方法;以及
图8示出了一种根据本发明的另一种实施方案实行模制后固化的步骤的方法。
具体实施方式
以下结合附图阐述的详细描述意欲作为关于本发明当前优选的实施方案的描述,而并非意指表示可以实施本发明的唯一形式。应当理解,相同或相当的功能可以由意指包含于本发明的精神和范围之内的不同实施方案来实现。在附图中,类似的参考标记始终用来指示类似的元素。而且,词语“包含”、“含有”、或其任何不同形式意指涵盖非排他性的包括,使得包含一列表元素或步骤的系统、电路、装置组件以及方法步骤不仅包括那些列出的元素而且还可以包括没有专门列出或者该系统、电路、装置组件或步骤固有的其他元素或步骤。在没有更多约束的情况下,由“包含...一个”所说明的元素或步骤不排除存在包含该元素或步骤的另外的相同元素或步骤。
本发明在一种实施方案中提供了一种用于制造扁平无引脚半导体封装的方法。该方法包括将半导体单元片的基表面安装到支持衬底以及然后将在单元片的上表面上的单元片电连接焊垫与被安装到支持衬底上的各自外部连接焊垫进行电连接。然后,该方法用包封材料对半导体单元片和外部连接焊垫进行包封以形成半导体封装。所述包封材料与支持衬底将外部连接焊垫夹在中间并且在固化步骤中于固化温度下对包封材料进行固化。然后,在冷却步骤中,使包封材料从固化温度快速冷却到小于50摄氏度的冷却温度。该冷却由被引导到包封材料之上的流体流进行辅助。快速冷却在最长不到5分钟的时间内将包封材料的温度从固化温度降低到冷却温度。
参考图1示出了现有技术的扁平无引脚半导体封装100的截面侧视图。扁平无引脚半导体封装100具有都被安装到支持衬底140的半导体单元片110和外部连接焊垫120。半导体单元片110的基表面130典型地通过标记板150被安装到支持衬底140。此外,在半导体单元片110的上表面上的单元片电连接焊垫160通过接合线丝170与其各自的外部连接焊垫120进行电连接。包封材料180对半导体单元片110和外部连接焊垫120进行包封使得包封材料180和支持衬底140将外部连接焊垫120夹在中间。包封材料180典型地是在大约175摄氏度被固化并且然后逐渐冷却到室内或环境温度的模制化合物。支持衬底140一般是柔性单面粘性带,以及在将包封材料180固化并逐渐冷却到室内温度之后,半导体封装100会轻微变形。半导体封装100的变形是由于半导体单元片110与包封材料180的膨胀系数的差异。这种变形可以引起包封材料180的上表面185轻微拱曲(凸的)以及引起包封材料180的相应的基表面190也轻微拱曲(凹的)。如之前所述,轻微拱曲的上表面185是不希望的,因为上表面理想地应当是平坦的以使得抽吸式机械手臂能够拾起封装以进行后固化处理。另外,轻微拱曲的基表面190能够引起外部连接焊垫120成为非平面的,由此导致外部连接焊垫120与电路板的安装焊垫的质量低劣的焊接连接。
参考图2示出了根据本发明的优选实施方案的扁平无引脚半导体封装200的截面侧视图。扁平无引脚半导体封装200具有都被安装到支持衬底240的半导体单元片210和外部连接焊垫220,该支持衬底240典型地是可去除的条带,例如柔性单面粘性带。半导体单元片210的基表面230通过标记板250被安装到支持衬底240。此外,在半导体单元片210上表面上的单元片电连接焊垫260通过接合线丝270与其各自的外部连接焊垫220进行电连接。包封材料280对半导体单元片210和外部连接焊垫220进行包封使得包封材料280和支持衬底240将外部连接焊垫220夹在中间。包封材料280典型地是根据本发明以下所描述的方法在大约175摄氏度被固化以及然后快速冷却到室内或环境温度的模制化合物。如所示,包封材料280的上表面285基本上是平坦的使得抽吸机械手臂能够拾起封装以进行后固化处理。另外,基表面290在平面P上能够基本上是平面的,由此给外部连接焊垫220与电路板的安装焊垫的焊接连接提供安装平面。
在图3中示出了已去除支持衬底240的扁平无引脚半导体封装200的底部视图。如所示出的,外部连接焊垫220与包封材料280的全部四条边310相关,因此该扁平无引脚半导体封装200是方形扁平无引脚半导体封装。但是,对本领域技术人员来说显而易见的是外部连接焊垫220可以不与边310中的每一边都相关。
参考图4示出了根据本发明的另一种优选实施方案的扁平无引脚半导体封装400的截面侧视图。扁平无引脚半导体封装400具有都被安装到支持衬底440的半导体单元片410和外部连接焊垫420,其中该支持衬底440典型地是可去除的条带,例如柔性单面粘性带。半导体单元片410的基表面430通过外部电连接焊垫420中的至少一些安装到支持衬底440。在半导体单元片410的上表面上的单元片连接焊垫460通过接合线丝470与其各自的外部连接焊垫420进行电连接。包封材料480对半导体单元片410和外部连接焊垫420进行包封使得包封材料480和支持衬底440将外部连接焊垫420夹在中间。此外,包封材料480典型地是根据本发明以下所描述的方法在大约175摄氏度被固化以及然后快速冷却到室内或环境温度的模制化合物。如所示,包封材料480的上表面485基本上是平坦的使得抽吸式机械手臂能够拾起封装以进行后固化处理。另外,基表面490在平面Q上能够基本上是平面的,由此给外部连接焊垫420与电路板的安装焊垫的焊接连接提供安装平面。
在图5中示出了已去除支持衬底440的扁平无引脚半导体封装400的底部视图。如所示出的,外部连接焊垫420与包封材料480的全部四条边510相关,因此该扁平无引脚半导体封装400是方形扁平无引脚半导体封装。此外,对本领域技术人员来说显而易见的是外部连接焊垫220可以不与边510中的每一边都相关。
参考图6示出了一种用于制造根据本发明的优选实施方案的扁平无引脚半导体封装200或400的方法600。该方法600,在安装步骤610中,将半导体单元片210、410的基表面230、430安装到支持衬底240、440。在电连接步骤620中使在半导体单元片210、410的上表面上的单元片电连接焊垫260、460与其各自的外部连接焊垫220、420进行电连接。然后在包封步骤630中用包封材料280、480对半导体单元片210、410和外部连接焊垫220、420进行包封以形成半导体封装200、400。更特别地,包封材料280、480和支持衬底240、440将外部连接焊垫220、420夹在中间。然后,在固化步骤640中,方法600在固化温度TC下对包封材料280、480进行固化。该固化温度TC通常是175摄氏度(±10%),并且该固化一般进行5小时(±10%)。
在固化之后,方法600在冷却步骤650中将包封材料从固化温度TC冷却到冷却温度TCD,其中该冷却温度TCD不超过50摄氏度,以及理想地是小于30摄氏度。该冷却的特征在于至少部分地由被引导至包封材料280、480之上的流体流辅助以便由此使包封材料280、480的温度在最长不到5分钟的期间内以及适宜地在3分钟内(小于3分钟)从固化温度TC降低至冷却温度TCD。更特别地,流体流是由一个或多个风扇所提供的流动速率至少为1米/秒的空气流。在一种实施方案中,空气流的温度为环境温度,或者在另一可选实施方案中空气流被冷却到10摄氏度以下的空气流温度。
在冷却后,在去除步骤660中,执行从半导体封装200、400去除支持衬底240、440(切单)。该去除通过将支持衬底240、440(可去除条带)从半导体封装200、400剥离来实现,由此留下露出用于安装到电路板的安装焊垫的外部连接焊垫的表面。
有利地,本发明的冷却步骤650缓解了或至少降低了半导体封装200、400的变形效应,该变性效应起因于半导体单元片210、410和包封材料280、480的膨胀系数的差异。因此,如上所述,本发明提供了基本上平坦的包封材料280、480的上表面285、485使得抽吸式机械手臂能够拾起封装以进行后固化处理。另外,基表面290能够基本上是平面的由此给外部连接焊垫220或420与电路板的安装焊垫的焊接连接提供安装表面。
参考图7示出一种用于根据本发明的一种实施方案实现快速的模制后固化的方法。图7显示了具有多个用于夹持扁平无引脚半导体封装200或400的插槽的杂志架型夹持器700。为了跨越扁平无引脚半导体封装200/400吹送流体以实现封装200/400的快速冷却,吹风机710位于接近夹持器700的位置。如上文所讨论的,在一种实施方案中,吹风机710将压缩、冷冻的空气吹送到封装200/400之上使得封装200/400在5分钟或更短的时间内从大约175℃的模制后固化温度冷却到大约25℃。
图8示出了一种用于根据本发明的另一种实施方案实现快速模制后固化的方法。图8显示了其上安装有多个扁平无引脚半导体封装200或400的传动带(transmission trip)或导轨800。导轨800沿箭头方向移动在一个或多个吹风机或风扇810下方的封装200/400。吹风机810吹送流体跨越扁平无引脚半导体封装200/400以实现封装200/400的快速冷却。再次,如上文所讨论的,吹风机810将压缩、冷冻的空气吹送到封装200/400之上使得封装200/400在5分钟或更短的时间内从大约175℃的模制后固化温度冷却到大约25℃。
关于本发明的优选实施方案的描述已经就说明及描述的目的进行了提供,但是并不意欲是穷举的或者将本发明限定于所公开的形式。本领域技术人员应当了解,在没有脱离其广泛的发明构思的情况下能够对以上所描述的实施方案进行改变。因此,应当理解,本发明并不限定于所公开的具体实施方案,而是涵盖如所附权利要求书定义的本发明的精神及范围之内的修改。

Claims (10)

1.一种用于装配扁平无引脚半导体封装的方法,包括:
将半导体单元片的基表面安装到支持衬底;
使在单元片的上表面上的单元片电连接焊垫与被安装到支持衬底的各个外部连接焊垫电连接;
用包封材料对所述半导体单元片和外部连接焊垫进行包封以形成半导体封装,其中所述包封材料和支持衬底将所述外部连接焊垫夹在它们之间;
在固化温度下固化所述包封材料;以及
将所述包封材料从固化温度快速冷却到不超过50摄氏度的冷却温度,所述快速冷却至少部分地由被引导至包封材料之上的流体流辅助以便由此使包封材料的温度在小于5分钟的最大冷却周期内从固化温度降低至所述冷却温度。
2.根据权利要求1的方法,其中所述流体流是空气流。
3.根据权利要求2的方法,其中所述空气流的流动速率至少为1米/秒。
4.根据权利要求2的方法,其中所述空气流至少由一个风扇来提供。
5.根据权利要求2的方法,其中被引导至所述包封材料之上的空气的温度为环境温度。
6.根据权利要求2的方法,其中被引导至所述包封材料之上的空气的温度是25摄氏度或更低。
7.根据权利要求1的方法,其中所述最大冷却周期小于3分钟。
8.根据权利要求1的方法,其中所述固化温度为175摄氏度±10%。
9.根据权利要求8的方法,其中所述固化被执行5小时±10%。
10.一种根据权利要求1的方法装配的封装半导体器件。
CN2010101136903A 2010-02-11 2010-02-11 制作半导体封装的方法 Pending CN102157461A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2010101136903A CN102157461A (zh) 2010-02-11 2010-02-11 制作半导体封装的方法
US13/004,029 US8216886B2 (en) 2010-02-11 2011-01-11 Method for making semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2010101136903A CN102157461A (zh) 2010-02-11 2010-02-11 制作半导体封装的方法

Publications (1)

Publication Number Publication Date
CN102157461A true CN102157461A (zh) 2011-08-17

Family

ID=44353061

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010101136903A Pending CN102157461A (zh) 2010-02-11 2010-02-11 制作半导体封装的方法

Country Status (2)

Country Link
US (1) US8216886B2 (zh)
CN (1) CN102157461A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106711152A (zh) * 2017-01-03 2017-05-24 京东方科技集团股份有限公司 一种显示面板及其封装方法
CN109382959A (zh) * 2017-08-04 2019-02-26 东和株式会社 树脂成形装置及树脂成形品制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8502362B2 (en) 2011-08-16 2013-08-06 Advanced Analogic Technologies, Incorporated Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance
US11791283B2 (en) 2021-04-14 2023-10-17 Nxp Usa, Inc. Semiconductor device packaging warpage control
US20220392777A1 (en) * 2021-06-03 2022-12-08 Nxp Usa, Inc. Semiconductor device packaging warpage control
US11729915B1 (en) * 2022-03-22 2023-08-15 Tactotek Oy Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4657137A (en) * 1981-05-22 1987-04-14 North American Philips Corporation Multi-chip packaging system
US20030096455A1 (en) * 2001-09-26 2003-05-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having tie bars for interconnecting leads
CN1755929A (zh) * 2004-09-28 2006-04-05 飞思卡尔半导体公司 形成半导体封装及其结构的方法
CN101271851A (zh) * 2008-05-08 2008-09-24 日月光半导体制造股份有限公司 降低封装翘曲度的热处理方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5622731A (en) * 1993-09-10 1997-04-22 Fierkens; Richard H. J. Automatic post mold curing apparatus for use in providing encapsulated semiconductor chips and method therefor
US6537848B2 (en) * 2001-05-30 2003-03-25 St. Assembly Test Services Ltd. Super thin/super thermal ball grid array package
TW554501B (en) * 2002-08-14 2003-09-21 Siliconware Precision Industries Co Ltd Substrate for semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4657137A (en) * 1981-05-22 1987-04-14 North American Philips Corporation Multi-chip packaging system
US20030096455A1 (en) * 2001-09-26 2003-05-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having tie bars for interconnecting leads
CN1755929A (zh) * 2004-09-28 2006-04-05 飞思卡尔半导体公司 形成半导体封装及其结构的方法
CN101271851A (zh) * 2008-05-08 2008-09-24 日月光半导体制造股份有限公司 降低封装翘曲度的热处理方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106711152A (zh) * 2017-01-03 2017-05-24 京东方科技集团股份有限公司 一种显示面板及其封装方法
CN109382959A (zh) * 2017-08-04 2019-02-26 东和株式会社 树脂成形装置及树脂成形品制造方法
CN109382959B (zh) * 2017-08-04 2021-07-20 东和株式会社 树脂成形装置及树脂成形品制造方法

Also Published As

Publication number Publication date
US8216886B2 (en) 2012-07-10
US20110193237A1 (en) 2011-08-11

Similar Documents

Publication Publication Date Title
CN102157461A (zh) 制作半导体封装的方法
US20090162467A1 (en) Resin Sealing/Molding Apparatus
TWI413195B (zh) 減少模封膠體內氣泡之壓縮模封方法與裝置
US6083775A (en) Method of encapsulating a chip
CN102280390B (zh) 组装具有散热器的半导体器件的方法
US6001672A (en) Method for transfer molding encapsulation of a semiconductor die with attached heat sink
US8749002B2 (en) Structure and method form air cavity packaging
US7604469B2 (en) Degating device
JP3450223B2 (ja) 半導体装置封入用金型、及び、半導体装置封入方法
CN101190556B (zh) 废胶剥除装置
CN104576554B (zh) 一种封装件及其制造方法
JP5499986B2 (ja) 半導体装置の製造方法及び半導体製造装置
JP2001007256A (ja) 半導体集積回路装置および半導体集積回路装置の製造方法
JPH10270627A (ja) 半導体装置の製造方法およびリードフレーム
US8273445B2 (en) Reinforced assembly carrier
CN102148168B (zh) 制造具有改进抬升的半导体封装的方法
KR101416114B1 (ko) 전자부품의 수지성형장치 및 방법
JP4381127B2 (ja) 不要樹脂除去装置及び除去方法
US20230162991A1 (en) Methods of forming packaged semiconductor devices, packaged semiconductor devices, and package molds for forming packaged semiconductor devices
CN116364562A (zh) 芯片封装方法及封装结构
JP2000158488A (ja) 金型クリーニング用のダミー・リードフレーム
JP3061115U (ja) 半導体パッケ―ジの基板
JP3419898B2 (ja) 半導体装置及びその製造方法
JP5991253B2 (ja) 樹脂封止型パワーモジュール及び成形金型
CN116613130A (zh) 引线框架及其制造方法、半导体封装结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C05 Deemed withdrawal (patent law before 1993)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20110817