CN103890904B - 包含绝缘体上硅的半导体封装体 - Google Patents

包含绝缘体上硅的半导体封装体 Download PDF

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CN103890904B
CN103890904B CN201280050797.5A CN201280050797A CN103890904B CN 103890904 B CN103890904 B CN 103890904B CN 201280050797 A CN201280050797 A CN 201280050797A CN 103890904 B CN103890904 B CN 103890904B
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active layer
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R.K.威廉斯
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Advanced Analog Technology Inc
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Abstract

来自绝缘体上硅（SOI）芯片的热传递通过在半导体封装体中以引线框上凸块方式安装芯片而得到改善，连接SOI芯片的有源层到金属引线的焊料或其它金属凸块用于将封装体安装在印刷电路板或其它支撑结构上。

Description

包含绝缘体上硅的半导体封装体
相关申请的交叉引用
本申请涉及2006年5月2日提交的名称为“Bump-on-Leadframe（BOL）Package Technology with Reduced Parasitics”的申请No.11/381,292，通过引用其全文合并于本文。
背景技术
绝缘体上硅半导体芯片可用于希望它在芯片中形成的半导体器件之间提供非常有效的绝缘屏障的应用。绝缘体上硅（SOI）芯片由三层组成：（1）有源层，其中形成半导体器件，（2）绝缘层，以及（3）处理层。绝缘层夹设在有源层和处理层之间。有源层和处理层由硅形成；绝缘层通常由二氧化硅（常常简称为"氧化物"）形成。绝缘层还可由热生长氧化物和沉积玻璃或氧化物的夹层组成。处理层通常是三层中最厚的。因为有缘层和处理层由硅形成，并且因此具有相同的温度膨胀系数，所以芯片是非常热稳定的。此外，因为绝缘层提供很强的绝缘屏障，所以有源层中形成的器件可采用延伸通过有源层的隔离结构非常有效地彼此电绝缘。
图1A示出了包含SOI芯片3的常规SOT-状半导体封装体1的截面图。SOT或"小外形晶体管"是工业标准封装体，用在离散晶体管或低引脚数集成电路的封装体中。SOI芯片3包括有源层3A、绝缘层3I和处理层3H。SOI芯片3通过处理层3H的暴露表面安装到引线2B。有源层3A中的器件（未示出）通过有源层3A的表面上的接触焊盘（未示出）且通过焊线4A和4B电连接到引线2A和2B。"鸥翼"状引线2A和2B从模塑料5突出，引线2A和2B的下表面安装到印刷电路板（PCB）6。
图1B示出了包含SOI芯片13的常规双无引线（DFN）半导体封装体11的截面图。SOI芯片13包括有源层13A、绝缘层131和处理层13H。SOI芯片13通过处理层13H的暴露表面安装到散热块12B。有源层13A中的器件（未示出）通过有源层13A的表面上的接触焊盘（未示出）且通过焊线14A和14B电连接到引线12A和12C。引线12A和12C的外表面与模塑料15的侧表面和底表面共面，即，与图1A中的引线2A和2B不同，引线12A和12C不从模塑料15突出。引线12A和12C的下表面以及散热块12B用于安装封装体11到PCB16。
但是，SOI芯片的良好电绝缘特性产生了热问题，其中有源层中形成的器件产生的热被绝缘层阻挡。例如，在封装体1和11中，SOI芯片3和13的有源层由绝缘层和处理层（焊线通常非常薄且不能传递大量的热）与引线物理隔离和热隔离。用于绝缘层的诸如二氧化硅的材料通常是良好的热绝缘体。结果，有源层中的温度可达到不可接受的高水平，并且可能损坏或者破坏SOI芯片中形成的器件。
因此，为SOI芯片提供半导体封装体以利去除芯片中半导体器件产生的热量是非常有用的。这样的解决方案从电和热两者角度看可使SOI芯片延长其潜在的寿命。
发明内容
根据本发明的半导体封装体，绝缘体上硅（SOI）芯片以引线框上凸块（BOL）或"倒装芯片"方式定向，其有源层面对引线和焊料或其它金属凸块，以在有源层的表面连接接触焊盘与引线。焊料可包括合金、诸如铅-锡（Pb-Sn）或锡-银（Sn-Ag）金属的二元或三元化合物，或者可包括任何软金属，例如金、银或锡。这形成了有源层中产生的热可容易传递到印刷电路板或者其上安装有封装体的其它结构的热通道。
本发明可应用于广泛种类的封装体，包括SOT-状和DFN封装体。
在某些实施例中，SOI芯片的有源层通过绝缘沟槽分成热岛，每个热岛通过一个或多个焊料块连接到引线。
附图说明
通过参考下面的附图将更好地理解本发明，附图不必按比例绘制，且其中相同的部件具有类似的附图标记。
图1A示出了常规的包含绝缘体上硅（SOI）芯片的SOT-状封装体的截面图。
图1B示出了常规的包含SOI芯片的DFN封装体的截面图。
图2A示出了模塑的SOT-状半导体封装体的截面图，其包含引线框上凸块（BOL）安装的SOI芯片，其中没有散热块。
图2B示出了双平面无引线（DFN）半导体封装体的截面图，其包含BOL-安装的SOI芯片，其中没有散热块。
图3A示出了模塑的SOT-状半导体封装体的截面图，其包含BOL-安装的SOI芯片，其中具有暴露的散热块。
图3B示出了双平面无引线（DFN）半导体封装体的截面图，其包含BOL-安装的SOI芯片，其中具有暴露的散热块。
图4是图3B所示DFN封装体的更加详细的截面图。
图5是图3B的封装体中的SOI芯片的平面图，示出了由沟槽隔离的热岛以及从每个热岛延伸的一个或多个热通孔。
具体实施方式
图2A示出了根据本发明的模塑SOT-状封装体30。封装体30包含SOI芯片21，SOI芯片21具有处理层22、绝缘层23和有源层24。SOI芯片21以引线框上凸块（BOL）或"倒装晶片"方式分别通过凸块34A和34B安装在引线2A和2B上。SOI芯片21定向为使有源层24面对引线2A和2B。焊料凸块34A和34B分别与位于有源层24表面的接触焊盘25A和25B电接触且从其向下延伸。焊料凸块34A和34B可由半导体封装体中所用的任何类型的焊料制造，例如，铅-锡（Pb-Sn）或锡-银（Sn-Ag）焊料，或者诸如纯锡（Sn）、纯银（Ag）或金（Au）的软金属。
SOI芯片21、焊料凸块34A和34B以及部分引线2A和2B包封在模塑料5中，模塑料5一般由塑料制造。“鸥翼”状引线2A和2B，通常由诸如铝的金属制造，从模塑料5突出且安装到印刷电路板（PCB）6。
有源层24一般包含多个半导体器件（MOSFETs、双极晶体管、二极管等），其某些可在有源层24中的电路运行时产生大量的热。如图2A所示，存在两个热通道，有源层24中产生的热可通过其传导到PCB6：第一通道包括接触焊盘25A、焊料块34A和引线2A，以及第二通道包括接触焊盘25B、焊料块34B和引线2B。这些热通道的每一个也可用作连接SOI芯片中的电路与PCB6的电通路。
封装体30的传热特性远好于图1A所示的可比现有技术封装体1，因为有两个高导热通道，SOI芯片21中产生的热可通过其传递到PCB6。而且，SOI芯片21中产生的某些热通过辐射和转换从引线2A和2B去除。
制造封装体30的工艺是本领域熟知的。在示例性工艺中，焊料球开始设置在接触焊盘25A和25B上，并且充分加热以使焊料粘附到接触焊盘。焊料球的设置可通过在芯片上的“模板”掩模滴球而设置，从而使球仅落在球要与其连接的焊盘的顶部或者恰在其附近的芯片上。然后，SOI芯片21倒转，并且焊料球分别与引线2A和2B接触，因此其还是引线框的一部分。然后，再一次加热焊料（回流），从而使焊料球形成粘合到接触焊盘25A和引线2A的焊料块34A和粘合到接触焊盘25B和引线2B的焊料块34B。一旦焊料凸块34A和34B粘合到SOI芯片21和引线2A和2B，则组件通过注塑工艺包封在模塑料5中，然后，引线与引线框中的其它引线分开。
图2B示出了安装在双无引线（DFN）封装体40中的SOI芯片21。SOI芯片21分别通过焊料凸块44A和44B以BOL-方式安装在引线12A和12B上。焊料凸块44A和44B分别与接触焊盘25A和25B电接触且从其向下延伸。
SOI芯片21、焊料凸块44A和44B以及引线12A和12B包封在一般由塑料制造的模塑料15中。与封装体30中从模塑料5突出的鸥翼状引线2A和2B不同，引线12A和12B具有与模塑料15的底表面15B共面的底表面12AB和12BB以及与模塑料15的侧表面15A和15C共面的侧表面12AL和12BL。引线12A和12B的底表面12AB和12BB安装到印刷电路板（PCB）6。
如图2B所示，存在两个热通道，有源层24中产生的热可通过其传递到PCB6，第一通道包括接触焊盘25A、焊料块44A和引线12A，以及第二通道包括接触焊盘25B、焊料块44B和引线12B。这些热通道的每一个还可用作连接SOI芯片21中的电路与PCB6的电通道。
封装体40的热传输特性远好于如图1B所示的可比较的现有技术的封装体，因为有两个高导热通道，SOI芯片21产生的热可通过其传递到PCB6。
图3A示出了根据本发明的模塑SOT-状封装体50。封装体50包含SOI芯片21A，具有处理层22A、绝缘层23A和有源层24A，还包含暴露的芯片焊盘或散热块2C。接触焊盘25A、25B和25C设置在有源层24A的暴露的表面处。除了封装体50中模塑料5的底表面29与引线2A和2B的安装表面2AM和2BM共面外，封装体50类似于图2A所示的封装体30。在封装体50中，SOI芯片21A以BOL方式分别通过焊料凸块34A、34B和34C安装在引线2A和2B以及散热块2C上。焊料凸块34A、34B和34C分别与设置在有源层24A表面的接触焊盘25A、25B和25C电接触且从接触焊盘25A、25B和25C向下延伸。
SOI芯片21A、焊料凸块34A、34B和34C、散热块2C以及引线2A和2B的部分包封在模塑料5中。散热块2C具有与模塑料5的底表面29共面且由底表面29围绕的暴露表面。散热块2C的底表面28与PCB6接触。
如图3A所示，存在三个热通道，有源层24A中产生的热可通过其传导到PCB6。第一通道包括接触焊盘25A、焊料块34A和引线2A，第二通道包括接触焊盘25B、焊料块34B和引线2B，并且第三通道包括接触焊盘25C、焊料块34C和散热块2C。这些热通道的每一个还可用作连接SOI芯片中的电路与PCB6的电通路。
为了利于通过散热块2C传热，散热块2C通过水平横截面剖取的面积充分大于（例如，三至五倍或更大）引线2A或2B分别通过垂直于引线2A或2B的壁的截面剖取的面积。
图3B示出了双平面无引线（DFN）封装体60中安装的SOI芯片21A。除了封装体60还包含暴露的芯片焊盘或散热块12C外，封装体60类似于图2B所示的封装体40。在封装体60中，SOI芯片21A以BOL方式分别通过焊料凸块44A、44B和44C安装在引线12A和12B以及散热块12C上。焊料凸块44A、44B和44C分别与位于有源层24A表面的接触焊盘25A、25B和25C电接触且从接触焊盘25A、25B和25C向下延伸。
SOI芯片21A、焊料凸块44A、44B和44C、引线12A和12B以及散热块12C包封在模塑料15中。引线12A和12B的底表面12AB和12BB与模塑料15的底表面39共面，且其侧表面12AL和12BL与模塑料15的侧表面15A和15C共面。引线12A和12B的底表面12AB和12BB以及散热块12C的底表面38安装到PCB6。
如图3B所示，存在三个热通道，有源层24A中产生的热可通过其传递到PCB6。第一通道包括接触焊盘25A、焊料块44A和引线12A，第二通道包括接触焊盘25B、焊料块44B和引线12B，以及第三通道包括接触焊盘25C、焊料块44C和散热块12C。这些热通道的每一个还可用作连接SOI芯片21A中的电路与PCB6的电通路。
为了利于通过散热块12C传热，散热块12C通过水平截面剖取的面积充分大于（例如，为五倍或更大）引线12A或12B分别通过垂直于引线12A或12B的壁的截面剖取的面积。
在某些实施例中，SOI芯片的有源层分成"热岛"，从而一个热岛中的器件与另一个热岛中器件产生的热绝缘。图4是图3B的DFN封装体60的详细剖视图，示出了有源层24A被绝缘沟槽72A、72B、72C和72D穿过，产生热岛71A、71D和71E。沟槽72A、72B、72C和72D一般填充有绝缘介质，例如氧化硅、氮化硅、具有沉积玻璃的热生长二氧化硅或包含或围绕沉积的多晶硅层的热生长二氧化硅。
图5是图3B的封装体中SOI芯片21A的平面图。示出了其上剖取图4的截面4-4。如所示，沟槽72A、72B、72C和72D的每一个以围绕热岛的封闭图的形状形成，即沟槽72C围绕热岛71D，沟槽72D围绕热岛71E，并且双沟槽72A和72B围绕热岛71A。热岛71D包含MOSFET M1，热岛71A包含MOSFET M2和MOSFET M3，并且热岛71E包含MOSFET M4。还示出了没有被沟槽72A、72B、72C和72D之一围绕的内岛区域71C。
结合参看图4和5，可见热岛71D通过接触焊盘25A连接到包括焊料块44A和引线12A的热通道，热岛71E通过接触焊盘25B连接到包括焊料块44B和引线12B的热通道，以及热岛71A通过接触焊盘25C连接到包括焊料块44C和散热块12C的热通道。如图5所示，热岛71A还经由在图4的截面之外的焊料凸块44D、44E和44K连接到散热块。
沟槽72A、72B、72C和72D可通过常规的光刻和蚀刻工艺形成在有源层24A中。例如，沟槽掩模可形成且图案化在有源层24A的暴露表面上，其在要设置沟槽的区域之上具有开口。有源层24A可通过沟槽掩模中的开口蚀刻向下至绝缘层23A，以采用反应离子蚀刻形成沟槽，例如采用溴化氢（HBr）或六氟化硫（SF6）或类似的气体。然后，沟槽被热氧化，且然后可通过化学气相沉积填充诸如二氧化硅的绝缘材料或诸如非掺杂多晶硅的半绝缘材料。如本领域所知，可采用其它的材料或工艺填充沟槽。
上面的描述旨在示例而不是限制。本发明的很多选择性实施例对本领域的技术人员而言是明显的。本发明的一般原理仅限定在所附的权利要求中。

Claims (28)

1.一种半导体封装体，包括：
引线；
绝缘体上硅(SOI)芯片，该SOI芯片包括夹设在处理层和有源层之间的绝缘层，该处理层具有与该绝缘层接触的第一表面和与该第一表面相对的第二表面，该SOI芯片以该有源层面对该引线的方式在该封装体中定向；以及
金属凸块，连接该有源层的表面处的接触焊盘与该引线，该接触焊盘形成在有源层中的热岛中，该热岛由该有源层中的至少一个沟槽限定，该至少一个沟槽在该有源层的该表面和该绝缘层之间延伸并且被该有源层侧面包围，该至少一个沟槽填充有电介质材料，该SOI芯片、该金属凸块和该引线的至少一部分包封在模塑料中，该模塑料完全覆盖该处理层的该第二表面。
2.如权利要求1所述的半导体封装体，其中该热岛由双沟槽围绕。
3.如权利要求1所述的半导体封装体，其中该热岛包含至少一个半导体器件。
4.如权利要求1所述的半导体封装体，其中该引线从该模塑料的外表面突出。
5.如权利要求4所述的半导体封装体，还包括散热块和第二金属凸块，该第二金属凸块在该有源层的表面处连接第二接触焊盘与该散热块，该散热块具有暴露表面，该暴露表面与该模塑料的底表面共面且由该底表面围绕。
6.如权利要求5所述的半导体封装体，其中该散热块的水平截面面积为沿着垂直于该引线的侧壁的截面剖取的该引线的面积的至少五倍。
7.如权利要求1所述的半导体封装体，其中该半导体封装体包括DFN-型封装体，该引线的至少一个表面与该模塑料的外表面共面。
8.如权利要求7所述的半导体封装体，还包括散热块和第二金属凸块，该第二金属凸块在该有源层的表面处连接第二接触焊盘与该散热块，该散热块具有暴露表面，该暴露表面与该模塑料的底表面共面且由该底表面围绕。
9.如权利要求8所述的半导体封装体，其中该散热块的水平截面面积为沿着垂直于该引线的侧壁的截面剖取的该引线的面积的至少五倍。
10.如权利要求8所述的半导体封装体，其中该第二接触焊盘形成在该有源层的第二热岛中，该第二热岛由至少一个在该有源层的该表面和氧化物层之间延伸的至少一个第二沟槽限定，并且该至少一个第二沟槽填充有该电介质材料。
11.如权利要求10所述的半导体封装体，其中该热岛包含至少一个半导体器件。
12.一种半导体封装体，包括：
引线，从该半导体封装体延伸；
绝缘体上硅(SOI)芯片，包括夹设在处理层和有源层之间的绝缘层，该处理层具有与该绝缘层接触的第一表面和与该第一表面相对的第二表面，以及该SOI芯片以该有源层面对该引线的方式在该封装体中定向；
第一金属凸块，连接该有源层的表面处的第一接触焊盘与该引线；
模塑料，包封该SOI芯片、该第一金属凸块和至少一部分该引线，该模塑料完全覆盖该处理层的该第二表面；
散热块，具有表面，该表面与该模塑料的底表面共面且由该底表面围绕；以及
第二金属凸块，在该有源层的该表面处连接第二接触焊盘与该散热块。
13.如权利要求12所述的半导体封装体，其中配置第一热通道传导将该有源层中产生的热传到印刷电路板，该第一热通道包括该第一接触焊盘、该第一金属凸块和该引线。
14.如权利要求13所述的半导体封装体，其中配置该第一热通道电路电连接SOI芯片中的电路与印刷电路板。
15.如权利要求13所述的半导体封装体，其中配置第二热通道将该有源层中产生的热传导印刷电路板，该第二热通道包括该第二接触焊盘、该第二金属凸块和该散热块。
16.如权利要求12所述的半导体封装体，其中该散热块的水平截面面积为沿着垂直于该引线的侧壁的截面剖取的该引线的面积的至少五倍。
17.如权利要求12所述的半导体封装体，其中该第一接触焊盘形成在有源层中的热岛中，该热岛由至少一个填充有电介质的沟槽限定，以及该沟槽在该有源层的该表面和该绝缘层之间延伸并且被有源层侧面包围。
18.如权利要求17所述的半导体封装体，其中该热岛由双沟槽围绕。
19.如权利要求17所述的半导体封装体，其中该热岛包含至少一个半导体器件。
20.如权利要求12所述的半导体封装体，其中该引线从该模塑料的外表面突出。
21.如权利要求12所述的半导体封装体，其中该半导体封装体为DFN-型封装体，该引线的至少一个表面与该模塑料的外表面共面。
22.如权利要求21所述的半导体封装体，其中该散热块的水平截面面积为沿着垂直于该引线的侧壁的截面剖取的该引线的面积的至少五倍。
23.如权利要求21所述的半导体封装体，其中该第一接触焊盘形成在该有源层中的热岛中，该热岛由在该有源层的该表面和该绝缘层之间延伸的至少一个沟槽围绕，并且该沟槽填充有电介质材料。
24.如权利要求23所述的半导体封装体，其中该第二接触焊盘形成在该有源层中的第二热岛中，该第二热岛由在该有源层的该表面和该绝缘层之间延伸的至少一个第二沟槽围绕，并且该第二沟槽充有电介质材料。
25.如权利要求23所述的半导体封装体，其中该热岛包含至少一个半导体器件。
26.如权利要求12所述的半导体封装体，其中该模塑料的底表面与该引线的安装表面共面。
27.一种半导体封装体，包括：
引线，从该半导体封装体延伸；
绝缘体上硅(SOI)芯片，包括夹设在处理层和有源层之间的绝缘层，该处理层具有与该绝缘层接触的第一表面和与该第一表面相对的第二表面，以及该SOI芯片以该有源层面对该引线的方式在该封装体中定向；
第一金属凸块，连接该有源层的表面处的第一接触焊盘与该引线；
模塑料，包封该SOI芯片、该第一金属凸块和至少一部分该引线，该模塑料完全覆盖该处理层的该第二表面；以及
第二接触焊盘，形成在该有源层的该表面和该有源层的热岛中，该第二接触焊盘热连接该有源层至散热块。
28.如权利要求27所述的半导体封装体，其中该第一接触焊盘形成在该有源层中的热岛中，该热岛由在该有源层的该表面和该绝缘层之间延伸的至少一个沟槽围绕，以及该沟槽充有电介质材料。
CN201280050797.5A 2011-08-16 2012-08-12 包含绝缘体上硅的半导体封装体 Active CN103890904B (zh)

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