TW201318115A - 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻 - Google Patents
以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻 Download PDFInfo
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Abstract
來自一絕緣物上矽(SOI)晶粒之熱轉移藉由以一引線架上凸塊之方式將該晶粒安裝於一半導體封裝中而加以改良,其中焊料或其他金屬凸塊將該SOI晶粒之作用層連接至用以將該封裝安裝於一印刷電路板或其他支撐結構上之金屬引線。
Description
本申請案與標題為「Bump-on-Leadframe(BOL)Package Technology with Reduced Parasitics」之於2006年5月2日提出申請之第11/381,292號申請案相關,該申請案之全文以引用之方式併入本文中。
絕緣物上矽半導體晶粒用於其中期望在形成於晶粒中之半導體裝置之間提供一極有效之絕緣障壁之應用中。一絕緣物上矽(SOI)晶粒由三層組成:(1)一作用層,其中形成有半導體裝置,(2)一絕緣層,及(3)一處置層。絕緣層夾在作用層與處置層之間。作用層及處置層由矽形成;絕緣層通常由二氧化矽(經常簡單地稱為「氧化物」)形成。絕緣層亦可由熱生長氧化物與經沈積玻璃或氧化物之一夾層組成。處置層通常係三個層中最厚的。由於作用層及處置層由矽形成且因此具有相同溫度膨脹係數,因此晶粒係極熱穩定的。此外,由於絕緣層提供一強絕緣障壁,因此形成於作用層中之裝置可使用延伸穿過作用層之隔離結構極有效地彼此電絕緣。
圖1A展示含有一SOI晶粒3之一習用SOT狀半導體封裝1之一剖面圖。SOT或「小型電晶體」係用於封裝離散電晶體或低接針計數積體電路之一行業標準封裝。SOI晶粒3包含一作用層3A、一絕緣層3I及一處置層3H。SOI晶粒3經由處置層3H之經曝露表面安裝至一引線2B。作用層3A中之裝置(未展示)經由作用層3A之表面處之接觸襯墊(未展
示)且經由接合線4A及4B電連接至引線2A及2B。「鷗翼」引線2A及2B自模製化合物5突出。引線2A及2B之下部表面安裝至一印刷電路板(PCB)6。
圖1B展示含有一SOI晶粒13之一習用雙邊扁平無引線(DFN)半導體封裝11之一剖面圖。SOI晶粒13包含一作用層13A、一絕緣層13I及一處置層13H。SOI晶粒13經由處置層13H之經曝露表面安裝至一散熱塊12B。作用層13A中之裝置(未展示)經由作用層13A之表面處之接觸襯墊(未展示)且經由接合線14A及14B電連接至引線12A及12C。引線12A及12C具有與模製化合物15之側表面及底部表面共面之外部表面,亦即,不同於圖1A中之引線2A及2B,引線12A及12C不自模製化合物15突出。引線12A及12C以及散熱塊12B之下部表面用以將封裝11安裝至一PCB 16。
不幸地,一SOI晶粒之良好電絕緣性質形成熱問題,此乃因由形成於作用層中之裝置產生之熱被絕緣層陷獲。在封裝1及11中,舉例而言,SOI晶粒3及13之作用層藉由絕緣層及處置層而與引線實體及熱分離(接合線通常極薄且不轉移顯著熱量)。用於絕緣層之材料(諸如二氧化矽)經常係良好熱絕緣物。因此,作用層中之溫度可達到不可接受之高位準且可損壞或毀壞形成於SOI晶粒中之裝置。
因此,給一SOI晶粒提供促進移除由形成於晶粒中之半導體裝置產生之熱之一半導體封裝將係極有用的。自一電及熱兩者之觀點,此一解決方案將允許SOI晶粒達到其全部潛力。
在根據本發明之一半導體封裝中,一絕緣物上矽(SOI)晶粒以一引線架上凸塊(BOL)或「覆晶」方式定向使得在作用層面向一引線且一焊料或其他金屬凸塊連接該作用層之一表面處之一接觸襯墊與該引線。焊料可包括一合金、二元或三元金屬化合物(諸如鉛-錫(Pb-Sn)或錫-銀(Sn-Ag)),或者可包括任何軟金屬(諸如金、銀或錫)。此形成一熱路徑,透過該熱路徑產生於作用層中之熱可容易地轉移至封裝所安裝於其上之一印刷電路板或其他結構。
本發明可應用於各種各樣的封裝,包含SOT狀及DFN封裝。
在某些實施例中,SOI晶粒之作用層由絕緣溝渠分離成熱島,每一熱島藉助一或多個焊料凸塊連接至一引線。
藉由參考以下圖式將更佳地理解本發明,該等圖式未必按比例繪製且其中相似組件具有類似元件符號。
圖2A圖解說明根據本發明之一經模製SOT狀封裝30。封裝30含有具有一處置層22、一絕緣層23及一作用層24之一SOI晶粒21。SOI晶粒21分別藉助焊料凸塊34A及34B以引線架上凸塊(BOL)或「覆晶」樣式安裝於引線2A及2B上。SOI晶粒21經定向以使得作用層24面向引線2A及2B。焊料凸塊34A及34B分別與位於作用層24之表面處之接觸襯墊25A及25B進行電接觸且自其向下延伸。焊料凸塊34A及34B可由用於半導體封裝中之任何類型之焊料製成,舉例
而言,一鉛-錫(Pb-Sn)或錫-銀(Sn-Ag)焊料或者一軟金屬(諸如純錫(Sn)、純銀(Ag)或金(Au))。
SOI晶粒21、焊料凸塊34A及34B以及引線2A及2B之部分圍封於通常由塑膠製成之一模製化合物5中。通常由一金屬(諸如鋁)製成之「鷗翼」形引線2A及2B自模製化合物5突出且安裝至一印刷電路板(PCB)6。
作用層24通常含有複數個半導體裝置(MOSFET、雙極電晶體、二極體等),當作用層24中之電路操作時,該複數個半導體裝置中之某些裝置可產生實質熱量。如圖2A中所展示,存在產生於作用層24中之熱可藉由其傳導至PCB 6之兩個熱路徑:第一路徑包含接觸襯墊25A、焊料凸塊34A及引線2A,且第二路徑包含接觸襯墊25B、焊料凸塊34B及引線2B。此等熱路徑中之每一者亦可用作連接SOI晶粒中之電路與PCB 6之一電路徑。
封裝30之熱轉移特性遠優於圖1A中所展示之可比較之先前技術封裝1之彼等熱轉移特性,此乃因存在兩個高度傳導熱路徑,透過該兩個高度傳導熱路徑可將產生於SOI晶粒21中之熱轉移至PCB 6。此外,藉由輻射及對流自引線2A及2B移除產生於SOI晶粒21中之熱中之某些熱。
用於製作封裝30之製程係此項技術中眾所周知的。在一例示性製程中,最初將焊料球放置於接觸襯墊25A及25B上且將其充分加熱以致使焊料黏附至該等接觸襯墊。可藉由穿過一「模板」遮罩將焊料球滴落至晶粒上以使得該等球僅落至該等球意欲黏附至其之接合襯墊之頂部上或緊鄰
處之晶粒上來配置該等球之放置。然後,將SOI晶粒21倒置,且使得焊料球分別與引線2A及2B接觸,彼時引線2A及2B仍係一引線架之部分。然後,將焊料再次加熱(回流)以使得焊料球形成黏附至接觸襯墊25A及引線2A之焊料凸塊34A以及黏附至接觸襯墊25B及引線2B之焊料凸塊34B。一旦焊料凸塊34A及34B黏附至SOI晶粒21以及引線2A及2B,便藉由一注射模製製程將總成圍封於模製化合物5中,然後將該等引線與引線架中之其他引線單粒化。
圖2B圖解說明安裝於一雙邊扁平無引線(DFN)封裝40中之SOI晶粒21。SOI晶粒21分別藉助焊料凸塊44A及44B以BOL樣式安裝於引線12A及12B上。焊料凸塊44A及44B分別與接觸襯墊25A及25B進行電接觸且自其向下延伸。
SOI晶粒21、焊料凸塊44A及44B以及引線12A及12B圍封於通常由塑膠製成之一模製化合物15中。不同於自模製化合物5突出的封裝30中之鷗翼形引線2A及2B,引線12A及12B具有與模製化合物15之一底部表面15B共面之底部表面12AB及12BB以及與模製化合物15之橫向表面15A及15C共面之橫向表面12AL及12BL。引線12A及12B之底部表面12AB及12BB安裝至印刷電路板(PCB)6。
如圖2B中所展示,存在產生於作用層24中之熱可藉由其傳導至PCB 6之兩個熱路徑:第一路徑包含接觸襯墊25A、焊料凸塊44A及引線12A,且第二路徑包含接觸襯墊25B、焊料凸塊44B及引線12B。此等熱路徑中之每一者亦可用作連接SOI晶粒21中之電路與PCB 6之一電路徑。
封裝40之熱轉移特性遠優於圖1B中所展示之可比較之先前技術封裝11之彼等熱轉移特性,此乃因存在兩個高度傳導熱路徑,藉由該兩個高度傳導熱路徑可將產生於SOI晶粒21中之熱轉移至PCB 6。
圖3A圖解說明根據本發明之一經模製SOT狀封裝50。封裝50含有具有一處置層22A、一絕緣層23A及一作用層24A之一SOI晶粒21A以及一經曝露晶粒襯墊或散熱塊2C。接觸襯墊25A、25B及25C位於作用層24A之經曝露表面處。在其他方面,封裝50類似於圖2A中所展示之封裝30,惟封裝50中之模製化合物5之一底部表面29與引線2A及2B之安裝表面2AM及2BM共面除外。在封裝50中,SOI晶粒21A分別藉助焊料凸塊34A、34B及34C以BOL樣式安裝於引線2A及2B以及散熱塊2C上。焊料凸塊34A、34B及34C分別與位於作用層24A之表面處之接觸襯墊25A、25B及25C進行電接觸且自其向下延伸。
SOI晶粒21A,焊料凸塊34A、34B及34C,散熱塊2C以及引線2A及2B之部分圍封於模製化合物5中。散熱塊2C具有與模製化合物5之一底部表面29共面且由底部表面29環繞之一經曝露表面28。散熱塊2C之底部表面28與PCB 6接觸。
如圖3A中所展示,存在產生於作用層24A中之熱可藉由其傳導至PCB 6之三個熱路徑:第一路徑包含接觸襯墊25A、焊料凸塊34A及引線2A,第二路徑包含接觸襯墊25B、焊料凸塊34B及引線2B,且第三路徑包含接觸襯墊
25C、焊料凸塊34C及散熱塊2C。此等熱路徑中之每一者亦可用作連接SOI晶粒中之電路與PCB 6之一電路徑。
為促進透過散熱塊2C之熱轉移,穿過一水平剖面截取之散熱塊2C之面積實質上大於(例如,三至五倍或更大)分別穿過與引線2A或2B之壁垂直之一剖面截取之引線2A或2B之面積。
圖3B圖解說明安裝於一雙邊扁平無引線(DFN)封裝60中之SOI晶粒21A。封裝60類似於圖2B中所展示之封裝40,惟封裝60亦含有一經曝露晶粒襯墊或散熱塊12C除外。在封裝60中,SOI晶粒21A分別藉助焊料凸塊44A、44B及44C以BOL樣式安裝於引線12A及12B以及散熱塊12C上。焊料凸塊44A、44B及44C分別與位於作用層24A之表面處之接觸襯墊25A、25B及25C進行電接觸且自其向下延伸。
SOI晶粒21A,焊料凸塊44A、44B及44C,引線12A及12B以及散熱塊12C圍封於模製化合物15中。引線12A及12B具有與模製化合物15之一底部表面39共面之底部表面12AB及12BB以及與模製化合物15之橫向表面15A及15C共面之橫向表面12AL及12BL。引線12A及12B之底部表面12AB及12BB以及散熱塊12C之底部表面38安裝至PCB 6。
如圖3B中所展示,存在產生於作用層24A中之熱可藉由其傳導至PCB 6之三個熱路徑:第一路徑包含接觸襯墊25A、焊料凸塊44A及引線12A,第二路徑包含接觸襯墊25B、焊料凸塊44B及引線12B,且第三路徑包含接觸襯墊25C、焊料凸塊44C及散熱塊12C。此等熱路徑中之每一者
亦可用作連接SOI晶粒21A中之電路與PCB 6之一電路徑。
為促進透過散熱塊12C之熱轉移,穿過一水平剖面截取之散熱塊12C之面積實質上大於(例如,五倍或更大)分別穿過與引線12A或12B之壁垂直之一剖面截取之引線12A或12B之面積。
在某些實施例中,將SOI晶粒之作用層劃分成「熱島」,以使得一個熱島中之裝置與由另一熱島中之裝置產生之熱絕緣。圖4係圖3B之DFN封裝60之一詳細剖面圖,其展示作用層24A由絕緣溝渠72A、72B、72C及72D刺穿,從而形成熱島71A、71D及71E。溝渠72A、72B、72C及72D通常填充有一絕緣電介質,諸如氧化矽、氮化矽、具有一經沈積玻璃之熱生長二氧化矽或者含有或環繞一經沈積多晶矽層之熱生長二氧化矽。
圖5係圖3B之封裝中之SOI晶粒21A之一平面圖。指示了在其處截取圖4之剖面4-4。如所展示,溝渠72A、72B、72C及72D中之每一者形成為環繞一熱島之一閉合圖之形狀,亦即,溝渠72C環繞熱島71D,溝渠72D環繞熱島71E,且雙重溝渠72A與72B環繞熱島71A。熱島71D含有一MOSFET M1,熱島71A含有MOSFET M2及MOSFET M3,且熱島71E含有一MOSFET M4。亦展示了未由溝渠72A、72B、72C及72D中之一者環繞之一島間區71C。
一起觀察圖4及圖5,可看出熱島71D透過接觸襯墊25A連接至包含焊料凸塊44A及引線12A之一熱路徑,熱島71E透過接觸襯墊25B連接至包含焊料凸塊44B及引線12B之一
熱路徑,且熱島71A透過接觸襯墊25C連接至包含焊料凸塊44C及散熱塊12C之一熱路徑。如圖5中所展示,熱島71A亦經由在圖4之剖面外側之焊料凸塊44D、44E及44K連接至散熱塊。
溝渠72A、72B、72C及72D可藉由習用光微影及蝕刻製程形成於作用層24A中。舉例而言,一溝渠遮罩可形成且圖案化於作用層24A之經曝露表面上,其中開口在溝渠將位於其中之區上方。可使用一反應離子蝕刻(舉例而言,使用溴化氫(HBr)或六氟化硫(SF6)或類似氣體)透過溝渠遮罩中之開口蝕刻作用層24A向下到達絕緣層23A以形成溝渠。然後將該等溝渠熱氧化且然後可藉由化學汽相沈積用一絕緣材料(諸如二氧化矽)或一半絕緣材料(諸如未經摻雜多晶矽)填充該等溝渠。如此項技術中已知,其他材料及製程可用於填充溝渠。
上文說明意欲係圖解說明性而非限制性。熟習此項技術者將明瞭本發明之諸多替代實施例。僅在以下申請專利範圍中定義本發明之寬廣原理。
1‧‧‧習用小型電晶體狀半導體封裝/封裝/先前技術封裝
2A‧‧‧引線/「鷗翼」引線/「鷗翼」形引線/鷗翼形引線
2AM‧‧‧安裝表面
2B‧‧‧引線/「鷗翼」引線/「鷗翼」形引線/鷗翼形引線
2BM‧‧‧安裝表面
2C‧‧‧散熱塊
3‧‧‧絕緣物上矽晶粒
3A‧‧‧作用層
3H‧‧‧處置層
3I‧‧‧絕緣層
4A‧‧‧接合線
4B‧‧‧接合線
5‧‧‧模製化合物
6‧‧‧印刷電路板
11‧‧‧習用雙邊扁平無引線半導體封裝/封裝/先前技術封裝
12A‧‧‧引線
12AB‧‧‧底部表面
12AL‧‧‧橫向表面
12B‧‧‧散熱塊/引線
12BB‧‧‧底部表面
12BL‧‧‧橫向表面
12C‧‧‧引線/散熱塊
13‧‧‧絕緣物上矽晶粒
13A‧‧‧作用層
13H‧‧‧處置層
13I‧‧‧絕緣層
14A‧‧‧接合線
14B‧‧‧接合線
15‧‧‧模製化合物
15A‧‧‧橫向表面
15B‧‧‧底部表面
15C‧‧‧橫向表面
16‧‧‧印刷電路板
21‧‧‧絕緣物上矽晶粒
21A‧‧‧絕緣物上矽晶粒
22‧‧‧處置層
22A‧‧‧處置層
23‧‧‧絕緣層
23A‧‧‧絕緣層
24‧‧‧作用層
24A‧‧‧作用層
25A‧‧‧接觸襯墊
25B‧‧‧接觸襯墊
25C‧‧‧接觸襯墊
28‧‧‧經曝露表面/底部表面
29‧‧‧底部表面
30‧‧‧經模製小型電晶體狀封裝/封裝
34A‧‧‧焊料凸塊
34B‧‧‧焊料凸塊
34C‧‧‧焊料凸塊
38‧‧‧底部表面
39‧‧‧底部表面
40‧‧‧雙邊扁平無引線封裝/封裝
44A‧‧‧焊料凸塊
44B‧‧‧焊料凸塊
44C‧‧‧焊料凸塊
44D‧‧‧焊料凸塊
44E‧‧‧焊料凸塊
44K‧‧‧焊料凸塊
50‧‧‧經模製小型電晶體狀封裝/封裝
60‧‧‧雙邊扁平無引線封裝/封裝
71A‧‧‧熱島
71C‧‧‧島間區
71D‧‧‧熱島
71E‧‧‧熱島
72A‧‧‧絕緣溝渠/溝渠
72B‧‧‧絕緣溝渠/溝渠
72C‧‧‧絕緣溝渠/溝渠
72D‧‧‧絕緣溝渠/溝渠
M1‧‧‧金屬氧化物半導體場效電晶體
M2‧‧‧金屬氧化物半導體場效電晶體
M3‧‧‧金屬氧化物半導體場效電晶體
M4‧‧‧金屬氧化物半導體場效電晶體
圖1A展示含有一絕緣物上矽(SOI)晶粒之一習用SOT狀封裝之一剖面圖。
圖1B展示含有一SOI晶粒之一習用DFN封裝之一剖面圖。
圖2A展示不具有一散熱塊之含有一引線架上凸塊(BOL)安裝式SOI晶粒之經模製SOT狀半導體封裝之一剖面圖。
圖2B展示不具有一散熱塊之含有BOL安裝式SOI晶粒之一雙邊扁平無引線(DFN)半導體封裝之一剖面圖。
圖3A展示具有一經曝露散熱塊之含有一BOL安裝式SOI晶粒之經模製SOT狀半導體封裝之一剖面圖。
圖3B展示具有一經曝露散熱塊之含有一BOL安裝式SOI晶粒之一雙邊扁平無引線(DFN)半導體封裝之一剖面圖。
圖4係圖3B中所展示之DFN封裝之一更詳細剖面圖。
圖5係圖3B之封裝中之SOI晶粒之一平面圖,其展示由溝渠隔離之熱島及自每一熱島延伸之一或多個熱通孔。
6‧‧‧印刷電路板
12A‧‧‧引線
12AB‧‧‧底部表面
12AL‧‧‧橫向表面
12B‧‧‧散熱塊/引線
12BB‧‧‧底部表面
12BL‧‧‧橫向表面
12C‧‧‧引線/散熱塊
15‧‧‧模製化合物
15A‧‧‧橫向表面
15C‧‧‧橫向表面
21A‧‧‧絕緣物上矽晶粒
22A‧‧‧處置層
23A‧‧‧絕緣層
24A‧‧‧作用層
25A‧‧‧接觸襯墊
25B‧‧‧接觸襯墊
25C‧‧‧接觸襯墊
38‧‧‧底部表面
39‧‧‧底部表面
44A‧‧‧焊料凸塊
44B‧‧‧焊料凸塊
44C‧‧‧焊料凸塊
60‧‧‧雙邊扁平無引線封裝/封裝
Claims (12)
- 一種半導體封裝,其包括:一引線;一絕緣物上矽(SOI)晶粒,該SOI晶粒包括夾在一處置層與一作用層之間的一絕緣層,該SOI晶粒在該封裝中經定向使得該作用層面向該引線;及一金屬凸塊,其連接該作用層之一表面處之一接觸襯墊與該引線;其中該SOI晶粒、該金屬凸塊及該引線之至少一部分圍封於一模製化合物中。
- 如請求項1之半導體封裝,其中該接觸襯墊形成於該作用層中之一熱島中,該熱島由在該作用層之該表面與該絕緣層之間延伸之至少一個溝渠環繞,該溝渠填充有一介電材料。
- 如請求項2之半導體封裝,其中該熱島由一雙重溝渠環繞。
- 如請求項2之半導體封裝,其中該熱島含有至少一個半導體裝置。
- 如請求項1之半導體封裝,其中該半導體封裝包括一SOT狀封裝,該引線自該模製化合物之一外側表面突出。
- 如請求項5之半導體封裝,其進一步包括一散熱塊及一第二金屬凸塊,該第二金屬凸塊連接該作用層之該表面處之一第二接觸襯墊與該散熱塊,該散熱塊具有與該模製化合物之一底部表面共面且由該底部表面環繞之一經 曝露表面。
- 如請求項6之半導體封裝,其中該散熱塊之一水平剖面面積比在與該引線之一壁垂直之一剖面處截取之該引線之一面積大至少五倍。
- 如請求項1之半導體封裝,其中該半導體封裝包括一DFN型封裝,該引線具有與該模製化合物之一外側表面共面之至少一個表面。
- 如請求項8之半導體封裝,其進一步包括一散熱塊及一第二金屬凸塊,該第二金屬凸塊連接該作用層之該表面處之一第二接觸襯墊與該散熱塊,該散熱塊具有與該模製化合物之一底部表面共面且由該底部表面環繞之一經曝露表面。
- 如請求項9之半導體封裝,其中該散熱塊之一水平剖面面積比在與該引線之一壁垂直之一剖面處截取之該引線之一面積大至少五倍。
- 如請求項9之半導體封裝,其中該接觸襯墊形成於該作用層中之一熱島中,該熱島由在該作用層之該表面與該絕緣層之間延伸之至少一個溝渠環繞,該溝渠填充有一介電材料,且其中該第二接觸襯墊形成於該作用層中之一第二熱島中,該第二熱島由在該作用層之該表面與氧化物層之間延伸之至少一個第二溝渠環繞,該第二溝渠填充有該介電材料。
- 如請求項11之半導體封裝,其中該熱島含有至少一個半導體裝置。
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US13/210,592 US8502362B2 (en) | 2011-08-16 | 2011-08-16 | Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance |
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TW103129755A TWI497654B (zh) | 2011-08-16 | 2012-08-16 | 以引線架上凸塊之方式所安裝之含有絕緣物上矽晶粒之半導體封裝以提供低熱阻 |
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Country Status (6)
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KR (1) | KR102012989B1 (zh) |
CN (1) | CN103890904B (zh) |
HK (1) | HK1194204A1 (zh) |
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-
2011
- 2011-08-16 US US13/210,592 patent/US8502362B2/en active Active
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2012
- 2012-08-12 CN CN201280050797.5A patent/CN103890904B/zh active Active
- 2012-08-12 KR KR1020147003697A patent/KR102012989B1/ko active IP Right Grant
- 2012-08-12 WO PCT/US2012/050496 patent/WO2013025575A1/en active Application Filing
- 2012-08-16 TW TW101129758A patent/TWI455256B/zh active
- 2012-08-16 TW TW103129755A patent/TWI497654B/zh active
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- 2013-08-05 US US13/959,197 patent/US8916965B2/en active Active
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Also Published As
Publication number | Publication date |
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US8502362B2 (en) | 2013-08-06 |
WO2013025575A1 (en) | 2013-02-21 |
KR20140054049A (ko) | 2014-05-08 |
US8916965B2 (en) | 2014-12-23 |
TWI455256B (zh) | 2014-10-01 |
KR102012989B1 (ko) | 2019-08-21 |
US20140035133A1 (en) | 2014-02-06 |
US20130043595A1 (en) | 2013-02-21 |
HK1194204A1 (zh) | 2014-10-10 |
TWI497654B (zh) | 2015-08-21 |
CN103890904B (zh) | 2016-09-28 |
TW201503297A (zh) | 2015-01-16 |
CN103890904A (zh) | 2014-06-25 |
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