TWI431746B - 半導體元件 - Google Patents

半導體元件 Download PDF

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Publication number
TWI431746B
TWI431746B TW097122669A TW97122669A TWI431746B TW I431746 B TWI431746 B TW I431746B TW 097122669 A TW097122669 A TW 097122669A TW 97122669 A TW97122669 A TW 97122669A TW I431746 B TWI431746 B TW I431746B
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TW
Taiwan
Prior art keywords
hole
bump
wiring board
printed wiring
conductive particles
Prior art date
Application number
TW097122669A
Other languages
English (en)
Other versions
TW200919678A (en
Inventor
Dai Sasaki
Original Assignee
Elpida Memory Inc
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Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Publication of TW200919678A publication Critical patent/TW200919678A/zh
Application granted granted Critical
Publication of TWI431746B publication Critical patent/TWI431746B/zh

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    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Description

半導體元件
本發明係關於半導體封裝之安裝構造。
近年來，半導體元件之密集度逐年提高，伴隨於此，高密度化、高性能化、高速化、線路微細化、多層化等正在進展。另一方面，為了安裝之高密度化，需要使封裝尺寸小型化及薄型化。
例如BGA(Ball Grid Array,球柵陣列)或CSP(Chip Size Package,晶片尺寸封裝)等，具有在具通孔之印刷線路板上安裝半導體元件，並將該半導體元件與印刷線路板之間藉由引線接合或凸塊連接後，將印刷線路板之安裝面側以密封樹脂密封之構造。於該情形，由於可在印刷線路板之安裝面的相反側之面，通過通孔設置連接端子，因此成為可因應於多針腳的封裝。
圖9顯示習知覆晶晶片安裝構造之剖面圖。如圖9所示，習知之覆晶晶片安裝構造10，係在半導體晶片1形成稱為凸塊2之突起電極，將半導體晶片1面朝下，使印刷線路板3之接合區4與凸塊2連接，並將半導體晶片1與印刷線路板3的間隙以熱固性黏著劑9固定。
於印刷線路板3，具備：接合區4；線路圖案6a，從該接合區4引出；另一線路圖案6b，形成在印刷線路板3之與半導體晶片1的安裝面3a為相反側之面3b；球形端子5，形成在6b；及，通孔7，連接線路圖案6a與線路圖案6b。
習知的覆晶晶片安裝構造10，由於印刷線路板3之安裝面3a之線路圖案6a從接合區4引出，通過通孔7而於相反側之面3b，將線路圖案6b迴繞至球形端子5，因此有無法達成線路圖案縮短的問題。
在此，於專利文獻1或專利文獻2中，揭示使導電性材料介於凸塊與通孔之間的安裝構造，能因應縮短印刷線路板之線路長 度的要求。
然而，習知的半導體封裝，無法解決因為半導體晶片之線膨脹係數與印刷線路板之線膨脹係數的差異而產生的應力所致連接部斷裂的問題，現狀為：並非滿足半導體封裝之連接可靠性之安裝構造。
[專利文獻1]日本特開2003－324126號[專利文獻2]日本特開2002－260444號
本發明係為解決上述課題而生，目的在於提供一種半導體封裝之安裝構造，縮短從半導體晶片往與印刷線路板之安裝面為相反側面之線路圖案的線路長度，同時，減輕由於半導體晶片之線膨脹係數與印刷線路板之線膨脹係數的差異所生的應力，連接部不斷裂、連接可靠性高。
為了達成上述目的，本發明採用以下構成。
本發明之半導體封裝之安裝構造，具備：印刷線路板，具有貫通安裝面及其相反側面之通孔；通孔接合區，以堵塞與通孔之安裝面為相反側面之開口部的方式，形成於印刷線路板之相反側面而與通孔相通；半導體晶片，具有安裝在安裝面的凸塊；熱固性黏著劑，充填於半導體晶片與印刷線路板之安裝面間的間隙；於通孔中充填有由導電性粒子與絕緣樹脂所構成之異向性導電材料，同時，於通孔中插入有凸塊，藉由導電性粒子將凸塊與通孔導通。
本發明之半導體封裝之安裝構造，藉由導電性粒子使凸塊之前端部與通孔接合區導通較佳。又，藉由導電性粒子使凸塊之側面部與通孔之導體部導通較佳。再者，藉由凸塊之側面部與通孔之導體部接觸而導通較佳。
本發明之半導體封裝之安裝構造，較佳為：凸塊徑R1小於通孔徑R2。又，較佳為：凸塊高度H大於通孔深度D。再者，較佳為：熱固性黏著劑之線膨脹係數、異向性導電材料中包含之絕緣樹脂之線膨脹係數，落於半導體晶片之線膨脹係數與印刷線路板之線膨脹係數之間。
如以上所説明，依照本發明之半導體安裝構造，半導體晶片之凸塊與通孔導通，通孔導通於位在印刷線路板之安裝面之相反側的通孔接合區，因此能藉由通孔及通孔接合區，使半導體晶片之線路迴繞至印刷線路板之相反側。藉此，可縮短線路長度，能提供因應於高速化要求之半導體封裝之安裝構造。
又，雖然因為半導體晶片之線膨脹係數與印刷線路板之線膨脹係數差異會產生應力，但是由於將凸塊與通孔以具有彈性的導電性粒子連接，因此，向連接部之應力，可藉由導電性粒子而減輕。
再者，可藉由為低彈性係數且線膨脹係數落在半導體晶片之線膨脹係數與印刷線路板之線膨脹係數間的熱固性黏著劑，將半導體晶片與印刷線路板接合，因此，凸塊與通孔向連接部之應力亦能藉由熱固性黏著劑而減輕。
由以上，可提供不發生凸塊與通孔的連接部斷裂之問題且高連接可靠性之半導體封裝之安裝構造。
 (實施發明之最佳形態)
以下，對於本發明之實施形態參照圖式説明。
圖1顯示本發明實施形態之半導體封裝之剖面圖。
如圖1所示，本實施形態之半導體封裝之安裝構造11，概略構成為：將半導體晶片1與印刷線路板3以熱固性黏著劑9固定。
再者，於設置在印刷線路板3之通孔7內部，插入有半導體 晶片1之凸塊2，藉由凸塊2與通孔接合區7a，充填於通孔7之異向性導電材料8中之導電性粒子8a被夾持而壓縮。並且，通過導電性粒子8a，使凸塊2與通孔接合區7a導通。
本實施形態之凸塊2，如圖1所示，設置於半導體晶片1。
凸塊2以金屬凸塊較佳，焊錫凸塊或金凸塊更佳，金柱凸塊(gold stud bump)尤佳。又，本實施形態中，如圖1所示，由於將凸塊2插入於後述通孔7內，因此，需要控制凸塊之前端為細、凸塊高度為高，以應用成為圖釘形狀之金柱凸塊較佳。
凸塊2之凸塊徑R1不特別限定，以15~100 μm之範圍較佳。凸塊徑R1若低於15 μm，則凸塊之形成變得困難。另一方面，凸塊徑R1若超過100 μm，則封裝小型化、高密度化變得困難。因此，凸塊徑R1，以15~100 μm之範圍較佳，20~80 μm之範圍更佳。又，凸塊2之凸塊徑R1，較佳為：較設置在印刷線路板3之通孔7之通孔徑R2為小。
凸塊2之高度H不特別限定，以50~100 μm之範圍較佳。又，凸塊2之高度H，較佳為：較設置於印刷線路板3之通孔7之通孔深度D(與印刷線路板8之厚度約相等)為大，更佳為：考慮通孔7之深度D、接合時凸塊2之壓縮量、接合後之半導體晶片1與印刷線路板3之距離(standoff,間距)而形成。
例如，將通孔7之深度D定為25 μm，壓縮量定為5 μm，間距定為50 μm時，例如凸塊2之高度H可為80 μm。
凸塊2之間隔(凸塊間距)不特別限定，以窄間距(例如0.4mm以下)較佳。超過0.4mm之凸塊間距，可對應於習知的安裝構造。因此，凸塊間距以0.4mm以下較佳，0.2mm以下更佳。
本實施形態之印刷線路板3，不特別限定，可應用多層建成(build up)基板、撓性基板、軟硬合成基板等，較佳為應用雙面線路構造之撓性基板。又，藉由對於撓性基板應用COF(Chip on Film)安裝，可提供內部導線(inner lead)之線路間距為35 μm以下之微線線路對應的半導體封裝之安裝構造11。
本實施形態之通孔7，如圖1所示，由設置於印刷線路板3之貫通孔7c及至少形成於貫通孔7c之內面的導體部7b所形成。又，於安裝面之相反側之面3b，以堵塞通孔7之貫通孔7c之方式形成有通孔接合區7a。通孔接合區7a與導體部7b接合而導通，又，通孔接合區7a部與安裝面之相反側面3b的線路圖案6b為一體化。再者，通孔7之導體部7b與安裝面3a之線路圖案6a連接。
藉此，藉由通孔7之導體部7b及通孔接合區7a，將印刷線路板3之安裝面3a之線路圖案6a與安裝面之相反側之面3b之線路圖案6b導通。
通孔7之導體部7b及通孔接合區7a之材質，以Cu、Al、Au、Cr、Ti之金屬較佳，Cu更佳。
又，通孔徑R2大於前述凸塊徑R1較佳，於30~120 μm之範圍更佳。
本實施形態之異向性導電材料8，如圖1所示，充填在設置於印刷線路板3之通孔7中。異向性導電材料8，不特別限定，異向性導電膜(ACF：Anisotropic Conductive Film)，或異向性導電糊漿(ACP：Anisotropic Conductive Paste)較佳，本實施形態中，由於僅在通孔7內部選擇性地充填，因此異向性導電糊漿(ACP)更佳。
異向性導電材料8，由後述導電性粒子8a與黏結劑樹脂絕緣樹脂8b所構成，絕緣樹脂8b，可應用合成橡膠、熱塑性樹脂、熱固性樹脂等。又，絕緣樹脂8b，一般而言，要求高Tg(玻璃移轉溫度)、低給水率、低線膨脹係數等特性。
再者，本實施形態中，絕緣樹脂8b之線膨脹係數以5~30ppm/℃之範圍較佳，與後述熱固性黏著劑9之線膨脹係數為同程度，同時落在半導體晶片1之線膨脹係數與印刷線路板3之線膨脹係數之間更佳。
導電性粒子8a不特別限定，鎳(Ni)單體及經施以鍍金處理之Ni這些金屬核本身，或對於苯乙烯、壓克力等樹脂核施以鍍金處理者較佳，由於要求高彈性，因此，較佳為對於樹脂核施以鍍金 處理者。
導電性粒子8a，一般而言，不僅要求電導通，尚要求鄰接電極間不相接之形狀、適度分散率及粒徑尺寸。本實施形態中，由於僅充填通孔7內部且藉由後述熱固性黏著劑9而被覆，因此，由於導電性粒子8a流出到通孔7外部而使鄰接電極短路的可能性低。
導電性粒子8a之粒徑，以3~10 μm之範圍較佳。導電性粒子8a之粒徑若增大，則壓縮量大，減輕向連接部之應力的效果大，故為較佳。又，導電性粒子8a之粒徑以較半導體晶片1與印刷線路板3間之距離小較佳，以使得不因為凸塊2之插入，而於導電性粒子8a從通孔7內溢出時，在鄰接電極間發生短路。
又，異向性導電材料8中，導電性粒子8a之含量，以5~15vol%之範圍較佳。異向性導電材料8中之導電性粒子8a之含有率若高，則凸塊2與通孔7之間，導電性粒子8a被壓縮的機會增高，且連接可靠性增高，故較佳。
本實施形態之熱固性黏著劑9，如圖1所示，作為底部填充樹脂，充填在半導體晶片1與印刷線路板3間的間隙，於熱硬化時，固定半導體晶片1與印刷線路板3。熱固性黏著劑9不特別限定，可為液狀亦可為膜狀。
又，熱固性黏著劑9，以低彈性係數較佳，彈性係數5GPa以下更佳。
再者，熱固性黏著劑9之線膨脹係數，以5~30ppm/℃之範圍較佳，更佳為落在半導體晶片1之線膨脹係數與印刷線路板3之線膨脹係數之間。
又，熱固性黏著劑9之線膨脹係數，與異向性導電材料8中之絕緣樹脂8b之線膨脹係數，以同程度更佳。熱固性黏著劑9與異向性溥電材料8成為一體，可減輕半導體晶片1與印刷線路板3之線膨脹係數差異所產生應力，能提供凸塊2與通孔7之連接部可靠性高的半導體封裝之安裝構造。
於本實施形態中，關於凸塊2與通孔7之連接部，參照圖式説明。
圖2(A)~(C)，為本實施形態之凸塊2與通孔7之連接部分之1接腳分量的擴大剖面圖。如圖2(A)所示，構成通孔7之貫通孔7c之中心附近插入有凸塊2時，藉由在凸塊2之前端部2a與通孔接合區7a之間將導電性粒子8a壓縮，可良好地導通。
又，如圖2(B)所示，從構成通孔7之貫通孔7c之中心起略為偏離的位置有凸塊2插入之情形，在凸塊2之前端部2a與通孔接合區7a之間將導電性粒子8a壓縮，同時，凸塊2之側面部2b與通孔7之導體部7b之間，亦有導電性粒子8a壓縮，藉此能確保良好導通。
再者，如圖2(C)所示，從構成通孔7之貫通孔7c之中心偏離許多的位置插入有凸塊2時，凸塊2之前端部2a與通孔接合區7a之間有導電性粒子8a壓縮，同時，在凸塊2之肩部2c與通孔7之導體部7b之間，不經由導電柱粒子8a，藉由凸塊2變形而接觸，能確保良好導通。
如以上所述，本實施形態之半導體封裝之安裝構造中，即使是半導體晶片1安裝時之配置發生偏離，及半導體晶片1之凸塊2與印刷線路板3之通孔7之間距發生偏離時，亦能確保良好的導通。
參照圖式說明本實施形態之製造方法。圖3~圖8，說明本實施形態之半導體封裝之安裝構造之製造方法，圖3為顯示凸塊形成步驟之剖面圖、圖4~圖6顯示樹脂供給步驟之剖面圖，圖7~圖8顯示凸塊連接步驟之剖面圖。
又，各圖為了說明本實施形態之製造方法，僅將多數電極之中，1接腳部分擴大顯示，圖示各部之大小或厚度、尺寸等，與實際半導體封裝的安裝構造尺寸關係不同。
本實施形態之半導體封裝之安裝構造之製造方法，由凸塊形成步驟、樹脂供給步驟、凸塊連接步驟概略構成。以下，對於各 步驟依序説明。
最初，在凸塊形成步驟中，如圖3所示，於設置在半導體晶片1之電極接墊1a上，形成凸塊2。
凸塊2之形成方法不特別限定，可使用微影方法之鍍膜工法，或超音波及加熱方式。
例如，依照超音波及加熱方式，可形成金柱凸塊。具體而言，將金線之前端以電極產生火花，形成金球，將該金球抵緊到半導體晶片1之電極接墊1a。其次，提供超音波振動，使得金球與電極接墊1a之間形成金屬間化合物。之後，將金線拉伸截斷，整平其前端，可得到高度均勻且前端平滑之金柱凸塊。
其次，於樹脂供給步驟，首先將圖4所示之印刷線路板3設置成：使通孔7之開口部側即安裝面3a位在上側，通孔接合區7a側即安裝面之相反側之面3b位在下側。其次，如圖5所示，將異向性導電材料8充填於印刷線路板3之通孔7中。於此時，異向性導電材料8僅充填在通孔7內，且異向性導電材料8中之導電位粒子8a不殘存於通孔7外即安裝面3a上較佳。具體而言，異向性導電材料8使用ACP時，可使用以塗布器等僅注入到通孔7內之方法，或將ACP利用印刷充填於通孔7內之後，將塗布在印刷線路板3之安裝面3a的ACP以溶劑等除去之方法。
其次，如圖6所示，將熱固性黏著劑9供給到包含通孔7之開口部的印刷線路板3的安裝面3a。熱固性黏著劑9，不僅是糊漿狀之樹脂，亦可使用膜狀樹脂。具體而言，糊漿狀樹脂例：NCP(Non Conductive Paste)，或膜上之樹脂例：NCF(Non Conductive Film)。
最後，於凸塊連接步驟，如圖7所示，將半導體晶片1以使凸塊2朝下之方式面向下，配置凸塊2與通孔7的位置。其次，如圖8所示，將凸塊2裝載成嵌入通孔7，若將半導體晶片1加壓，則充填於通孔7之導電性粒子8a，會被夾持在凸塊2之底部2a與通孔接合區7a而成壓縮狀態。之後，進行加熱處理，使異向性導 電材料8中之絕緣樹脂8b及熱固性黏著劑9硬化，將半導體晶片1與印刷線路板3固定。安裝條件例例如，藉由1N/凸塊之加重量，將半導體晶片1加壓，並於200℃加熱。
如以上方式，可製造如圖1所示之半導體封裝之安裝構造11。
如以上所説明，依照本實施形態，半導體晶片1之凸塊2與通孔7導通，通孔7導通於位在印刷線路板3之安裝面的相反側面3b的通孔接合區7a，因此，通過通孔7與通孔接合區7a，可將半導體晶片1之線路迴繞至印刷線路板3之相反側之線路6b。藉此，能縮短線路長度，可提供能因應於高速化要求之半導體封裝之安裝構造11。
又，由於半導體晶片1之線膨脹係數與印刷線路板3之線膨脹係數差異所生應力，由於凸塊2與通孔7通過具彈性之導電性粒子8a而連接，因此，凸塊2與通孔7向連接部之應力，因為導電性粒子8a而減輕。
又，由於低彈性係數且具線膨脹係數落在半導體晶片之線膨脹係數與印刷線路板之線膨張係數之間的熱固性黏著劑9，將半導體晶片1與印刷線路板3接合，因此，凸塊2與通孔7向連接部之應力，亦可藉由熱固性黏著劑9而減輕。
又，能成為凸塊2與通孔7之連接，不論凸塊2插入於通孔7內之插入位置，能確實地確保導通的構造。
由以上，可提供不發生凸塊2與通孔7之連接部斷裂之問題，連接可靠性高之半導體封裝之安裝構造11。
再者，由於異向性導電材料8僅供給到通孔7內，將通孔7之開口部以熱固性黏著劑9被覆，因此於凸塊2壓接時即使有導電性粒子8a流到通孔7之外之情形，亦能藉被覆之熱固性黏著劑9，抑制導電性粒子8a流出到鄰接端子間發生短路之程度。由以上，習知之ACF接合或ACP接合成為問題之導電性粒子8a所致鄰接端子間之短路的問題不會發生，因此能提供能因應微細線路化之高密度化對應的半導體封裝之安裝構造11。
(產業上利用性)
就本發明之活用例而言，使用導電性粒子之覆晶晶片安裝得到的半導體封裝均能使用。
R1‧‧‧凸塊徑
R2‧‧‧通孔徑
H‧‧‧凸塊高度
D‧‧‧通孔深度
1‧‧‧半導體晶片
1a‧‧‧電極接墊
2‧‧‧凸塊
2a‧‧‧底部
2b‧‧‧側面部
2c‧‧‧肩部
3‧‧‧印刷線路板
3a‧‧‧安裝面
3b‧‧‧相反側面
4‧‧‧接合區
5‧‧‧球形端子
6a‧‧‧線路圖案(線路)
6b‧‧‧線路圖案(線路)
7‧‧‧通孔
7a‧‧‧通孔接合區
7b‧‧‧導體部
7c‧‧‧貫通孔
8‧‧‧異向性導電材料
8a‧‧‧導電性粒子
8b‧‧‧絕緣樹脂
9‧‧‧熱固性黏著劑
10‧‧‧覆晶晶片安裝構造
11‧‧‧半導體封裝之安裝構造
圖1顯示本發明實施形態半導體封裝之剖面圖。
圖2(A)~(C)，顯示本發明實施形態之凸塊與通孔之連接部分之1接腳分量的擴大剖面圖。
圖3顯示本發明實施形態之凸塊形成步驟之剖面圖。
圖4顯示本發明實施形態之樹脂供給步驟之剖面圖。
圖5顯示本發明實施形態之樹脂供給步驟之剖面圖。
圖6顯示本發明實施形態之樹脂供給步驟之剖面圖。
圖7顯示本發明實施形態之凸塊連接步驟之剖面圖。
圖8顯示本發明實施形態之凸塊連接步驟之剖面圖。
圖9顯示習知覆晶晶片安裝構造之剖面圖。
R1‧‧‧凸塊徑
R2‧‧‧通孔徑
H‧‧‧凸塊高度
D‧‧‧通孔深度
1‧‧‧半導體晶片
2‧‧‧凸塊
3‧‧‧印刷線路板
3a‧‧‧安裝面
3b‧‧‧相反側面
5‧‧‧球形端子
6a‧‧‧線路圖案
6b‧‧‧線路圖案
7‧‧‧通孔
7a‧‧‧通孔接合區
7b‧‧‧導體部
7c‧‧‧貫通孔
8‧‧‧異向性導電材料
8a‧‧‧導電性粒子
8b‧‧‧絕緣樹脂
9‧‧‧熱固性黏著劑
11‧‧‧半導體封裝之安裝構造

Claims (20)

  1. 一種半導體元件，包含：印刷線路板，具有將該印刷線路板的安裝面與相反側面貫通的通孔，該相反側面係相對於該印刷線路板之該安裝面的相反側；通孔接合區，形成在該印刷線路板之該相反側面而覆蓋該通孔的開口部；以及半導體晶片，具有用以安裝在該安裝面上的凸塊，其中該凸塊係插入至該通孔中，且線膨脹係數落於該半導體晶片與該印刷線路板的線膨脹係數之間的材料係充填於垂直方向上該凸塊的最底端與該通孔接合區之間的間隙中。
  2. 如申請專利範圍第1項之半導體元件，其中該凸塊之直徑小於該通孔之直徑。
  3. 如申請專利範圍第1項之半導體元件，其中該凸塊之高度大於該通孔之深度。
  4. 如申請專利範圍第1項之半導體元件，更包含和該材料混合之導電性粒子。
  5. 如申請專利範圍第4項之半導體元件，其中該導電性粒子將該凸塊的最底端和該通孔接合區導通。
  6. 如申請專利範圍第4項之半導體元件，其中該通孔包含和該通孔接合區導通之導體部，以及其中該導體部和該凸塊之側面部藉由該導電性粒子導通。
  7. 如申請專利範圍第4項之半導體元件，其中混合有該導電性粒子之該材料係選自於異向性導電膜與異向性導電糊漿所組成之群組。
  8. 如申請專利範圍第4項之半導體元件，其中該導電性粒子係選自於鎳、鍍金鎳、以及包含苯乙烯或壓克力作為樹脂核的鍍金樹脂核所組成之群組。
  9. 如申請專利範圍第1項之半導體元件，其中該材料包含選自於合成橡膠與熱固性樹脂所組成之群組 的絕緣樹脂。
  10. 如申請專利範圍第9項之半導體元件，其中該絕緣樹脂的線膨脹係數落在5~30ppm/℃之範圍中。
  11. 如申請專利範圍第1項之半導體元件，其中該材料係充填於該凸塊與該通孔之間的間隙中。
  12. 如申請專利範圍第1項之半導體元件，其中該凸塊係與該通孔導通，且該通孔係和該相反側面上的該通孔接合區導通，以及其中提供一導通路徑自該安裝面上的第一線路圖案通過該通孔與該通孔接合區而到達該相反側面上的第二線路圖案。
  13. 如申請專利範圍第4項之半導體元件，其中在該半導體晶片與該印刷線路板之間至少藉由該通孔、通孔接合區、與導電性粒子而在該印刷線路板的該安裝面與該相反側面之二者上提供一導通路徑。
  14. 如申請專利範圍第4項之半導體元件，其中該導電性粒子係僅充填於該通孔內部且由包含熱固性黏著劑之該材料披覆，以及其中在該相反側面上，該通孔接合區係形成以封閉該通孔的貫穿孔並和該相反側面上的線路圖案形成為一體。
  15. 如申請專利範圍第4項之半導體元件，其中該導電性粒子的粒徑小於該半導體晶片與該印刷線路板之間的間隙。
  16. 如申請專利範圍第4項之半導體元件，其中包含異向性導電材料的該材料中所含之導電性粒子的含量百分比落在5~15vol.%之範圍中，以及其中該凸塊具有較上方肩部窄而面向該通孔接合區的底部。
  17. 一種半導體元件，包含：基板，具有形成在該基板之安裝面上的孔洞；接合區，形成在該孔洞的底部；以及 半導體晶片，具有用以安裝在該安裝面上的凸塊，其中該凸塊係插入至該孔洞中，且一材料係充填於垂直方向上該凸塊的最底端與該接合區之間的間隙中。
  18. 如申請專利範圍第17之半導體元件，其中該材料包含絕緣材料。
  19. 如申請專利範圍第18之半導體元件，更包含和該材料混合之導電性粒子。
  20. 如申請專利範圍第19之半導體元件，其中該導電性粒子將該凸塊和該接合區導通。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4917979B2 (ja) * 2007-07-09 2012-04-18 半導体特許株式会社 半導体装置及びその製造方法
JP2011014680A (ja) * 2009-07-01 2011-01-20 Casio Computer Co Ltd 半導体装置の製造方法
US20120286416A1 (en) * 2011-05-11 2012-11-15 Tessera Research Llc Semiconductor chip package assembly and method for making same
JP6044258B2 (ja) * 2012-10-19 2016-12-14 コニカミノルタ株式会社 インクジェットヘッド
KR101557841B1 (ko) * 2012-12-07 2015-10-06 제일모직주식회사 이방 전도성 필름
WO2014182239A1 (en) * 2013-05-07 2014-11-13 Smartflex Technology Pte Ltd Ultra-thin smart card modules with chip bumps disposed in susbtrate via holes and methods of fabricating the same
US20150187681A1 (en) * 2013-12-26 2015-07-02 Ravi V. Mahajan Flexible microelectronic assembly and method
KR102199991B1 (ko) * 2014-05-28 2021-01-11 엘지이노텍 주식회사 발광 소자 및 이를 구비한 라이트 유닛
KR102268385B1 (ko) * 2014-08-14 2021-06-23 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
JP6390404B2 (ja) * 2014-12-15 2018-09-19 富士通株式会社 電子装置及び電子装置の製造方法
US9559075B1 (en) * 2016-01-06 2017-01-31 Amkor Technology, Inc. Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof
JP6702019B2 (ja) * 2016-06-22 2020-05-27 株式会社ジェイテクト 半導体装置
KR102432216B1 (ko) * 2017-07-11 2022-08-12 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자 패키지
KR102393035B1 (ko) * 2017-09-01 2022-05-02 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자 패키지
US10741482B2 (en) 2017-12-29 2020-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package
DE102018104279A1 (de) * 2018-02-26 2019-08-29 Tdk Electronics Ag Elektronische Vorrichtung

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661419A (ja) * 1992-08-06 1994-03-04 Hitachi Ltd 電子部品及びその接続方法
US5742100A (en) * 1995-03-27 1998-04-21 Motorola, Inc. Structure having flip-chip connected substrates
EP1005082A4 (en) * 1998-03-27 2001-08-16 Seiko Epson Corp SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, PRINTED CIRCUIT BOARD, AND ELECTRONIC APPARATUS
JP3183272B2 (ja) * 1998-09-17 2001-07-09 日本電気株式会社 半導体装置およびその製造方法
US6046909A (en) * 1998-11-16 2000-04-04 Intel Corporation Computer card with a printed circuit board with vias providing strength to the printed circuit board
JP3880762B2 (ja) * 1999-01-18 2007-02-14 株式会社東芝 半導体装置
JP2000232130A (ja) * 1999-02-09 2000-08-22 Toshiba Corp 半導体チップの実装方法
JP2003152023A (ja) * 1999-03-23 2003-05-23 Citizen Watch Co Ltd 半導体装置の接続構造とその製造方法
US6492738B2 (en) * 1999-09-02 2002-12-10 Micron Technology, Inc. Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
JP3994262B2 (ja) * 1999-10-04 2007-10-17 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP2001257453A (ja) * 2000-03-09 2001-09-21 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
US6518514B2 (en) * 2000-08-21 2003-02-11 Matsushita Electric Industrial Co., Ltd. Circuit board and production of the same
WO2003007370A1 (en) * 2001-07-12 2003-01-23 Hitachi, Ltd. Wiring glass substrate and method of manufacturing the wiring glass substrate, conductive paste and semiconductor module used for wiring glass substrate, and method of forming wiring substrate and conductor
JP2005032989A (ja) * 2003-07-14 2005-02-03 Matsushita Electric Ind Co Ltd 半導体装置の接続方法
JP2006019636A (ja) * 2004-07-05 2006-01-19 Renesas Technology Corp 半導体装置
JP4766943B2 (ja) * 2005-07-27 2011-09-07 旭化成イーマテリアルズ株式会社 回路接着シートとその製造方法、及び、微細接続構造体とその接続方法
US20070045812A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
JP4224056B2 (ja) * 2005-12-22 2009-02-12 株式会社東芝 基板検査方法、プリント配線板および電子回路装置
JP2007305799A (ja) * 2006-05-11 2007-11-22 Fujitsu Ltd 半導体装置の製造方法

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