TWI420590B - 積體電路結構與其形成方法 - Google Patents

積體電路結構與其形成方法 Download PDF

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TWI420590B
TWI420590B TW099109037A TW99109037A TWI420590B TW I420590 B TWI420590 B TW I420590B TW 099109037 A TW099109037 A TW 099109037A TW 99109037 A TW99109037 A TW 99109037A TW I420590 B TWI420590 B TW I420590B
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hard mask
semiconductor substrate
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integrated circuit
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Hung Pin Chang
Wen Chih Chiou
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Description

積體電路結構與其形成方法
本發明係關於半導體元件之製造方法，更特別關於通孔結構及形成其之通孔蝕刻製程。
積體電路之操作速度一般受晶片上相隔最遠且相連的組件之間的距離影響。因為層間的垂直距離遠小於單層的晶片寬度，三維結構之電路設計可明顯減少晶片上組件的連接距離。如此一來，垂直堆疊晶片可增加整體晶片速度。用以形成堆疊的方法之一為晶片接合，係接合含有積體電路於其上的兩個或多個半導體晶圓。上述晶圓的接合方式一般為直接接合其外層氧化層，或施加黏著劑至層間介電層。之後將接合的晶圓堆疊進行切割製程以形成獨立的晶粒堆疊，且每一晶粒堆疊均具有多層的積體電路。晶圓堆疊除了可增加三維電路的速度外，還有其他優點如改善參數、降低成本、並增加晶片系統(SoC)之積體程度。為了將不同組件整合至晶粒堆疊，需在垂直的層狀結構之間形成導體以電性連接組件。
常見於半導體製程之通孔，可提供半導體元件中一或多層之導電材料之間的電性耦合。近來發展之穿透矽通孔(TSV)可克服習知晶圓接合的限制，特別是在需要較佳性能及較高密度等不適於採用習知晶圓接合製程的元件中。TSV可在Z軸方向形成內連線，因此縮短了內連線的長度。藉由自基板正面延伸至基板背面的通孔，可形成穿透晶圓或基板的內連線。TSV亦可應用於晶圓堆疊之內連線、晶粒堆疊、及/或上述之組合。
然而TSV技術仍有部份問題待克服。一般來說，通孔的深寬比過高(基板厚度或通孔深度遠高於通孔直徑)。形成通孔的習知方法可能會形成不良的底切於半導體的層狀結構中，比如形成於介電硬遮罩與矽層之間。部份研究採用虛置有機層於硬遮罩開口的垂直側壁上，保護介電硬遮罩不受後續通孔蝕刻製程的水平蝕刻影響，可消除矽底切輪廓。但上述預防措施將導致與通孔填充製程有關的新問題。舉例來說，虛置有機層可能會在矽邊緣造成矽鳥嘴輪廓，並粗糙化側壁如形成扇貝狀圖案於通孔的側壁頂部。這會降低後續材料於通孔側壁之覆蓋性，不適於沉積晶種層、阻障層、及/或保護層。上述方法亦會減慢通孔填充製程的速度。此外，側壁的扇背狀粗糙度亦會影響TSV的性能。
綜上所述，目前亟需改良的通孔結構及其形成方法，以避免習知技藝的缺點。
本發明提供一種積體電路結構的形成方法，包括提供半導體基板；形成硬遮罩層於半導體基板上；形成光阻層於硬遮罩層上；圖案化光阻層以形成第一開口；圖案化硬遮罩層以形成第二開口於第一開口下，並露出部份半導體基板；蝕刻露出之部份半導體基板以形成通孔，通孔穿過至少部份半導體基板；進行修邊製程以圓滑化通孔之頂角；以及移除光阻層。
本發明更提供一種積體電路結構，包括：半導體基板；硬遮罩層形成於半導體基板上；至少導電層形成於硬遮罩層中；以及通孔自硬遮罩層延伸到至少部份半導體基板，其中通孔具有圓滑角及上寬下窄的側壁。
本發明係關於通孔蝕刻製程，可應用在形成開口於半導體基板中的任何製程。本發明更特別關於通孔結構與形成其之通孔蝕刻製程，可應用於具有垂直內連線的堆疊晶圓/晶粒的穿透矽通孔製程(如穿透矽通孔製程或穿透晶圓通孔製程)。通孔蝕刻製程可實施於生產線前端(FEOL)元件之製程後，與內連線結構之製程前。通孔蝕刻製程亦可實施於生產線前端元件之製程後，與內連線結構之製程後。然而可以理解的是，特定實施例僅用以教示本發明之概念，本技藝人士自可將本發明之教示應用於其他方法或元件。此外可以理解的是，本發明討論之方法及設備包含某些習知結構及/或製程。由於該些結構與製程已熟知於本領域，本發明僅就一般層級進行討論。本發明在圖示中延用相同標號以有利說明，該些重複並非限定圖示中標示的結構或步驟必然相同。此外，說明書中關於第一結構位於二結構上、第一結構鄰接第二結構、或第一結構連接至第一結構等敘述，包含直接接觸，或有其他結構夾設於第一結構與第二結構之間使兩者非直接接觸。形成結構於基板上如蝕刻基板等形成於基板表面上的方法，包括直接形成於基板表面上，及/或延伸至基板表面下(如通孔)。基板可包含半導體晶圓，以及一或多層形成於晶圓上。通孔在本發明之定義為基板上一或多個導電層(如金屬內連線層，或接觸墊如接合墊)的連接、導電層(如金屬內連線層)與半導體層(如矽特徵)之間的連接、及/或其他形成於基板上或連接至基板的元件之間的連接。通孔可填入導電材料、絕緣材料、及/或本領域的其他材料。通孔可形成於基板上，如形成於基板上的一或多層(如介電層、金屬層、半導體層、及/或本領域的其他材料)之中。
第1-6圖係本發明一實施例之通孔蝕刻製程剖視圖，第7圖係第1-6圖之步驟的流程圖。
在步驟200中，提供半導體基板10。第1圖顯示半導體基板10之剖視圖。半導體基板10一般為矽(Si)，但亦可為砷化鎵(GaAs)、磷砷化鎵(GaAsP)、磷化銦(InP)、砷化鎵鋁(GaAlAs)、磷化銦鎵(GaInP)、或類似物。對半導體基板10進行製程以形成元件100。舉例來說，元件100係包含閘極、源極、與汲極之電晶體。沉積於基板10上的接觸孔蝕刻停止層12與層間介電層14將作為硬遮罩層15，可用以形成下述之穿透矽通孔。硬遮罩層可包含氧化物如氧化矽、氮化物如氮化矽Si3 N4 、碳化矽、氮氧化矽、及/或其他合適的介電材料。硬遮罩層之形成方法包含化學氣相沉積法(CVD)、物理氣相沉積法(PVD)、原子層沉積法(ALD)、及/或其他製程。在一實施例中，接觸孔蝕刻停止層12為氮化矽層，而層間介電層14係磷掺雜矽酸鹽玻璃(PSG)層。在圖案化接觸孔蝕刻停止層12與層間介電層14形成接觸孔開口後，將接觸結構16形成於接觸孔開口中，以提供電性接觸至元件100。填入接觸孔開口之導電材料可包含多種材料如銅、鎢、鋁、鈦、多晶矽、或類似物。接著將層間介電層14上多餘的導電材料移除，移除方法可為蝕刻法、化學機械研磨法、或類似方法。
接著進行步驟210，旋轉塗佈光阻層18於硬遮罩層15上。之後以曝光、烘烤、顯影、及/或其他微影製程圖案化光阻層18，形成開口18a並露出部份硬遮罩層15。如第2圖所示，接著進行步驟220，以圖案化之光阻層作為遮罩進行濕蝕刻或乾蝕刻製程，蝕刻露出之硬遮罩層15以形成開口15a。在一實施例中，硬遮罩層之開口15a的蝕刻法為反應性離子蝕刻(RIE)。含有開口18a之光阻層18與含有開口15a之硬遮罩層15，將作為後續蝕刻製程之遮罩以形成穿透矽通孔。
如第3圖所示，進行步驟230以蝕刻通孔於半導體基板10中。以含有開口18a之光阻層18與含有開口15a之硬遮罩層15作為遮罩單元進行蝕刻，形成穿透矽通孔20(如開口或孔洞)穿過至少部份的半導體基板10。上述形成穿透矽通孔20之蝕刻步驟包含任何合適蝕刻方法，例如電漿蝕刻、化學濕式蝕刻、雷射鑽孔、及/或其他製程。在一實施例中，蝕刻製程包含深RIE製程以蝕刻半導體基板10。蝕刻製程可由基板正面(如電路端)蝕刻至基板背面(如非電路端)。在一實施例中，通孔深度介於幾十微米至幾百微米。上述蝕刻製程會讓穿透矽通孔20具有垂直或上寬下窄(tapered)的側壁輪廓。
為了避免通孔蝕刻製程形成矽底切22於穿透矽通孔20之頂角，將進行步驟240之修邊製程(trimming process)，使通孔角圓滑化及通孔側壁的粗糙度光滑化。如此一來可避免扇貝狀(scallop)圖案形成於通孔側壁。此修邊製程將形成具有上寬下窄之側壁輪廓的穿透基板通孔20”，如第4圖所示。上述修邊製程可為任何合適蝕刻方法如電漿乾蝕刻、化學濕式蝕刻、或其他製程。舉例來說，修邊製程係操作於乾蝕刻元件中，其採用之混合氣體包括下列一或多者：氦氣(He)、氬氣(Ar)、氧氣(O2 )、氫氟為主的氣體、三氟化氮(NF3 )、或六氟化硫(SF6 )。上述製程之壓力介於5至200毫托(mTorr)，其射頻偏壓功率介於100瓦至2500瓦之間。在修邊製程完成後，將進行步驟250如灰化光阻層。此步驟將光阻層18自半導體基板10剝除，保留具有光滑角24之穿透基板通孔20”，如第5圖所示。接著可視情況進一步清除任何位於半導體基板10上方的殘留物，清除方式係採用酸性或鹼性溶液之濕式清潔製程。
在通孔蝕刻製程後進行上述的底切修邊製程，可消除矽底切輪廓、矽鳥嘴結構、以及側壁的扇貝圖案。上述修邊製程還可光滑化通孔側壁與圓滑化通孔頂角，可改善後續沉積製程在通孔側壁之覆蓋性。後續沉積製程包含形成晶種層、阻障層、及/或保護層。上述製程係有利於通孔填充製程，並提高穿透基板通孔20”的性能。
如第6圖所示，接著進行步驟260塗佈及/或填充絕緣層26及/或導電材料28，於上述具有上寬下窄之側壁輪廓與光滑頂角的穿透基板通孔20”中。絕緣層26可包含氧化矽(SiO2 )、氮化矽(Si3 N4 )、及/或其他合適之介電材料。絕緣材料使形成於通孔中的導電材料與一或多種結構電性絕緣。絕緣層之形成方法可為成長法如熱氧化法，或沉積法如CVD。接著將導電材料28填入通孔，以提供電性耦合至一或多個內連線，而該些內連線又再耦合至一或多個位於基板上的元件結構。在一實施例中，可先形成晶種層如銅。在一實施例中，可形成一或多層黏著促進層。在一實施例中，可形成擴散阻障層如氮化鉭於穿透矽通孔20中。上述通孔可填入導電材料如銅、鋁、鎢、鉭、鈦、鎳、鈷、一或多種金屬矽化物、一或多種金屬氮化物、多晶矽、及/或其他合適材料。在一實施例中，將導電材料填入通孔的方法為電鍍製程。在其他實施例中，將導電材料填入通孔的方法包括濺鍍、PVD、CVD、及/或其他沉積製程。在上述製程後，可繼續進行其他製程如化學機械研磨、晶圓薄化、形成內連線之進一步金屬化製程、及/或其他製程。
第8-13圖係本發明另一實施例之通孔蝕刻製程剖視圖，其流程亦依據第7圖。在後續說明中，將省略與第1-6圖重疊之部份。
在步驟200中，首先提供具有生產線前端(FEOL)結構與生產線後端(BEOL)結構之基板。如第8圖所示，半導體基板10含有內連線結構30(如內連線層)，其包含複數個金屬層、複數個接觸通孔以耦合金屬層、以及金屬間介電層32分隔該些金屬物。半導體基板10更包含一或多個生產線前端結構如閘極結構、源極/汲極區、其他掺雜區、絕緣結構、閘極/源極/汲極之接觸物、記憶單元(如記憶晶胞)、及/或其他結構。一般來說，上述生產線前端結構係形成於半導體基板之正面。一或多個生產線前端結構將電性耦合至內連線結構30。內連線結構30可稱為生產線後端結構。可以理解的是，「前端」、「後端」、基板正面、與基板背面等相對用詞為任意選定的，其他適合的現有用詞可用以取代上述用詞。
內連線結構30包含四層金屬層，但金屬層的層數可為任意數目。在內連線結構30中，金屬層與通孔可包含導電材料如銅、鋁、鎢、鉭、鈦、鎳、鈷、一或多種金屬矽化物、一或多種金屬氮化物、多晶矽、金、銀、及/或其他導電材料，且可包含一或多層的抗腐蝕耐火層/襯墊。金屬層及/或通孔的形成方法可為CVD、PVD、ALD、電鍍、及/或其他製程。
金屬間介電層32與其下之介電層12及14組成硬遮罩層15”，係用以形成穿透矽通孔如下述。金屬間介電層32包含低介電常數。金屬間介電層32可減少內連線結構中的金屬線(如內連線路)之間的電容式耦合。金屬間介電層32可分隔金屬層。適於作為金屬間介電層32的其他材料包括四乙氧矽烷形成之氧化物、未掺雜之矽玻璃、掺雜之矽包璃如硼磷掺雜矽酸鹽玻璃(BPSG)、氟掺雜矽酸鹽玻璃(FSG)、磷掺雜矽酸鹽玻璃(PSG)、硼掺雜矽酸鹽玻璃(BSG)、SiLKTM (購自美國密西根州之密德蘭的Dow Chemical)、Black diamond(購自美國加州的Santa Clara公司)、或其他本技藝所知之絕緣材料。金屬間介電層32之形成方法包括CVD、ALD、PVD、旋轉塗佈法、及/或其他製程。
接著進行步驟210，將光阻層18旋轉塗佈於硬遮罩層15”上。接著進行曝光、烘烤、顯影、及/或其他微影製程圖案化光阻層18，形成開口18a於光阻層18中並露出部份硬遮罩層15”。如第9圖所示進行步驟220，以圖案化光阻層18作為遮罩，進行濕蝕刻或乾蝕刻製程以蝕刻露出之硬遮罩層15”，形成開口15”a。具有開口18a之光阻層18與具有開口15”a之硬遮罩層15”，可作為後續形成穿透矽通孔製程之蝕刻遮罩。
如第10圖所示，進行步驟230以蝕刻通孔於半導體基板10中。以硬遮罩層15”與光阻層18作為遮罩單元進行蝕刻，形成穿透矽通孔20(如開口或孔洞)穿過至少部份的半導體基板10。上述形成穿透矽通孔20之蝕刻步驟包含任何合適蝕刻方法，例如電漿蝕刻、化學濕式蝕刻、雷射鑽孔、及/或其他製程。在一實施例中，蝕刻製程包含深RIE製程以蝕刻半導體基板10。蝕刻製程可由基板正面(如電路端)蝕刻至基板背面(如非電路端)。在一實施例中，通孔深度介於幾十微米至幾百微米。上述蝕刻製程會讓穿透矽通孔20具有垂直或上寬下窄(tapered)的側壁輪廓。
為了避免通孔蝕刻製程形成矽底切22於穿透矽通孔20之頂角，將進行步驟240之修邊製程(trimming process)，使通孔角圓滑化及通孔側壁的粗糙度光滑化，如第11圖所示。如此一來可避免扇貝狀(scallop)圖案形成於通孔側壁。此修邊製程將形成具有上寬下窄之側壁輪廓的穿透基板通孔20”。上述修邊製程可為任何合適蝕刻方法如電漿乾蝕刻、化學濕式蝕刻、或其他製程。舉例來說，修邊製程係操作於乾蝕刻元件中，其採用之混合氣體包括下列一或多者：氦氣(He)、氬氣(Ar)、氧氣(O2 )、氫氟為主的氣體、三氟化氮(NF3 )、或六氟化硫(SF6 )。上述製程之壓力介於5至200毫托(mTorr)，其射頻偏壓功率介於100瓦至2500瓦之間。在修邊製程完成後，將進行步驟250如灰化光阻層。此步驟將光阻層18自半導體基板10剝除，保留具有光滑角24之穿透基板通孔20”，如第12圖所示。接著可視情況進一步清除任何位於半導體基板10上方的殘留物，清除方式係採用酸性或鹼性溶液之濕式清潔製程。
在通孔蝕刻製程後進行上述的底切修邊製程，可消除矽底切輪廓、矽鳥嘴結構、以及側壁的扇貝圖案。上述修邊製程還可光滑化通孔側壁與圓滑化通孔頂角，可改善後續沉積製程在通孔側壁之覆蓋性。後續沉積製程包含形成晶種層、阻障層、及/或保護層。上述製程係有利於通孔填充製程，並提高穿透基板通孔20”的性能。
如第13圖所示，接著進行步驟260塗佈及/或填充絕緣層26及/或導電材料28，於上述具有上寬下窄之側壁輪廓與光滑頂角的穿透基板通孔20”中。在上述製程後，可繼續進行其他製程如化學機械研磨、晶圓薄化、形成內連線之進一步金屬化製程、及/或其他製程。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．半導體基板
12．．．接觸孔蝕刻停止層
14．．．層間介電層
15、15”．．．硬遮罩層
15a、15”a、18a．．．開口
18．．．光阻層
20．．．穿透矽通孔
20”．．．穿透基板通孔
22．．．底切
24．．．光滑角
26．．．絕緣層
28．．．導電材料
30．．．內連線結構
32．．．金屬間介電層
100．．．元件
200、210、220、230、240、250、260．．．步驟
第1-6圖係本發明一實施例之通孔蝕刻製程剖視圖；
第7圖係本發明一實施例之通孔蝕刻製程流程圖；以及
第8-13圖係本發明另一實施例之通孔蝕刻製程剖視圖。
10．．．半導體基板
12．．．接觸孔蝕刻停止層
14．．．層間介電層
26．．．絕緣層
28．．．導電材料

Claims (13)

  1. 一種積體電路結構的形成方法，包括：提供一半導體基板；形成一硬遮罩層於該半導體基板上；形成一光阻層於該硬遮罩層上；圖案化該光阻層以形成一第一開口；圖案化該硬遮罩層以形成一第二開口於該第一開口下，並露出部份該半導體基板；蝕刻露出之部份該半導體基板以形成一通孔，該通孔穿過至少部份該半導體基板；進行一修邊製程以圓滑化該通孔之頂角；以及移除該光阻層。
  2. 如申請專利範圍第1項所述之積體電路結構通孔的形成方法，更包括：在形成該硬遮罩層於該半導體基板上之步驟前，形成一元件於該半導體基板上；以及在形成該硬遮罩層於該半導體基板上之步驟後，形成一接觸結構於該硬遮罩層上；其中該接觸結構電性電接至該元件。
  3. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中該硬遮罩層包括一蝕刻停止層與一介電層。
  4. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中該修邊製程降低該通孔側壁之粗糙度。
  5. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中該修邊製程使該通孔具有一上寬下窄之側壁輪廓。
  6. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中該修邊製程採用一混合氣體，且該混合氣體包括下列一或多者：氦氣、氬氣、氧氣、氫氟為主的氣體、三氟化氮、或六氟化硫。
  7. 如申請專利範圍第1項所述之積體電路結構的形成方法，更包括在移除該光阻層後，形成一導電層於該通孔中。
  8. 一種積體電路結構，包括：一半導體基板；一硬遮罩層形成於該半導體基板上；至少一導電層形成於該硬遮罩層中；以及一通孔自該硬遮罩層延伸到至少部份該半導體基板，其中該通孔具有一圓滑角及上寬下窄的側壁。
  9. 如申請專利範圍第8項所述之積體電路結構，其中該硬遮罩層包括：一蝕刻停止層形成於該半導體基板上；以及一第一介電層形成於該蝕刻停止層上；其中形成於該硬遮罩層中的導電層係一接觸結構。
  10. 如申請專利範圍第8項所述之積體電路結構，其中該硬遮罩層包括：一蝕刻停止層形成於該半導體基板上；一第一介電層形成於該蝕刻停止層上；以及一第二介電層形成於該第一介電層上；其中形成於該硬遮罩層中之該導電層係一內連線結構。
  11. 如申請專利範圍第8項所述之積體電路結構，其中該通孔填有一導電材料。
  12. 如申請專利範圍第8項所述之積體電路結構，其中該通孔填有銅。
  13. 如申請專利範圍第8項所述之積體電路結構，其中該蝕刻停止層包括氮化矽。
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