WO2013023456A1 - 同时制备垂直导通孔和第一层再布线层的方法 - Google Patents

同时制备垂直导通孔和第一层再布线层的方法 Download PDF

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WO2013023456A1
WO2013023456A1 PCT/CN2012/074279 CN2012074279W WO2013023456A1 WO 2013023456 A1 WO2013023456 A1 WO 2013023456A1 CN 2012074279 W CN2012074279 W CN 2012074279W WO 2013023456 A1 WO2013023456 A1 WO 2013023456A1
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layer
semiconductor substrate
conductive material
vertical via
etching
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French (fr)
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宋崇申
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中国科学院微电子研究所
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

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  • the present invention relates to the field of semiconductor fabrication, microelectronic packaging, and three-dimensional integration techniques, and more particularly to a method of simultaneously preparing vertical vias and first layer rewiring layers. Background technique
  • the vertical via hole is a conductive channel embedded in the inside of the semiconductor substrate, and the back end of the semiconductor substrate is exposed by thinning the semiconductor substrate to form an electrical connection through the semiconductor chip, and the signal is transmitted from one side of the semiconductor chip to the semiconductor chip.
  • chip stacking technology three-dimensional integration of multilayer semiconductor chips is realized.
  • the use of vertical via holes can effectively shorten the length of inter-chip interconnect lines, thereby improving the signal transmission performance and operating frequency of electronic systems, and is an important direction for the development of semiconductor technology in the future.
  • the vertical vias need to be used in combination with a Re-Distribution Layer (RDL), which optimizes the chip connection position.
  • RDL Re-Distribution Layer
  • the Belgian IMEC is in the literature [A. Jourdain, S. Stoukatch, P. De Moor, et al., "Simultanneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs", Proc. 2007 IEEE International Interconnects Technology Conference, pp. 207-209] and literature [G. Katti, A. Mercha, J. The technical solution proposed in Van Olmen, et al., "3D Stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding", Proc. 2009 IEEE International Electron Devices Meeting, pp.
  • 357-360 is: Active semiconductor lining After the device is fabricated on the bottom, deep hole etching, sidewall insulation, metal filling, and chemical mechanical polishing (CMP) processes are performed to obtain vertical via holes, and then the rewiring layer is processed. Finally, through the thinning, the vertical via holes are exposed from the back of the semiconductor substrate, and the electrical connection and mechanical connection with the underlying chip are realized by stack bonding technology. In this integrated mode, the vertical via fabrication and the first rewiring layer processing require a total of 2 photolithography, 2 metallization, and 2 chemical mechanical polishing steps.
  • CMP chemical mechanical polishing
  • the prior art has the following drawbacks: (1) Since the vertical via hole finally needs to penetrate the entire semiconductor chip substrate, its distribution and density are greatly limited, and generally the opening area is less than 5% of the entire chip area. In this case, after metal filling Chemical mechanical polishing, there is a large load effect problem, it is often difficult to obtain good uniformity, and the optimization process has great limitations;
  • the rewiring layer is processed, and the required process steps are often more. According to the two examples described above, the vertical via hole fabrication and the first layer rewiring layer are simply considered. Processing requires at least 2 lithography, 2 metallization, and at least 1 chemical mechanical polishing step, which corresponds to a higher process cost.
  • the invention solves the prior art solution that the chemical mechanical polishing process stops at the top of the vertical via hole, the process optimization is difficult, and the sidewall insulation layer of the vertical via hole is easily damaged; the vertical via hole fabrication and the first layer rewiring layer processing A method of simultaneously preparing a vertical via hole and a first layer rewiring layer is proposed, which requires many overall process steps and high process cost.
  • a method of simultaneously preparing a vertical via and a first layer rewiring layer comprising:
  • a conductive material filling process is performed to fill a hole or a groove structure on the semiconductor substrate with a conductive material; the semiconductor substrate is planarized to obtain a vertical via hole and a first layer re-wiring layer.
  • the semiconductor substrate material is silicon, germanium, germanium silicon or gallium arsenide.
  • the dielectric layer is one or a combination of silicon oxide, silicon nitride, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and organic polymer.
  • the method of fabricating the dielectric layer is one or more combinations of thermal oxidation, chemical vapor deposition (CVD), and spin coating baking.
  • the insulating layer deposited on the surface of the semiconductor substrate is one or a combination of silicon oxide, silicon nitride, and organic polymer.
  • the method of depositing an insulating layer on the surface of the semiconductor substrate is chemical vapor deposition
  • the conductive material used in the implementation of the conductive filling process is metallic copper.
  • the manner in which the conductive filling process is performed is electroplating.
  • FIG. 1 is a flowchart of a method for simultaneously preparing a vertical via hole and a first layer re-wiring layer according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of simultaneously preparing a vertical via hole and a first layer re-wiring layer according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of simultaneously preparing a vertical via hole and a first layer re-wiring layer according to an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a method of simultaneously preparing a vertical via hole and a first layer re-wiring layer after performing pattern etching on the semiconductor substrate not covered by the dielectric layer according to an embodiment of the present invention; Schematic;
  • FIG. 5 is a schematic cross-sectional view showing a method of simultaneously preparing a vertical via hole and a first layer re-wiring layer after depositing an insulating layer on a surface of the semiconductor substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional structural view of a method for simultaneously preparing a vertical via hole and a first layer re-wiring layer after performing a conductive material filling process according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of simultaneously preparing a vertical via hole and a first layer re-wiring layer according to an embodiment of the present invention.
  • the method for simultaneously preparing a vertical via hole and a first layer re-wiring layer includes the following steps:
  • Step 101 fabricating a dielectric layer on a surface of the semiconductor substrate
  • Step 102 Perform pattern etching on the dielectric layer
  • Step 103 Graphically pattern a semiconductor substrate that has been patterned to etch away the dielectric layer Etching to form a hole or groove structure on the semiconductor substrate;
  • Step 104 depositing an insulating layer on a surface of the semiconductor substrate
  • Step 105 Perform a conductive material filling process to fill a hole or a groove structure on the semiconductor substrate with a conductive material
  • Step 106 planarizing the semiconductor substrate while obtaining the vertical via and the first layer of the rewiring layer.
  • a method for simultaneously preparing a vertical via hole and a first layer re-wiring layer according to an embodiment of the present invention will be specifically described below with reference to FIGS. 2-7.
  • a dielectric layer 2 is formed on the surface of the semiconductor substrate 1.
  • the material of the semiconductor substrate may be silicon, germanium, germanium or gallium arsenide; the dielectric layer may be one of silicon oxide, silicon nitride, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, organic polymer or Various combinations; the method of forming the dielectric layer may be one or a combination of thermal oxidation, chemical vapor deposition (CVD), spin coating baking.
  • CVD chemical vapor deposition
  • silicon may be used as the semiconductor substrate material, and silicon oxide produced by a chemical vapor deposition process may be used as the dielectric layer material.
  • the dielectric layer 2 is patterned and etched.
  • the patterned etching can be selected by wet etching, dry etching or Reactive Ion Etching (RIE) of direct exposure and development of photosensitive materials to obtain better line definition.
  • the mask pattern used corresponds to the line pattern of the first layer of the rewiring layer, and more specifically, the dielectric layer 2 of the region where the first layer of the rewiring layer is to be formed is finally etched and removed.
  • the third step as shown in FIG. 4, the semiconductor lining that has been patterned to etch away the dielectric layer
  • the bottom region i.e., the dielectric layer 2 originally covered on the semiconductor substrate 1 is patterned and etched away
  • This etching is performed in a region not covered by the dielectric layer 2, and the semiconductor substrate 1 is directly etched. Since the etching is a single material, the etching can well control the shape of the etching profile, which is advantageous for the subsequent filling process.
  • the pattern of this etch is the same as the shape and distribution of the vertical via holes to be fabricated.
  • DRIE deep Reactive Ion Etching
  • an insulating layer 3 is deposited on the surface of the semiconductor substrate 1.
  • the insulating layer may be one or a combination of silicon oxide, silicon nitride, and organic polymer.
  • the method of depositing the insulating layer is preferably a chemical vapor deposition method to obtain continuous sidewall coverage of a high aspect ratio structure at a low temperature. After this step is completed, the insulating layer covers the hole or trench structure on the semiconductor substrate, and the dielectric layer 2, as shown in FIG.
  • a conductive material filling process is performed to fill the hole or groove structure on the semiconductor substrate with the conductive material 4.
  • the preferred conductive material is metallic copper.
  • the preferred filling method is electroplating.
  • the electroplating copper process is a relatively mature process, and a relatively good filling effect can be achieved in a structure having a relatively large depth and a wide structure.
  • a diffusion barrier layer and a plating seed layer are first formed on the surface of the insulating layer to block diffusion of copper ions to the insulating layer and provide a seed layer of the electroplating process.
  • the semiconductor substrate is planarized to obtain a vertical via and a first layer of rewiring.
  • the method for simultaneously preparing a vertical via hole and a first layer rewiring layer provided by the present invention is applied.
  • the chemical mechanical polishing process stops at the top of the first layer rewiring layer, and can be optimized by optimizing the distribution of the first layer rewiring layer.
  • the sidewall insulating layer of the vertical via hole is not damaged; on the other hand, the overall process steps required for the vertical via hole fabrication and the first layer rewiring layer processing can be reduced, and the process cost can be reduced.
  • the method provided by the present invention can reduce process steps, reduce process costs, and provide more freedom of process optimization to ensure the performance of the final product.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

一种同时制备垂直导通孔和第一层再布线层的方法,包括:在半导体衬底表面制作介质层(101);对所述介质层进行图形化刻蚀(102);对所述图形化刻蚀掉所述介质层而没有所述介质层覆盖区域的半导体衬底进行图形化刻蚀(103),以在所述半导体衬底上的形成孔或槽结构;在所述半导体衬底表面沉积绝缘层(104);实施导电材料填充工艺(105),使导电材料填充所述半导体衬底上的孔或槽结构;对所述半导体衬底进行平坦化处理,同时获得垂直导通孔和第一层再布线层(106)。该方法能够缩减工艺步骤、降低工艺成本,并提供工艺优化的更多自由度,保证最终产品的性能。

Description

同时制备垂直导通孔和第一层再布线层的方法 技术领域
本发明涉及半导体制造、 微电子封装和三维集成技术领域, 特别是涉及一 种同时制备垂直导通孔和第一层再布线层的方法。 背景技术
垂直导通孔是一种嵌入在半导体衬底内部的导电通道, 通过减薄半导体衬 底将其背端露出, 可以构成贯穿半导体芯片的电连接, 将信号从半导体芯片的 一面传导至半导体芯片的另一面, 并通过结合芯片堆叠技术, 实现多层半导体 芯片的三维集成。 与传统的引线键合技术相比, 使用垂直导通孔可以有效缩短 芯片间互连线的长度, 从而提高电子系统的信号传输性能和工作频率, 是未来 半导体技术发展的重要方向。 为了充分发挥垂直导通孔的互连自由度以及整个 半导体芯片的可靠性,垂直导通孔需要与再布线层( Re-Distribution Layer, RDL ) 结合使用, 再布线层实现芯片连接位置的优化。 从产业化角度来说, 如何降低 垂直导通孔与再布线层的总体制造成本, 并确保制造成品率, 对实现多个半导 体芯片的三维集成至关重要。
目前国际上存在多种工艺方案实现垂直导通孔和再布线层的加工, 一般来 说, 这些方案都是首先完成垂直导通孔的制造, 这包括深孔刻蚀、 侧壁绝缘、 导电材料填充、 表面平坦化等几个关键步骤, 在这些步骤完成之后再进行再布 线层的加工。 为详细说明这类加工方式, 下面介绍两个典型实例。
作为第一个典型实例, 比利时 IMEC在文献【 A. Jourdain, S. Stoukatch, P. De Moor, et al., "Simultanneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs", Proc. 2007 IEEE International Interconnects Technology Conference, pp. 207-209]和文献【G. Katti, A. Mercha, J. Van Olmen, et al., "3D Stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding", Proc. 2009 IEEE International Electron Devices Meeting, pp. 357-360】中提出的技术方案 为: 在有源半导体衬底上完成器件制造之后, 进行深孔刻蚀、 侧壁绝缘、 金属 填充及化学机械抛光(CMP ) 工艺, 获得垂直导通孔, 之后再进行再布线层的 加工。 最终通过减薄, 使垂直导通孔从半导体衬底背部露出, 并借助堆叠键合 技术, 实现与下层芯片的电学连接和机械连接。 在这一集成方式下, 垂直导通 孔制造及第一层再布线层加工共需 2次光刻, 2次金属化, 和 2次化学机械抛光 步骤。
作为第二个典型实例, 新加坡微电子研究院 ( Institute of Microelectronics, IME )在文献【V. S. Rao, H. S. Wee, Lee W. S. Vincent, et al., "TSV Interposer Fabrication for 3D IC Packaging", Proc. 2009 Electronics Packaging Technology Conference, pp. 431-437】提出的集成方案为: 在无源半导体衬底上首先进行深 孔刻蚀、 侧壁绝缘、 金属填充及化学机械抛光加工, 获得垂直导通孔, 然后再 进行再布线层的制造, 而且在制作第一层再布线层之前, 首先在化学机械抛光 之后的表面沉积一层氮化硅介质层, 经由微孔刻蚀及第二次金属化, 获得第一 层再布线层加工并实现其与垂直导通孔的连接。 在这一集成方式下, 垂直导通 孔制造及第一层再布线层加工共需 3次光刻, 2次金属化, 和至少 1次化学机械 抛光步骤。
现有技术存在如下几个缺陷: ( 1 ) 由于垂直导通孔最终需要穿透整个半导体芯片衬底, 其分布及密度存 在很大限制, 一般其开口面积不及整个芯片面积的 5%, 在这种情况下, 进行金 属填充后的化学机械抛光, 存在很大的负载效应问题, 往往难以获得很好的均 匀性, 而且优化过程存在很大限制;
( 2 )垂直导通孔填充后的化学机械抛光步骤需要停止于垂直导通孔顶端, 即垂直导通孔侧壁绝缘层顶部, 由于机械作用, 容易损伤侧壁绝缘层, 影响其 厚度和性能, 并影响最终产品的可靠性;
( 3 )完成垂直导通孔所有工艺之后再进行再布线层的加工, 所需工艺步骤 往往较多, 根据以上所述的两个实例, 单纯考虑垂直导通孔制造和第一层再布 线层加工, 至少需要 2次光刻, 2次金属化, 和至少 1次化学机械抛光步骤, 对 应工艺成本较高。
发明内容
本发明为了解决现有技术方案中化学机械抛光工艺停止于垂直导通孔顶 端, 工艺优化困难、 易损伤垂直导通孔侧壁绝缘层; 垂直导通孔制造和第一层 再布线层加工所需的整体工艺步骤多、 工艺成本高等问题, 提出一种同时制备 垂直导通孔和第一层再布线层的方法。
根据本发明的一个方面, 提供一种同时制备垂直导通孔和第一层再布线层 的方法, 包括:
在半导体衬底表面制作介质层;
对所述介质层进行图形化刻蚀; 蚀, 以在所述半导体衬底上的形成孔或槽结构;
在所述半导体衬底表面沉积绝缘层;
实施导电材料填充工艺, 使导电材料填充所述半导体衬底上的孔或槽结构; 对所述半导体衬底进行平坦化处理, 同时获得垂直导通孔和第一层再布线 层。
进一步地, 所述半导体衬底材料为硅、 锗、 锗硅或砷化镓。
进一步地, 所述介质层为氧化硅、 氮化硅、 硼硅玻璃、 磷硅玻璃、 硼磷硅 玻璃、 有机聚合物中的一种或多种组合。
进一步地, 所述制作介质层的方法为热氧化、 化学汽相沉积(CVD )、 旋涂 烘烤中的一种或多种组合。
进一步地, 所述在半导体衬底表面沉积的绝缘层为氧化硅、 氮化硅、 有机 聚合物中的一种或多种组合。
进一步地, 所述在半导体衬底表面沉积绝缘层的方法为化学汽相沉积
( CVD )。
进一步地, 所述实施导电填充工艺时所用的导电材料为金属铜。
进一步地, 所述实施导电填充工艺时所用的方式为电镀。
本发明提供的同时制备垂直导通孔和第一层再布线层的方法一方面化学机 械抛光工艺停止于第一层再布线层顶部, 可以通过优化第一层再布线层的分布 获得优化且不会损伤垂直导通孔的侧壁绝缘层; 另一方面可以减少垂直导通孔 制造和第一层再布线层加工所需的总体工艺步骤、 降低工艺成本。 附图说明 图 1 为本发明实施例提供的一种同时制备垂直导通孔和第一层再布线层的 方法的流程图;
图 2 为本发明实施例提供的一种同时制备垂直导通孔和第一层再布线层的 图 3 为本发明实施例提供的一种同时制备垂直导通孔和第一层再布线层的 方法在对所述介质层进行图形化刻蚀之后的剖面结构示意图;
图 4 为本发明实施例提供的一种同时制备垂直导通孔和第一层再布线层的 方法在对没有被所述介质层覆盖区域的所述半导体衬底进行图形化刻蚀之后的 剖面结构示意图;
图 5 为本发明实施例提供的一种同时制备垂直导通孔和第一层再布线层的 方法在所述半导体衬底表面沉积绝缘层之后的剖面结构示意图;
图 6 为本发明实施例提供的一种同时制备垂直导通孔和第一层再布线层的 方法在实施导电材料填充工艺之后的剖面结构示意图;
图 7 为本发明实施例提供的一种同时制备垂直导通孔和第一层再布线层的
具体实施方式
如图 1 所示, 本发明实施例提供的同时制备垂直导通孔和第一层再布线层 的方法包括以下步骤:
步骤 101、 在半导体衬底表面制作介质层;
步骤 102、 对介质层进行图形化刻蚀;
步骤 103、对已经被所述图形化刻蚀掉所述介质层的半导体衬底进行图形化 刻蚀, 以在所述半导体衬底上的形成孔或槽结构;
步骤 104、 在半导体衬底表面沉积绝缘层;
步骤 105、 实施导电材料填充工艺,使导电材料填充所述半导体衬底上的孔 或槽结构;
步骤 106、对半导体衬底进行平坦化处理, 同时获得垂直导通孔和第一层再 布线层。
下面结合图 2-图 7对本发明实施例提供的同时制备垂直导通孔和第一层再 布线层的方法进行具体说明。
第一步, 如图 2所示, 在半导体衬底 1表面制作介质层 2。
半导体衬底的材料可以是硅、 锗、 锗硅或砷化镓; 介质层可以是氧化硅、 氮化硅、 硼硅玻璃、 磷硅玻璃、 硼磷硅玻璃、 有机聚合物中的一种或多种组合; 制作介质层的方法可以是热氧化、 化学汽相沉积(CVD )、 旋涂烘烤中的一种或 多种组合。
作为一个具体实施例, 可以使用硅作为半导体衬底材料, 使用化学汽相沉 积工艺制作的氧化硅作为介质层材料。
第二步, 如图 3所示, 对介质层 2进行图形化刻蚀。
图形化刻蚀可以选择湿法腐蚀、 干法刻蚀或者光敏材料直接曝光显影的方 反应离子刻蚀( Reactive Ion Etching, RIE ) 的方式, 以获得更好的线条定义。 所 用掩膜图形对应第一层再布线层的线条图形, 更具体的, 最终要将需要制作第 一层再布线层的区域的介质层 2刻蚀去除干净。
第三步, 如图 4所示, 对已经被所述图形化刻蚀掉所述介质层的半导体衬 底的区域(即原来覆盖在半导体衬底 1上的介质层 2被图形化刻蚀掉)进行图 形化刻蚀, 以在半导体衬底 1上获得孔或槽结构。
本次刻蚀在没有介质层 2覆盖的区域进行, 直接刻蚀半导体衬底 1 , 由于是 单一材料刻蚀, 这种刻蚀可以艮好地控制刻蚀剖面形状, 有利于后续的填充工 艺。 本次刻蚀的图形与要制造的垂直导通孔的形状和分布相同。
更具体的, 在衬底材料是硅的情况下, 优选深反应离子刻蚀( Deep Reactive Ion Etching, DRIE ) 的方式, 这种方式可以获得深宽比较大的孔或槽结构, 有助 于获得陡直的垂直导通孔。
第四步, 如图 5所示, 在半导体衬底 1表面沉积绝缘层 3。
绝缘层可以是氧化硅、 氮化硅、 有机聚合物中的一种或多种组合。 沉积绝 缘层的方法优选化学汽相沉积的方法, 以在低温下获得高深宽比结构的侧壁连 续覆盖。 本步骤完成之后, 绝缘层覆盖半导体衬底上的孔或槽结构, 以及所述 介质层 2, 如图 5所示。
第五步, 如图 6所示, 实施导电材料填充工艺, 使导电材料 4填充半导体 衬底上的孔或槽结构。
优选的导电材料为金属铜, 优选的填充方式为电镀, 电镀铜工艺是一种比 较成熟的工艺, 可以在深宽比较大的结构中实现比较好的填充效果。 在电镀填 充工艺之前, 需要首先在所述绝缘层表面制作扩散阻挡层以及电镀种子层, 阻 挡铜离子向绝缘层扩散, 并提供电镀工艺的籽晶层。
第六步, 如图 7所示, 对半导体衬底进行平坦化处理, 同时获得垂直导通 孔和第一层再布线层。
平坦化处理使用化学机械抛光、 电化学抛光或电化学机械抛光的方式, 平 坦化操作将半导体衬底表面多余的导电材料 4去除, 最终在半导体衬底上的介 质层开口位置及深孔位置保留导电材料 4(分别对应在第一层再布线层和垂直导 通孔)。
应用本发明提供的同时制备垂直导通孔和第一层再布线层的方法, 一方面 化学机械抛光工艺停止于第一层再布线层顶部, 可以通过优化第一层再布线层 的分布获得优化且不会损伤垂直导通孔的侧壁绝缘层; 另一方面可以减少垂直 导通孔制造和第一层再布线层加工所需的总体工艺步骤、 降低工艺成本。 使用 本发明提供的方法能够缩减工艺步骤、 降低工艺成本, 并提供工艺优化的更多 自由度, 保证最终产品的性能。
以上所述的具体实施方式, 对本发明的目的、 技术方案和有益效果进行了 进一步详细说明, 所应理解的是, 以上所述仅为本发明的具体实施方式而已, 并不用于限制本发明, 凡在本发明的精神和原则之内, 所做的任何修改、 等同 替换、 改进等, 均应包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1、 一种同时制备垂直导通孔和第一层再布线层的方法, 包括:
在半导体衬底表面制作介质层;
对所述介质层进行图形化刻蚀; 蚀, 以在所述半导体衬底上的形成孔或槽结构;
在所述半导体衬底表面沉积绝缘层;
实施导电材料填充工艺, 使导电材料填充所述半导体衬底上的孔或槽结构; 对所述半导体衬底进行平坦化处理, 同时获得垂直导通孔和第一层再布线 层。
2、 根据权利要求 1所述的方法, 其特征在于:
所述半导体衬底材料为硅、 锗、 锗硅或砷化镓。
3、 根据权利要求 1所述的方法, 其特征在于:
所述介质层为氧化硅、 氮化硅、 硼硅玻璃、 磷硅玻璃、 硼磷硅玻璃、 有机 聚合物中的一种或多种组合。
4、 根据权利要求 1所述的方法, 其特征在于:
所述制作介质层的方法为热氧化、 化学汽相沉积、 旋涂烘烤中的一种或多 种组合。
5、 根据权利要求 1所述的方法, 其特征在于:
所述在半导体衬底表面沉积的绝缘层为氧化硅、 氮化硅、 有机聚合物中的 一种或多种组合。
6、 根据权利要求 1所述的方法, 其特征在于: 所述在半导体衬底表面沉积绝缘层的方法为化学汽相沉积。
7、 根据权利要求 1所述的方法, 其特征在于:
所述实施导电填充工艺时所用的导电材料为金属铜。
8、 根据权利要求 1所述的方法, 其特征在于:
所述实施导电填充工艺时所用的方式为电镀。
9、 根据权利要求 1-8任一项所述的方法, 其特征在于, 在所述实施导电材 料填充工艺之前还包括:
在所述绝缘层表面制作扩散阻挡层以及电镀种子层。
PCT/CN2012/074279 2011-08-15 2012-04-18 同时制备垂直导通孔和第一层再布线层的方法 WO2013023456A1 (zh)

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