TWI419331B - 金氧半導體場效電晶體及其製造方法 - Google Patents
金氧半導體場效電晶體及其製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 35
- 230000005669 field effect Effects 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title description 4
- 239000000463 material Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 22
- 230000007547 defect Effects 0.000 claims description 16
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 12
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 10
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本發明係有關於通道層含有例如InGaAs、InAs或InAsSb之III-V族半導體的金氧半導體場效電晶體。
本發明係有關於通道層含有例如InGaAs、InAs或InAsSb之III-V族半導體的金氧半導體場效電晶體(此後稱之為“III-V族MOSFET(III-V MOSFET)”或“薄體MOSFET(thin body MOSFET)”)。在習知技術中,一般當III-V族MOSFET是形成在GaAs基底上時,會使用銦(In)莫耳分率低(<30%)的InGaAs通道;而當形成在InP基底上時,則會使用銦莫耳分率高()的InGaAs通道。具有銦(In)含量較高之通道層的III-V族MOSFET也適合未來形成在矽基底上的CMOS應用。
在習知技術中,通道具有高的銦莫耳分率的MOSFET使用一般的離子摻雜法形成源極與汲極延伸區域以降低寄生電阻,如Y. Xuan等人在“High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET with Maximum Drain Current Exceeding 1A/mm,”Electron Device letters,Vol. 29,No. 4,p. 294(2008)中所述。0.5μm的裝置其最終的有效寄生串聯源極/汲極電阻(parasitic series source/drain resistance(Rsd
))約為2000Ωμm,且次臨界擺幅(subthreshold swing(S))為200mV/decade。習知技術更揭示無摻雜的III-V族MOSFET,其是使用極性與通道相反並形成在閘極氧化層表面上的電荷層,藉此降低源極/汲極延伸區域中的寄生電阻,如R. J. W. Hill等人在“1μm gate length,In0.75
Ga0.25
As channel,thin body n-MOSFET on InP substrate with transconductance of 73μS/μm,”Electronics Letter,Vol. 44,No. 7,pp. 498-500(2008),與美國專利公開號2008/0102607中所述。在此例子中,1μm的裝置其Rsd約為530Ωμm,且次臨界擺幅為1100mV/decade。習知技術也揭露使用從源極接觸延伸至汲極接觸的單一個氧化層,其同時在閘極下方與源極/汲極延伸區域中誘導出導電的表面通道,如N. Li等人在“Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2
O3
Dielectric,”Applied Physics Letters,Vol. 92,143507(2008)中所述。N. Li等人量測5μm的裝置得到Rsd
為52,500Ωμm,且次臨界擺幅為400mV/decade。而量測得的跨導(transconductance;gm
)非常小,為2.3μS/μm。
國際半導體技術藍圖(International Technology Roadmap for Semiconductors)顯示22奈米及更小尺寸世代的CMOS裝置需要符合、S<100mV/decade,且gm=3000-4000μS/μm的條件。然而,所有的習知技術並無法達到上述需求。
本發明提供一種金氧半導體場效電晶體,包括:一半導體基底;一通道層,設置在該基底的頂表面上;一閘極介電層,插入一閘電極與該通道層之間;以及介電延伸層,設置在該通道層的頂部上,並插入該閘電極與歐姆接觸之間;其中該閘極介電層包括一第一材料,該第一材料與該通道層的頂表面形成一低缺陷的界面;以及其中該介電延伸層包括一不同於該第一材料的第二材料,該第二材料與該通道層形成一導電表面通道。
本發明也提供一種薄體金氧半導體場效電晶體,包括:一半導體基底;一通道層,設置在該基底的頂表面上,該通道層包括一III-V族半導體;一間極介電層,插入一閘電極與該通道層之間,並沿著該通道層的前側與後側設置;以及介電延伸層,設置在通道層的頂部上,並插入該閘電極與歐姆接觸之間;其中該閘極介電層包括一第一材料,該第一材料沿著該通道層的頂表面、前側表面與後側表面而與該通道層形成一低缺陷的界面;以及其中該介電延伸層包括一不同於該第一材料的第二材料,該第二材料與該通道層形成一導電表面通道。
本發明還提供一種包括閘電極位於源極與汲極歐姆接觸之間的薄體金氧半導體場效電晶體的製造方法,包括:在一半導體基底的頂表面上提供一通道層;在該閘電極與該通道層之間提供一閘極介電層;以及提供介電延伸層,設置在該通道層的頂部上,並插入該閘電極與歐姆接觸之間;其中該閘極介電層包括第一材料,該第一材料與該通道層形成一低缺陷的界面;以及其中該介電延伸層包括一不同於該第一材料的第二材料,該第二材料與該通道層形成一導電表面通道。
以下是透過圖示說明本發明的概念。要強調的是,圖中的各種元件並未畫成與工業標準規範相符的比例。實際上,為了清楚地描述本發明,各種元件的尺寸可任意地放大或縮小。
在此所述的實施例提供III-V族MOSFET,其在導通狀態時具有低的寄生導通電阻(parasitic on-resistance;Rsd
)與高的跨導(transconductance;gm
),且在關閉狀態時具有低的次臨界擺幅(subthreshold swing;S)。本發明一實施例包括III-V族MOSFET,其同時具有只在源極/汲極延伸區域誘導的導電表面通道造成的低導通電阻;在閘極區域使用低界面缺陷的閘極氧化物所造成的高跨導;以及裝置在關閉狀態時由於空乏的通道側壁所造成的低次臨界擺幅。
第1A圖至第1C圖顯示各種典型的III-V族MOSFET。第1A圖顯示第一典型之III-V族MOSFET 100的剖面圖。III-V族MOSFET 100包括寬能隙半導體的基底層101,其上方設置有通道層102並具有離子摻雜延伸區域103。歐姆接觸104設置在部分的離子摻雜延伸區域103上。通道層102包括多數個III-V族半導體中的其中一個,例如InGaAs、InAs或InAsSb。
閘極氧化層106延伸在歐姆接觸104之間,且閘電極108與閘極側壁110設置在閘極氧化層106的上方。MOSFET 100更包括隔離區域112。化合物半導體中的施體摻雜質的活化效率一般很低,只有幾個百分比的等級,且活化施體的濃度是限制在接近5x1018
原子cm-3
(atom cm-3
)。舉例來說,對遷移率為2500cm2
/Vs的10nm的通道層來說,其片電阻高達500Ω/sq,此會造成過高的Rsd
。
第1B圖顯示第二典型的III-V族MOSFET 120的剖面圖。MOSFET 120包括寬能隙半導體的基底層122,其上方設置有通道層124。通道層124包括多數個III-V族半導體中的其中一個,例如InGaAs、InAs或InAsSb。
MOSFET 120包括單一個閘極氧化層126,延伸在源極與汲極歐姆接觸128之間。閘電極130與閘極側壁132設置在閘極氧化層126的上方。MOSFET 120更包括隔離區域133。若InGaAs通道層具有高的In莫耳分率,特別是InAs通道層具有高的In莫耳分率,而其表面被氧化或其終端具有高程度的缺陷時,會造成導電表面通道134。雖然位於閘電極130與歐姆接觸128之間的延伸區域136有可能達成低的電阻,然而由於閘極氧化層126與通道層124之間的界面138的高缺陷,閘電極130下方的電荷控制成為不可能,因而造成非常小的跨導。
第1A圖與第1B圖顯示MOSFET垂直於對應的閘電極的剖面圖。第1C圖則顯示MOSFET 120位於閘電極130下方且平行於閘電極130的剖面圖。請參考第1C圖,隔離區域133與通道層124的側壁之間會形成高缺陷的界面138,而在通道層124的側壁產生導電表面通道134。由於導電表面通道134是無法被空乏掉的導電層,因此MOSFET 120在關閉狀態時會造成高次臨界擺幅與高源極至汲極的漏電流(source-to-drain leakage current)。
第2圖顯示本發明一實施例的III-V族MOSFET 200垂直於閘極的剖面圖。如第2圖中所示,MOSFET 200包括寬能隙半導體的基底層202,其上方設置有通道層204。通道層204包括多數個III-V族半導體中的其中一個,例如InGaAs、InAs或InAsSb。
MOSFET 200包括閘極介電層206與延伸介電層207,延伸在源極與汲極歐姆接觸208之間。閘電極210設置於閘極介電層206的上方,且閘極側壁212設置在延伸介電層207的上方。MOSFET 200更包括隔離區域213。如先前所述,閘極介電層206包括適合的氧化物或其他絕緣材料,其在通道層204提供低缺陷的界面,而在閘極下方造成有效的電荷控制的區域,其如符號214所示。詳細地說,區域214會被閘極控制,且在裝置200關閉狀態時電荷載子能有效地被空乏掉。
延伸介電層207是設置於鄰接且自對準於閘電極210,以誘導出導電表面通道216,其能將延伸電阻(extension resistance)最小化。延伸介電層207包括適合的氧化物或其他絕緣材料,此材料可與通道層204產生高缺陷的界面,藉此在半導體表面或鄰近半導體表面的區域產生電荷累積層(charge accumulation layer)。延伸介電層207能藉由對通道層204的表面進行氧化而相對容易地形成。要注意延伸介電層207與通道層204產生的“高缺陷”的界面是相對於閘極介電層206與通道層204產生的“低缺陷”的界面作定義。
第3圖則顯示MOSFET 200位於閘電極210下方且平行於閘電極210的剖面圖。由於通道層204的側壁300與閘極介電層206形成低缺陷的界面,因此能有效地控制在側壁300的電荷。因此,包含側壁300的區域,會類似於上述區域214,被閘極控制且在裝置200的關閉狀態下,可有效地空乏掉電荷載子。
第4圖為MOSFET 200的上視圖,顯示隔離區域213相對於閘電極210及源極與汲極歐姆接觸208的位置。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟悉此項技藝者,在不脫離本發明之精神和範圍內,當可做些許更動與潤飾。舉例來說,所述方法的各種步驟可以不同的順序或連續地執行,或與其他步驟合併、更分割成其他步驟或以其他步驟取代,或全部移除。另外,在說明書中的方法或其他部分所述的各種功能,可合併提供額外及/或其他的功能。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100...MOSFET
101...基底層
102...通道層
103...離子摻雜延伸區域
104...歐姆接觸
106...閘極氧化層
108...閘電極
110...閘極側壁
112...隔離區域
120...MOSFET
122...基底層
124...通道層
126...閘極氧化層
128...源極與汲極歐姆接觸
130...閘電極
132...閘極側壁
133...隔離區域
134...導電的表面通道
136...延伸區域
138...界面
200...MOSFET
202...基底層
204...通道層
206...閘極介電層
207‧‧‧延伸介電層
208‧‧‧源極與汲極歐姆接觸
210‧‧‧閘電極
212‧‧‧閘極側壁
213‧‧‧隔離區域
214‧‧‧區域
216‧‧‧導電表面通道
300‧‧‧側壁
第1A圖至第1C圖顯示各種典型的III-V族MOSFET。
第2圖為本發明一實施例的III-V族MOSFET垂直於閘極的剖面圖,III-V族MOSFET包括導電表面通道延伸區域與閘極控制的通道側壁。
第3圖為第2圖MOSFET位於閘電極210下方且平行於閘電極的剖面圖。
第4圖為MOSFET的上視圖。
200...MOSFET
202...基底層
204...通道層
206...閘極介電層
207...延伸介電層
208...源極與汲極歐姆接觸
210...閘電極
212...閘極側壁
213...隔離區域
214...區域
216...導電表面通道
Claims (20)
- 一種金氧半導體場效電晶體(MOSFET),包括:一半導體基底;一通道層,設置在該基底的頂表面上;一閘極介電層,插入一閘電極與該通道層之間;以及介電延伸層,設置在該通道層的頂部上,並插入該閘電極與歐姆接觸之間;其中該閘極介電層包括一第一材料,該第一材料與該通道層的頂表面形成一第一界面;以及其中該介電延伸層包括一不同於該第一材料的第二材料,該第二材料與該通道層形成一導電表面通道,該介電延伸層與該通道層的頂表面形成一第二界面,且該第一界面之缺陷低於該第二界面之缺陷。
- 如申請專利範圍第1項所述的金氧半導體場效電晶體,其中該通道層包括一III-V族半導體。
- 如申請專利範圍第2項所述的金氧半導體場效電晶體,其中該通道層包括InGaAs、InAs與InAsSb中的其中一個。
- 如申請專利範圍第1項所述的金氧半導體場效電晶體,其中該基底包括一寬能隙半導體材料。
- 如申請專利範圍第1項所述的金氧半導體場效電晶體,其中該介電延伸層是藉由氧化該半導體基底的表面形成。
- 如申請專利範圍第1項所述的金氧半導體場效電 晶體,其中該閘極介電層包括一氧化物。
- 如申請專利範圍第1項所述的金氧半導體場效電晶體,更包括一隔離區域,沿著該半導體基底的邊緣設置。
- 一種薄體金氧半導體場效電晶體(thin-body MOSFET),包括:一半導體基底;一通道層,設置在該基底的頂表面上,該通道層包括一III-V族半導體;一閘極介電層,插入一閘電極與該通道層之間,並沿著該通道層的前側與後側設置;以及介電延伸層,設置在通道層的頂部上,並插入該閘電極與歐姆接觸之間;其中該閘極介電層包括一第一材料,該第一材料沿著該通道層的頂表面、前側表面與後側表面而與該通道層形成一低缺陷的界面;以及其中該介電延伸層包括一不同於該第一材料的第二材料,該第二材料與該通道層形成一導電表面通道。
- 如申請專利範圍第8項所述的薄體金氧半導體場效電晶體,其中該通道層包括一III-V族半導體。
- 如申請專利範圍第8項所述的薄體金氧半導體場效電晶體,其中該通道層包括InGaAs、InAs與InAsSb中的其中一個。
- 如申請專利範圍第8項所述的薄體金氧半導體場效電晶體,其中該基底包括一寬能隙半導體材料。
- 如申請專利範圍第8項所述的薄體金氧半導體場效電晶體,其中該介電延伸層是藉由氧化該半導體基底的表面形成。
- 如申請專利範圍第8項所述的薄體金氧半導體場效電晶體,其中該閘極介電層包括一氧化物。
- 如申請專利範圍第8項所述的薄體金氧半導體場效電晶體,更包括一隔離區域,沿著該半導體基底的邊緣設置。
- 一種包括閘電極位於源極與汲極歐姆接觸之間的薄體金氧半導體場效電晶體的製造方法,包括:在一半導體基底的頂表面上提供一通道層;在該閘電極與該通道層之間提供一閘極介電層;以及提供介電延伸層,設置在該通道層的頂部上,並插入該閘電極與歐姆接觸之間;其中該閘極介電層包括第一材料,該第一材料與該通道層形成一第一界面;以及其中該介電延伸層包括一不同於該第一材料的第二材料,該第二材料與該通道層形成一導電表面通道,該介電延伸層與該通道層的頂表面形成一第二界面,且該第一界面之缺陷低於該第二界面之缺陷。
- 如申請專利範圍第15項所述的薄體金氧半導體場效電晶體的製造方法,其中該通道層包括一III-V族半導體。
- 如申請專利範圍第15項所述的薄體金氧半導體 場效電晶體的製造方法,其中該通道層包括InGaAs、InAs與InAsSb中的其中一個。
- 如申請專利範圍第15項所述的薄體金氧半導體場效電晶體的製造方法,其中該基底包括一寬能隙半導體材料。
- 如申請專利範圍第15項所述的薄體金氧半導體場效電晶體的製造方法,其中該介電延伸層是藉由氧化該半導體基底的表面形成。
- 如申請專利範圍第15項所述的薄體金氧半導體場效電晶體的製造方法,其中該閘極介電層包括一氧化物。
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CN106568548A (zh) * | 2016-10-27 | 2017-04-19 | 北京遥测技术研究所 | 基于soi‑mems技术的电容式绝压微压气压传感器 |
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EP2299480A2 (en) | 2011-03-23 |
US20110068348A1 (en) | 2011-03-24 |
CN102024850A (zh) | 2011-04-20 |
JP2011066415A (ja) | 2011-03-31 |
KR101145991B1 (ko) | 2012-05-15 |
CN102024850B (zh) | 2012-11-14 |
TW201112420A (en) | 2011-04-01 |
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