CN102024850B - 金属氧化物半导体场效应晶体管及其制造方法 - Google Patents
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Abstract
本发明提供一种金属氧化物半导体场效应晶体管及其制造方法,该晶体管包括:一半导体基底;一沟道层,设置在该基底的顶表面上;一栅极介电层,插入一栅电极与该沟道层之间;以及介电延伸层,设置在该沟道层的顶部上,并插入该栅电极与欧姆接触之间;其中该栅极介电层包括一第一材料,该第一材料与该沟道层的顶表面形成一低缺陷的界面;以及其中该介电延伸层包括一不同于该第一材料的第二材料,该第二材料与该沟道层形成一导电表面沟道。本发明能够使III-V族MOSFET在导通状态时具有低的寄生导通电阻与高的跨导,且在关闭状态时具有低的次临界摆幅。
Description
技术领域
本发明涉及一种沟道层含有例如InGaAs、InAs或InAsSb的III-V族半导体的金属氧化物半导体场效应晶体管及其制造方法。
背景技术
本发明涉及沟道层含有例如InGaAs、InAs或InAsSb的III-V族半导体的金属氧化物半导体场效应晶体管(此后称之为“III-V族MOSFET(III-VMOSFET)”或“薄体MOSFET(thin body MOSFET)”)。在公知技术中,一般当III-V族MOSFET是形成在GaAs基底上时,会使用铟(In)摩尔分率低(<30%)的InGaAs沟道;而当形成在InP基底上时,则会使用铟摩尔分率高(≈50-100%)的InGaAs沟道。具有铟(In)含量较高的沟道层的III-V族MOSFET也适合未来形成在硅基底上的CMOS应用。
在公知技术中,沟道具有高的铟摩尔分率的MOSFET使用一般的离子掺杂法形成源极与漏极延伸区域以降低寄生电阻,如Y.Xuan等人在“High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET withMaximum Drain Current Exceeding 1A/mm,”Electron Device letters,Vol.29,No.4,p.294(2008)中所述。0.5μm的装置其最终的有效寄生串联源极/漏极电阻(parasitic series source/drain resistance(Rsd))约为2000Ωμm,且次临界摆幅(subthreshold swing(S))为200mV/decade。公知技术还揭示无掺杂的III-V族MOSFET,其是使用极性与沟道相反并形成在栅极氧化层表面上的电荷层,借此降低源极/漏极延伸区域中的寄生电阻,如R.J.W.Hill等人在“1μmgate length,In0.75Ga0.25As channel,thin body n-MOSFET on InP substrate withtransconductance of 73μS/μm,”Electronics Letter,Vol.44,No.7,pp.498-500(2008),与美国专利公开号2008/0102607中所述。在此例子中,1μm的装置其Rsd约为530Ωμm,且次临界摆幅为1100mV/decade。公知技术也揭示使用从源极接触延伸至漏极接触的单个氧化层,其同时在栅极下方与源极/漏极延伸区域中诱导出导电的表面沟道,如N.Li等人在“Properties of InAsmetal-oxide-semiconductor structures with atomic-layer-deposited Al2O3Dielectric,”Applied Physics Letters,Vol.92,143507(2008)中所述。N.Li等人测量5μm的装置得到Rsd为52,500Ωμm,且次临界摆幅为400mV/decade。而测量得的跨导(transconductance;gm)非常小,为2.3μS/μm。
国际半导体技术蓝图(International Technology Roadmap forSemiconductors)显示22纳米及更小尺寸世代的CMOS装置需要符合Rsd≤155Ωum、S<100mV/decade,且gm=3000-4000μS/μm的条件。然而,所有的公知技术并无法达到上述需求。
发明内容
本发明为了解决现有技术的问题而提供一种金属氧化物半导体场效应晶体管,包括:一半导体基底;一沟道层,设置在该基底的顶表面上;一栅极介电层,插入一栅电极与该沟道层之间;以及介电延伸层,设置在该沟道层的顶部上,并插入该栅电极与欧姆接触之间;其中该栅极介电层包括一第一材料,该第一材料与该沟道层的顶表面形成一低缺陷的界面;以及其中该介电延伸层包括一不同于该第一材料的第二材料,该第二材料与该沟道层形成一导电表面沟道。
本发明也提供一种薄体金属氧化物半导体场效应晶体管,包括:一半导体基底;一沟道层,设置在该基底的顶表面上,该沟道层包括一III-V族半导体;一栅极介电层,插入一栅电极与该沟道层之间,并沿着该沟道层的前侧与后侧设置;以及介电延伸层,设置在沟道层的顶部上,并插入该栅电极与欧姆接触之间;其中该栅极介电层包括一第一材料,该第一材料沿着该沟道层的顶表面、前侧表面与后侧表面而与该沟道层形成一低缺陷的界面;以及其中该介电延伸层包括一不同于该第一材料的第二材料,该第二材料与该沟道层形成一导电表面沟道。
本发明还提供一种包括栅电极位于源极与漏极欧姆接触之间的薄体金属氧化物半导体场效应晶体管的制造方法,包括:在一半导体基底的顶表面上提供一沟道层;在该栅电极与该沟道层之间提供一栅极介电层;以及提供介电延伸层,设置在该沟道层的顶部上,并插入该栅电极与欧姆接触之间;其中该栅极介电层包括第一材料,该第一材料与该沟道层形成一低缺陷的界面;以及其中该介电延伸层包括一不同于该第一材料的第二材料,该第二材料与该沟道层形成一导电表面沟道。
本发明能够使III-V族MOSFET在导通状态时具有低的寄生导通电阻与高的跨导,且在关闭状态时具有低的次临界摆幅。
附图说明
图1A至图1C显示各种典型的III-V族MOSFET。
图2为本发明一实施例的III-V族MOSFET垂直于栅极的剖面图,III-V族MOSFET包括导电表面沟道延伸区域与栅极控制的沟道侧壁。
图3为图2的MOSFET位于栅电极210下方且平行于栅电极的剖面图。
图4为MOSFET的俯视图。
其中,附图标记说明如下:
100~MOSFET;101~基底层;102~沟道层;103~离子掺杂延伸区域;104~欧姆接触;106~栅极氧化层;108~栅电极;110~栅极侧壁;112~隔离区域;120~MOSFET;122~基底层;124~沟道层;126~栅极氧化层;128~源极与漏极欧姆接触;130~栅电极;132~栅极侧壁;133~隔离区域;134~导电的表面沟道;136~延伸区域;138~界面;200~MOSFET;202~基底层;204~沟道层;206~栅极介电层;207~延伸介电层;208~源极与漏极欧姆接触;210~栅电极;212~栅极侧壁;213~隔离区域;214~区域;216~导电表面沟道;300~侧壁。
具体实施方式
以下是通过图示说明本发明的概念。要强调的是,图中的各种元件并未画成与工业标准规范相符的比例。实际上,为了清楚地描述本发明,各种元件的尺寸可任意地放大或缩小。
在此所述的实施例提供III-V族MOSFET,其在导通状态时具有低的寄生导通电阻(parasitic on-resistance;Rsd)与高的跨导(transconductance;gm),且在关闭状态时具有低的次临界摆幅(subthreshold swing;S)。本发明一实施例包括III-V族MOSFET,其同时具有只在源极/漏极延伸区域诱导的导电表面沟道造成的低导通电阻;在栅极区域使用低界面缺陷的栅极氧化物所造成的高跨导;以及装置在关闭状态时由于耗尽的沟道侧壁所造成的低次临界摆幅。
图1A至图1C显示各种典型的III-V族MOSFET。图1A显示第一典型的III-V族MOSFET 100的剖面图。III-V族MOSFET 100包括宽能隙半导体的基底层101,其上方设置有沟道层102并具有离子掺杂延伸区域103。欧姆接触104设置在部分的离子掺杂延伸区域103上。沟道层102包括多个III-V族半导体中的其中一个,例如InGaAs、InAs或InAsSb。
栅极氧化层106延伸在欧姆接触104之间,且栅电极108与栅极侧壁110设置在栅极氧化层106的上方。MOSFET 100还包括隔离区域112。化合物半导体中的施体掺杂质的活化效率一般很低,只有几个百分比的等级,且活化施体的浓度是限制在接近5x1018原子cm-3(atom cm-3)。举例来说,对迁移率为2500cm2/Vs的10nm的沟道层来说,其片电阻高达500Ω/sq,此会造成过高的Rsd。
图1B显示第二典型的III-V族MOSFET 120的剖面图。MOSFET 120包括宽能隙半导体的基底层122,其上方设置有沟道层124。沟道层124包括多个III-V族半导体中的其中一个,例如InGaAs、InAs或InAsSb。
MOSFET 120包括单个栅极氧化层126,延伸在源极与漏极欧姆接触128之间。栅电极130与栅极侧壁132设置在栅极氧化层126的上方。MOSFET120还包括隔离区域133。若InGaAs沟道层具有高的In摩尔分率,特别是InAs沟道层具有高的In摩尔分率,而其表面被氧化或其终端具有高程度的缺陷时,会造成导电表面沟道134。虽然位于栅电极130与欧姆接触128之间的延伸区域136有可能达成低的电阻,然而由于栅极氧化层126与沟道层124之间的界面138的高缺陷,栅电极130下方的电荷控制成为不可能,因而造成非常小的跨导。
图1A与图1B显示MOSFET垂直于对应的栅电极的剖面图。图1C则显示MOSFET 120位于栅电极130下方且平行于栅电极130的剖面图。请参考图1C,隔离区域133与沟道层124的侧壁之间会形成高缺陷的界面138,而在沟道层124的侧壁产生导电表面沟道134。由于导电表面沟道134是无法被耗尽的导电层,因此MOSFET 120在关闭状态时会造成高次临界摆幅与高源极至漏极的漏电流(source-to-drain leakage current)。
图2显示本发明一实施例的III-V族MOSFET 200垂直于栅极的剖面图。如图2中所示,MOSFET 200包括宽能隙半导体的基底层202,其上方设置有沟道层204。沟道层204包括多个III-V族半导体中的其中一个,例如InGaAs、InAs或InAsSb。
MOSFET 200包括栅极介电层206与延伸介电层207,延伸在源极与漏极欧姆接触208之间。栅电极210设置于栅极介电层206的上方,且栅极侧壁212设置在延伸介电层207的上方。MOSFET 200还包括隔离区域213。如先前所述,栅极介电层206包括适合的氧化物或其他绝缘材料,其在沟道层204提供低缺陷的界面,而在栅极下方造成有效的电荷控制的区域,其如符号214所示。详细地说,区域214会被栅极控制,且在装置200关闭状态时电荷载流子能有效地被耗尽。
延伸介电层207是设置于邻接且自对准于栅电极210,以诱导出导电表面沟道216,其能将延伸电阻(extension resistance)最小化。延伸介电层207包括适合的氧化物或其他绝缘材料,此材料可与沟道层204产生高缺陷的界面,借此在半导体表面或邻近半导体表面的区域产生电荷累积层(chargeaccumulation layer)。延伸介电层207能借由对沟道层204的表面进行氧化而相对容易地形成。要注意延伸介电层207与沟道层204产生的“高缺陷”的界面是相对于栅极介电层206与沟道层204产生的“低缺陷”的界面作定义。
图3则显示MOSFET 200位于栅电极210下方且平行于栅电极210的剖面图。由于沟道层204的侧壁300与栅极介电层206形成低缺陷的界面,因此能有效地控制在侧壁300的电荷。因此,包含侧壁300的区域,会类似于上述区域214,被栅极控制且在装置200的关闭状态下,可有效地耗尽电荷载流子。
图4为MOSFET 200的俯视图,显示隔离区域213相对于栅电极210及源极与漏极欧姆接触208的位置。
虽然本发明已以优选实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可做些许更动与润饰。举例来说,所述方法的各种步骤可以不同的顺序或连续地执行,或与其他步骤合并、还分割成其他步骤或以其他步骤取代,或全部移除。另外,在说明书中的方法或其他部分所述的各种功能,可合并提供额外及/或其他的功能。因此,本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (10)
1.一种金属氧化物半导体场效应晶体管,包括:
一半导体基底;
一沟道层,设置在该基底的顶表面上,该沟道层包括多个III-V族半导体中的其中一个;
一栅极介电层,插入一栅电极与该沟道层之间;以及
介电延伸层,设置在该沟道层的顶部上,并插入该栅电极与源极和漏极欧姆接触之间,该介电延伸层是借由氧化沟道层的表面形成;
其中该栅极介电层包括一第一材料,该第一材料与该沟道层的顶表面形成一低缺陷率的界面,以在栅电极下方造成有效的电荷控制区域;以及
其中该介电延伸层包括一不同于该第一材料的第二材料,该第二材料与该沟道层产生高缺陷的界面,借此该第二材料与该沟道层形成一导电表面沟道,并且该介电延伸层与该沟道层产生的高缺陷的界面是相对于该栅极介电层与该沟道层产生的低缺陷的界面作定义。
2.如权利要求1所述的金属氧化物半导体场效应晶体管,其中该沟道层包括InGaAs、InAs与InAsSb中的其中一个。
3.如权利要求1所述的金属氧化物半导体场效应晶体管,其中该基底包括一宽能隙半导体材料。
4.如权利要求1所述的金属氧化物半导体场效应晶体管,还包括一隔离区域,沿着该半导体基底的边缘设置。
5.一种薄体金属氧化物半导体场效应晶体管,包括:
一半导体基底;
一沟道层,设置在该基底的顶表面上,该沟道层包括多个III-V族半导体中的其中一个;
一栅极介电层,插入一栅电极与该沟道层之间,并沿着该沟道层的前侧与后侧设置;以及
介电延伸层,设置在沟道层的顶部上,并插入该栅电极与源极和漏极欧姆接触之间,该介电延伸层是借由氧化沟道层的表面形成;
其中该栅极介电层包括一第一材料,该第一材料沿着该沟道层的顶表面、前侧表面与后侧表面而与该沟道层形成一低缺陷率的界面,以在栅电极下方造成有效的电荷控制区域;以及
其中该介电延伸层包括一不同于该第一材料的第二材料,该第二材料与该沟道层产生高缺陷的界面,借此该第二材料与该沟道层形成一导电表面沟道,并且该介电延伸层与该沟道层产生的高缺陷的界面是相对于该栅极介电层与该沟道层产生的低缺陷的界面作定义。
6.如权利要求5所述的薄体金属氧化物半导体场效应晶体管,其中该沟道层包括InGaAs、InAs与InAsSb中的其中一个。
7.如权利要求5所述的薄体金属氧化物半导体场效应晶体管,还包括一隔离区域,沿着该半导体基底的边缘设置。
8.一种包括栅电极位于源极与漏极欧姆接触之间的薄体金属氧化物半导体场效应晶体管的制造方法,包括:
在一半导体基底的顶表面上提供一沟道层,该沟道层包括多个III-V族半导体中的其中一个;
在该栅电极与该沟道层之间提供一栅极介电层;以及
提供介电延伸层,设置在该沟道层的顶部上,并插入该栅电极与源极和漏极欧姆接触之间,该介电延伸层是借由氧化沟道层的表面形成;
其中该栅极介电层包括第一材料,该第一材料与该沟道层形成一低缺陷率的界面,以在栅电极下方造成有效的电荷控制区域;以及
其中该介电延伸层包括一不同于该第一材料的第二材料,该第二材料与该沟道层产生高缺陷的界面,借此该第二材料与该沟道层形成一导电表面沟道,并且该介电延伸层与该沟道层产生的高缺陷的界面是相对于该栅极介电层与该沟道层产生的低缺陷的界面作定义。
9.如权利要求8所述的薄体金属氧化物半导体场效应晶体管的制造方法,其中该沟道层包括InGaAs、InAs与InAsSb中的其中一个。
10.如权利要求8所述的薄体金属氧化物半导体场效应晶体管的制造方法,其中该介电延伸层是借由氧化该半导体基底的表面形成。
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9680027B2 (en) | 2012-03-07 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nickelide source/drain structures for CMOS transistors |
US9252237B2 (en) | 2012-05-09 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors, semiconductor devices, and methods of manufacture thereof |
US20130299895A1 (en) | 2012-05-09 | 2013-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Iii-v compound semiconductor device having dopant layer and method of making the same |
CN105633169A (zh) * | 2016-03-04 | 2016-06-01 | 西安电子科技大学 | 基于InAs材料的铁电场效应晶体管及其制备方法 |
CN106568548A (zh) * | 2016-10-27 | 2017-04-19 | 北京遥测技术研究所 | 基于soi‑mems技术的电容式绝压微压气压传感器 |
WO2018182687A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | Field effect transistor structures |
US10468494B2 (en) * | 2018-02-09 | 2019-11-05 | United Microelectronics Corp. | High-voltage device and method for fabricating the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5920105A (en) * | 1996-09-19 | 1999-07-06 | Fujitsu Limited | Compound semiconductor field effect transistor having an amorphous gas gate insulation layer |
CN1291793A (zh) * | 1999-04-22 | 2001-04-18 | 索尼株式会社 | 制造半导体器件的方法 |
US7429506B2 (en) * | 2005-09-27 | 2008-09-30 | Freescale Semiconductor, Inc. | Process of making a III-V compound semiconductor heterostructure MOSFET |
US7435636B1 (en) * | 2007-03-29 | 2008-10-14 | Micron Technology, Inc. | Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1503411A (en) * | 1976-01-16 | 1978-03-08 | Nat Res Dev | Gaas mosfet |
GB1536177A (en) * | 1976-12-07 | 1978-12-20 | Nat Res Dev | Anodising a compound semiconductor |
US4291327A (en) * | 1978-08-28 | 1981-09-22 | Bell Telephone Laboratories, Incorporated | MOS Devices |
US4312113A (en) * | 1978-10-23 | 1982-01-26 | Eaton Corporation | Method of making field-effect transistors with micron and submicron gate lengths |
US4226667A (en) * | 1978-10-31 | 1980-10-07 | Bell Telephone Laboratories, Incorporated | Oxide masking of gallium arsenide |
IT1171402B (it) * | 1981-07-20 | 1987-06-10 | Selenia Ind Eletroniche Associ | Transistor ad effeto di campo a barriera metallo-semiconduttorre conzona svuotata modificata |
US4525239A (en) * | 1984-04-23 | 1985-06-25 | Hewlett-Packard Company | Extrinsic gettering of GaAs wafers for MESFETS and integrated circuits |
JPS60239066A (ja) * | 1984-05-11 | 1985-11-27 | Hitachi Ltd | 半導体装置 |
US5273937A (en) * | 1988-01-08 | 1993-12-28 | Kabushiki Kaisha Toshiba | Metal semiconductor device and method for producing the same |
US5188978A (en) * | 1990-03-02 | 1993-02-23 | International Business Machines Corporation | Controlled silicon doping of III-V compounds by thermal oxidation of silicon capping layer |
JP2773449B2 (ja) * | 1991-04-10 | 1998-07-09 | 日立電線株式会社 | 金属絶縁物半導体電界効果トランジスタ |
US5597768A (en) * | 1996-03-21 | 1997-01-28 | Motorola, Inc. | Method of forming a Ga2 O3 dielectric layer |
JPH10150185A (ja) * | 1996-11-20 | 1998-06-02 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5902130A (en) * | 1997-07-17 | 1999-05-11 | Motorola, Inc. | Thermal processing of oxide-compound semiconductor structures |
US5958519A (en) * | 1997-09-15 | 1999-09-28 | National Science Council | Method for forming oxide film on III-V substrate |
US5945718A (en) * | 1998-02-12 | 1999-08-31 | Motorola Inc. | Self-aligned metal-oxide-compound semiconductor device and method of fabrication |
US6200866B1 (en) * | 1998-02-23 | 2001-03-13 | Sharp Laboratories Of America, Inc. | Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET |
US6093947A (en) * | 1998-08-19 | 2000-07-25 | International Business Machines Corporation | Recessed-gate MOSFET with out-diffused source/drain extension |
US6960537B2 (en) * | 2001-10-02 | 2005-11-01 | Asm America, Inc. | Incorporation of nitrogen into high k dielectric film |
US6756320B2 (en) * | 2002-01-18 | 2004-06-29 | Freescale Semiconductor, Inc. | Method of forming article comprising an oxide layer on a GaAs-based semiconductor structure |
US7442654B2 (en) * | 2002-01-18 | 2008-10-28 | Freescale Semiconductor, Inc. | Method of forming an oxide layer on a compound semiconductor structure |
JP4134575B2 (ja) * | 2002-02-28 | 2008-08-20 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US6713819B1 (en) * | 2002-04-08 | 2004-03-30 | Advanced Micro Devices, Inc. | SOI MOSFET having amorphized source drain and method of fabrication |
US6989556B2 (en) * | 2002-06-06 | 2006-01-24 | Osemi, Inc. | Metal oxide compound semiconductor integrated transistor devices with a gate insulator structure |
US7615829B2 (en) * | 2002-06-07 | 2009-11-10 | Amberwave Systems Corporation | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors |
US6891234B1 (en) * | 2004-01-07 | 2005-05-10 | Acorn Technologies, Inc. | Transistor with workfunction-induced charge layer |
AU2003265691A1 (en) * | 2002-08-26 | 2004-03-11 | University Of Florida | GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE |
US6770536B2 (en) * | 2002-10-03 | 2004-08-03 | Agere Systems Inc. | Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate |
US6963090B2 (en) * | 2003-01-09 | 2005-11-08 | Freescale Semiconductor, Inc. | Enhancement mode metal-oxide-semiconductor field effect transistor |
JP4713078B2 (ja) * | 2003-12-15 | 2011-06-29 | シャープ株式会社 | 半導体装置の製造方法および半導体装置 |
US7045404B2 (en) | 2004-01-16 | 2006-05-16 | Cree, Inc. | Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof |
US7385247B2 (en) * | 2004-01-17 | 2008-06-10 | Samsung Electronics Co., Ltd. | At least penta-sided-channel type of FinFET transistor |
KR100625175B1 (ko) * | 2004-05-25 | 2006-09-20 | 삼성전자주식회사 | 채널층을 갖는 반도체 장치 및 이를 제조하는 방법 |
KR100604870B1 (ko) * | 2004-06-16 | 2006-07-31 | 삼성전자주식회사 | 접합 영역의 어브럽트니스를 개선시킬 수 있는 전계 효과트랜지스터 및 그 제조방법 |
KR100541515B1 (ko) * | 2004-07-22 | 2006-01-11 | 삼성전자주식회사 | 수직 채널 패턴을 갖는 반도체 장치 및 이를 제조하는 방법 |
JP4490336B2 (ja) * | 2005-06-13 | 2010-06-23 | シャープ株式会社 | 半導体装置およびその製造方法 |
US20070120153A1 (en) * | 2005-11-29 | 2007-05-31 | Advanced Analogic Technologies, Inc. | Rugged MESFET for Power Applications |
US20070131938A1 (en) * | 2005-11-29 | 2007-06-14 | Advanced Analogic Technologies, Inc. | Merged and Isolated Power MESFET Devices |
US20080068868A1 (en) * | 2005-11-29 | 2008-03-20 | Advanced Analogic Technologies, Inc. | Power MESFET Rectifier |
US7564081B2 (en) * | 2005-11-30 | 2009-07-21 | International Business Machines Corporation | finFET structure with multiply stressed gate electrode |
KR100653536B1 (ko) * | 2005-12-29 | 2006-12-05 | 동부일렉트로닉스 주식회사 | 반도체 소자의 핀 전계효과 트랜지스터 제조방법 |
WO2007142894A2 (en) * | 2006-05-30 | 2007-12-13 | Purdue Research Foundation | Apparatus and method of forming a mosfet with atomic layer deposited gate dielectric |
JP4271210B2 (ja) * | 2006-06-30 | 2009-06-03 | 株式会社東芝 | 電界効果トランジスタ、集積回路素子、及びそれらの製造方法 |
US7682912B2 (en) * | 2006-10-31 | 2010-03-23 | Freescale Semiconductor, Inc. | III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same |
US7943469B2 (en) * | 2006-11-28 | 2011-05-17 | Intel Corporation | Multi-component strain-inducing semiconductor regions |
KR100864631B1 (ko) * | 2007-02-23 | 2008-10-22 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜지스터 및 그 제조 방법 |
JP2008277640A (ja) * | 2007-05-02 | 2008-11-13 | Toshiba Corp | 窒化物半導体素子 |
US7812370B2 (en) | 2007-07-25 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling |
JP5448530B2 (ja) * | 2009-03-31 | 2014-03-19 | 古河電気工業株式会社 | 電界効果トランジスタ |
-
2009
- 2009-09-18 US US12/562,790 patent/US20110068348A1/en not_active Abandoned
- 2009-12-22 TW TW098144138A patent/TWI419331B/zh active
-
2010
- 2010-02-01 CN CN2010101084557A patent/CN102024850B/zh active Active
- 2010-06-11 KR KR1020100055672A patent/KR101145991B1/ko active IP Right Grant
- 2010-06-21 EP EP10006436.9A patent/EP2299480A3/en not_active Withdrawn
- 2010-09-15 JP JP2010206272A patent/JP5334934B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5920105A (en) * | 1996-09-19 | 1999-07-06 | Fujitsu Limited | Compound semiconductor field effect transistor having an amorphous gas gate insulation layer |
CN1291793A (zh) * | 1999-04-22 | 2001-04-18 | 索尼株式会社 | 制造半导体器件的方法 |
US7429506B2 (en) * | 2005-09-27 | 2008-09-30 | Freescale Semiconductor, Inc. | Process of making a III-V compound semiconductor heterostructure MOSFET |
US7435636B1 (en) * | 2007-03-29 | 2008-10-14 | Micron Technology, Inc. | Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods |
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KR20110031078A (ko) | 2011-03-24 |
US20110068348A1 (en) | 2011-03-24 |
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