TWI419276B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
TWI419276B
TWI419276B TW099111380A TW99111380A TWI419276B TW I419276 B TWI419276 B TW I419276B TW 099111380 A TW099111380 A TW 099111380A TW 99111380 A TW99111380 A TW 99111380A TW I419276 B TWI419276 B TW I419276B
Authority
TW
Taiwan
Prior art keywords
metal layer
layer
hole
main surface
semiconductor device
Prior art date
Application number
TW099111380A
Other languages
English (en)
Chinese (zh)
Other versions
TW201108362A (en
Inventor
西澤弘一郎
Original Assignee
三菱電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機股份有限公司 filed Critical 三菱電機股份有限公司
Publication of TW201108362A publication Critical patent/TW201108362A/zh
Application granted granted Critical
Publication of TWI419276B publication Critical patent/TWI419276B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0116—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW099111380A 2009-08-20 2010-04-13 Semiconductor device and manufacturing method thereof TWI419276B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009191093A JP5532743B2 (ja) 2009-08-20 2009-08-20 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
TW201108362A TW201108362A (en) 2011-03-01
TWI419276B true TWI419276B (zh) 2013-12-11

Family

ID=43604671

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099111380A TWI419276B (zh) 2009-08-20 2010-04-13 Semiconductor device and manufacturing method thereof

Country Status (3)

Country Link
US (2) US8581411B2 (https=)
JP (1) JP5532743B2 (https=)
TW (1) TWI419276B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9616379B2 (en) * 2013-07-25 2017-04-11 Korea Institute Of Energy Research Method for preparing hydrogen separation membrane and device for preparing hydrogen separation membrane
US9887131B2 (en) 2014-03-27 2018-02-06 Mitsubishi Electric Corporation Semiconductor device having a Pd-containing adhesion layer
WO2023079631A1 (ja) * 2021-11-04 2023-05-11 三菱電機株式会社 半導体装置及びその製造方法
JP7831687B2 (ja) * 2023-03-10 2026-03-17 三菱電機株式会社 半導体装置及びその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179533A (en) * 1978-04-25 1979-12-18 The United States Of America As Represented By The Secretary Of The Navy Multi-refractory films for gallium arsenide devices
US6268619B1 (en) * 1997-04-24 2001-07-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with high aspect ratio via hole including solder repelling coating
US20040213895A1 (en) * 2003-04-24 2004-10-28 Semiconductor Technology Academic Research Center Method of manufacturing multilevel interconnection
US20080012134A1 (en) * 2006-06-28 2008-01-17 Samsung Electronics Co., Ltd. Metal interconnection structures and methods of forming the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3642528A (en) * 1968-06-05 1972-02-15 Matsushita Electronics Corp Semiconductor device and method of making same
US5075763A (en) * 1988-09-28 1991-12-24 Kopin Corporation High temperature metallization system for contacting semiconductor materials
JPH03109725A (ja) * 1989-09-25 1991-05-09 Fujitsu Ltd 半導体装置の製造方法
JP2679320B2 (ja) * 1989-12-20 1997-11-19 富士電機株式会社 ショットキバリアダイオード
US5027189A (en) * 1990-01-10 1991-06-25 Hughes Aircraft Company Integrated circuit solder die-attach design and method
JPH07193214A (ja) 1993-12-27 1995-07-28 Mitsubishi Electric Corp バイアホール及びその形成方法
US5956362A (en) * 1996-02-27 1999-09-21 Matsushita Electric Industrial Co., Ltd. Semiconductor light emitting device and method of etching
CA2328907A1 (en) * 1999-02-18 2000-08-24 Naoki Tsukiji Electrode for semiconductor device and its manufacturing method
JP3462166B2 (ja) * 2000-09-08 2003-11-05 富士通カンタムデバイス株式会社 化合物半導体装置
US6787910B2 (en) * 2002-07-23 2004-09-07 National Chiao Tung University Schottky structure in GaAs semiconductor device
JP2005109058A (ja) * 2003-09-30 2005-04-21 Sanyo Electric Co Ltd 半導体素子およびその製造方法
JP4637009B2 (ja) 2005-12-02 2011-02-23 三菱電機株式会社 半導体装置の製造方法
JP2008251562A (ja) * 2007-03-29 2008-10-16 Sharp Corp 半導体レーザ素子およびその形成方法
JP2009064961A (ja) * 2007-09-06 2009-03-26 Sharp Corp 半導体レーザ装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179533A (en) * 1978-04-25 1979-12-18 The United States Of America As Represented By The Secretary Of The Navy Multi-refractory films for gallium arsenide devices
US6268619B1 (en) * 1997-04-24 2001-07-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with high aspect ratio via hole including solder repelling coating
US20040213895A1 (en) * 2003-04-24 2004-10-28 Semiconductor Technology Academic Research Center Method of manufacturing multilevel interconnection
US20080012134A1 (en) * 2006-06-28 2008-01-17 Samsung Electronics Co., Ltd. Metal interconnection structures and methods of forming the same

Also Published As

Publication number Publication date
JP2011044546A (ja) 2011-03-03
US20110042822A1 (en) 2011-02-24
US8581411B2 (en) 2013-11-12
TW201108362A (en) 2011-03-01
JP5532743B2 (ja) 2014-06-25
US20140035145A1 (en) 2014-02-06

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