TWI415261B - 用於提昇內嵌矽碳之ｎ型金氧半場效電晶體之效能的凸起淺溝構隔離結構及超鑲嵌技術 - Google Patents

用於提昇內嵌矽碳之ｎ型金氧半場效電晶體之效能的凸起淺溝構隔離結構及超鑲嵌技術 Download PDF

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TWI415261B
TWI415261B TW096124949A TW96124949A TWI415261B TW I415261 B TWI415261 B TW I415261B TW 096124949 A TW096124949 A TW 096124949A TW 96124949 A TW96124949 A TW 96124949A TW I415261 B TWI415261 B TW I415261B
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Ashima B Chakravarti
Dureseti Chidambarrao
Judson R Holt
Yaocheng Liu
Kern Rim
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Description

用於提昇內嵌矽碳之N型金氧半埸效電晶體之效能的凸起淺溝構隔離結構及超鑲嵌技術
本發明大體上有關於場效電晶體結構，更明確而言，係有關於一種具有能提升載子遷移率(carrier mobility)之應力通道的電晶體結構。
在現今半導體領域中，已意識到縮小半導體元件的尺寸能在積體電路效能、功能與製造經濟效益上帶來無數的益處。例如，CMOS結構尺寸的縮減可能減少通道阻力並且提高切換速度。然而，當此類元件縮減成較小尺寸時，散射效應(scattering effect)可能減弱載子遷移率，並且將原本可能藉由減低通道阻力而達到增加切換速度的増益效果完全抹煞掉。
由於已知壓縮應力/應變(strain)能提高電洞的遷移率，而拉伸應力/應變能提高電子遷移率，因此藉著發展出一種能夠持續施加拉伸張力(tensile)或壓縮應力(compress stress)至場效電晶體通道處的結構，可提高載子遷移率，從而改善CMOS元件的效能。目前已發展出數種罩幕技術(masking techniques)以及適當的材料與沉積技術，用以對同一晶片中的N型場效電晶體(NFET)施加拉伸應力，以及對P型場效電晶體(PFET)施加壓縮應力。
舉例而言，目前已發展出來內嵌(embedded)式矽鍺結構，其可直接設置在源極與汲極區域中，以在通道內產生壓縮應力，並且提高P型場效電晶體的電洞遷移率。同樣地，也可使用晶格常數(lattice constant)小於矽的矽碳在N型場效電晶體的源汲極區域中建構內嵌式矽碳(e－Si：C)結構，以在通道中產生拉伸應力，從而提高電子遷移率。
然而，取代性碳濃度(或稱置換型碳濃度)必須超過1%原子百分比，才能獲得明顯的元件效能改善效果，但是碳在矽中的平衡取代固體溶解度(substitutional solid solubility)非常低。適合形成高碳取代濃度的低溫條件將會導致非常低的沉積選擇性，而低沉積選擇性可能降低元件製造良率。雖然目前已發展出一些非選擇性沉積技術用以形成高碳取代濃度，然而僅採用非選擇性沉機製程很難在元件中形成矽碳結構。
因此，本發明其一目的是提供一種可在電晶體中形成內嵌矽碳結構的簡易高效技術，以提高N型場效電晶體的電子遷移率。
本發明另一目的是提供一種能在不降低製造良率的情況下，將非選擇性沉積材料整合至積體電路電晶體中的技術。
本發明又一目的在於提供一種相較於習知電晶體而言，能使電晶體之通道區域具有較高拉伸應力/應變的結構。
為了達成本發明上述目的，本發明提供一種場效電晶體與一種積體電路，其中該場效電晶體包含一閘極區域、一通道區域、位於通道兩端且鄰接閘極區域的源極區與汲極區、一凸起隔離結構以及一矽碳材料所構成的主體；該凸起隔離結構鄰接該等源/汲極區且延伸進入該矽基材中並且從該矽基材的表面突出；該矽碳材料所構成的主體則延伸跨越該源/汲極區，且一部分的該矽碳材料主體磊晶成長至/自該矽基材的溝渠中且具有超過1%原子百分比的碳取代濃度。
根據本發明另一態樣，提供一種形成具有提升電子遷移率之電晶體的方法，該方法包括下列步驟：形成一延伸進入且延伸超出矽基材的凸出隔離結構(raised isolation structure)、在一通道區域上形成一閘極結構、在鄰接該通道區域處形成源極區與汲極區、在該閘極結構與該通道區域至少其中一者以及該隔離結構之間磊晶成長一碳取代濃度超過1%原子百分比的矽碳材料、平坦化該矽碳材料至抵達該閘極結構，以及將該矽碳材料蝕刻至該凸起隔離結構的表面或低於該表面。
現請參閱附圖，特別是第1圖。第1圖顯示根據本發明，藉著在通道區域中產生拉伸應力/應變來形成一具有提升電子遷移率之電晶體時，其製程初始階段中的電晶體剖面圖。並且了解到，可使用導電性的矽鍺(SiGe)合金來形成能產生壓縮應力/應變的內嵌結構，以提高P型場效電晶體中的電洞遷移率。雖然以下內容是描述具有內嵌矽碳結構的N型場效電晶體(NFET)的形成製程，但是若簡單地以矽鍺來取代矽碳材料，則下述製程亦完全適用於如第7圖所示的互補P型場效電晶體，並且以下描述的數個步驟可共同執行於同一個晶片或晶圓上的P型與N型場效電晶體，因而可提高內含本發明之積體電路整體製程的簡易性與經濟效益。
為了達成用以在鄰近結構上施加拉伸或壓縮應力的內嵌結構，通常需要形成一溝渠並且利用一應力誘發材料(stress－inducing material)來填充該溝渠。而此要求暗示著該應力誘發材料的沉積製程必須有選擇性。然而，如上所述般，具有適當碳取代濃度之矽碳材料的磊晶成長製程極為困難，並且利於產生高碳取代濃度的製程條件通常是非選擇性的(non－selective)。在過去，研究人員曾嘗試藉由諸如蝕刻等處理方式來提高含有夠高碳取代濃度之矽碳材料的沉積選擇性，卻都徒勞無功。因此，本發明尋求使用非選擇性沉積製程來達到選擇性沉積效果的方法。
第1圖顯示一基材110，在該基材110上依序地沉積或形成有一墊氧化層120與一墊氮化層130。隨後在此具有多層結構100上覆蓋一罩幕，並且在欲形成淺溝渠隔離(STI)結構的位置處將該罩幕加以圖案化。隨後，蝕刻該多層結構，並且將諸如氧化物與氮化物等隔離材料、其他隔離材料或上述材料組合物沉積在該多層結構上，再對該結構執行平坦化製程以形成如圖所示的STI結構140。
提供明顯高過基材的STI結構是對於實施本發明來說是很重要且需要的，其理由將詳述於下。因此，墊氧化層120與墊氮化層130的總厚度必需相當於該STI結構欲凸出基材表面的高度。已知氮化層與氧化層彼此之間可選擇性地進行蝕刻，因此該墊氧化物層可作為蝕刻氮化物過程中的蝕刻終止層，而氮化物層則作為上述概略提及之平坦化製程的研磨或蝕刻終止層。其後，可選擇性地蝕刻該氧化物直至該基材(例如，矽)，而使得留下的STI材料成為如第2圖所示般的凸起STI結構；或者，如果該STI結構包含暴露出來的氧化物或氮化物，由於這些膜層可能遠薄於STI的尺寸，使得蝕刻劑無法有效地攻擊該STI時，則可藉由計時式蝕刻(timed etch)法來蝕刻該等氧化物。須注意的是，此凸起STI結構的形成步驟可共同且同時用來形成該基材上的N型與P型場效電晶體(NFET與PFET)。
參閱第3圖，PFET區域被遮蔽住，並且根據任一種所欲的結構設計與適合用來形成該結構設計的製程來形成包含源極區151、汲極區152與閘極區域153的NFET電晶體150。此階段，或在此階段之前，可先形成類似的PFET結構。實施本發明時，較佳可在該電晶體150的閘極上提供一氮化物覆蓋層(nitride cap)154，但非必要。亦可根據現行的多種電晶體設計，較佳在鄰接該電晶體閘極結構處或該電晶體閘極結構的一部分上提供側壁間隙壁(sidewall spacer)。隨後如第4圖所示，非選擇性地沉積一矽碳(Si：C)厚層160。
在此圖中，將此厚層160繪示成複數個隨意尺寸的沉積塊(blocks)160’，以表示如果僅沉積一矽碳薄層時，在磊晶成長過程中該非選擇性沉積製程實際上將表現出極差的輪廓形態，並且此結果透過掃描電子顯微鏡影像來加以證實了。在過去，研究人員試圖改善矽碳沉積製程的選擇性，以期達成能在鄰近結構中產生應力的矽碳磊晶薄膜沉積，然而皆以失敗告終。
但是，根據本發明，則可直接在單晶矽上沉積極厚的矽碳層，而過度填滿該電晶體閘極堆疊結構間之間隙(溝渠)。隨後可如鑲嵌製程中的研磨製程般，將該過度填充的矽碳厚層研磨直至該閘極堆疊結構，並且接著進行蝕刻；而本案發明人將此整個製程稱為「超鑲嵌(super－Damascene)」製程，此超鑲嵌製程在溝渠或凹槽中所產生的結構會如同一鑲嵌結構或製程中所產生的結構般，但是在例如由該些閘極堆疊結構所定義出來的該最初過填充溝渠中的結構會凹陷，在該最初過填充溝渠中的結構最初是沉積至或低於用來形成部分溝渠結構的表面。
需注意到第4圖所繪示的，是根據本發明且特定用於形成N型場效電晶體的最後材料沉積製程。因此，尚未沉積用於P型場效電晶體中產生壓縮力的相應材料(例如矽鍺)，也就是在第3與4圖中所討論製程步驟中的遮蔽步驟(masking)之前尚未沉積用於P型場效電晶體中產生壓縮力的材料時，則可於此階段移除PFET區塊的外遮蔽層(block out mask)且執行該相應材料的沉積製程。在另一範例中，可同時或依序分別地對PFET與NFET至少執行該PFET與NFET應力/應變誘導材料的平坦化製程與可能使用的蝕刻製程，並且可依據所選擇的蝕刻劑與材料來決定是否需要額外的外遮蔽層，此平坦化與蝕刻製程將於以下內容中配合第5與6圖來說明之。
如第5圖所示，較佳可平坦化該矽碳厚層直至該氮化物覆蓋層154，該氮化物覆蓋層可作為研磨終止層。需注意的是，由於平坦化製程執行至抵達該覆蓋層154但也到達由絕緣材料所形成的側壁155，因此將矽碳厚層平坦化至該覆蓋層154可至少電性分離該等電晶體閘極，並且可移除該覆蓋層154來形成一接觸。換句話說，執行平坦化製程直至抵達該覆蓋層154且到達側壁155，可確保非選擇性沉積的導電性矽碳材料不會使個別電晶體的閘極之間發生短路問題。同時，平坦化製程亦使保留在介於該等電晶體閘極間之溝渠/區域內的矽碳厚層變得均勻一致，從而能更加均勻一致地執行接續的蝕刻製程。
接著請參閱第6圖，至少蝕刻該矽碳厚層直至STI結構140的表面，從而不僅使該等電晶體彼此完全分離開來，更使每個電晶體的源極與汲極以及相鄰電晶體分離開來。因此，雖然只採用非選擇性沉積製程，但上述蝕刻結合平坦化的製程卻能夠達到選擇性沉積的效果。該凸起STI結構的高度容許進行過度蝕刻，以確保在該等電晶體間或是個別電晶體之源極與汲極之間沒有矽碳材料橋接處。需注意的是，STI結構的高度必須選擇能夠允許執行實質過蝕刻以確保良好製造良率的同時，仍舊能夠留下足夠厚度的矽碳層160來產生足夠的應力。若將該凸起STI結構應用於互補PFET中以形成類似形狀的內嵌矽鍺(e－SiGe)結構時，也能夠提供同樣的好處與有益效果。
再者，該矽碳層延伸在整個源/汲極區以及在部分或所有的源/汲極延伸區域上，因此該矽碳層能就既定的電晶體間距(pitch)與STI結構側向尺寸來產生最大的應變量。此外，由於矽碳層延伸至電晶體側壁，因此該矽碳層能理想地靠近該電晶體通道，而能將拉伸應力/應變施加至該電晶體通道。更明確而言，在執行佈植製程而形成源極與汲極結構之後，將矽碳材料磊晶成長在矽基材上，該矽碳材料的較小晶格常數會在源極與汲極區域中造成拉伸應力，而所產生的應力會透過基材110的單晶結構而良好地傳遞至電晶體通道中，其中源極與汲極形成於該基材110內。
此外，必須了解到，本文所揭示由矽碳保留部分160所形成的內嵌結構(embedded structure)，並不會與習知用來施加拉伸或壓縮力至電晶體通道上以提升載子遷移率的覆蓋結構(capping structure，例如，結構170)相牴觸。也就是，可使用氮化物等材料來形成延伸在場效電晶體閘極上的覆蓋結構，且其亦能達到提升載子遷移率的效果。除了藉著使用該覆蓋結構而施加在通道上的力量之外，還可使用根據本發明的內嵌結構來提高施加在通道上的力量。或相反地，可藉由該覆蓋結構170來調整或控制本發明內嵌結構施加在通道上的力量。可依照需求，選擇使用拉伸性或壓縮性覆蓋材料來提高或降低根據本發明內嵌結構施加在通道上力量。
亦需了解到，第6圖所顯示的NFET(或如上所述般地同時形成PFET)已大致完成，僅剩下接觸形成製程(contact formation)，並且使用導電性矽碳材料有助於與該源極與汲極的接觸連接。可藉由任何已知或可預見的技術來形成連接至源極與汲極的接觸，並且該接觸可包括矽化物的形成。更進一步，由於該覆蓋結構無需延伸在整個源/汲極上，因此使用非導電性材料來形成該覆蓋結構並不會影響接觸的形成。
綜上所述，本發明提供一種簡單、經濟且高良率製程，其能形成拉伸性內嵌結構以提高N型場效電晶體中的電子遷移率，並且使用導電材料的應力大小遠高於習知覆蓋式結構所能得到的大小，特別是矽碳材料是目前唯一已知能產生拉伸應力的導電材料，同時根據本發明所得到的矽碳材料之碳取代濃度足以支持該高碳取代特性與選擇性沉積製程彼此間相牴觸的問題。此外，該製程可完全適用以形成PFET中用來提升電洞遷移率的壓縮結構。又該製程與覆蓋式應力誘發結構的形成製程完全相容，使得該覆蓋式應力誘發結構能與根據本發明所做的內嵌結構合併使用，從而提供習知技術無法達到的應力大小與電子遷移率。
雖然上述內容中以單一個較佳實施例來描述本發明，然而習知技術者皆明白可在不偏離後附申請專利範圍的精神與範圍下，對本發明作各種變化與修飾。
100．．．多層結構
110．．．基材
120．．．墊氧化層
130．．．墊氮化層
140．．．STI結構
150．．．電晶體
151．．．源極區
152．．．汲極區
153．．．閘極區域
154．．．覆蓋層
155．．．側壁
160．．．矽碳厚層
160’．．．沉積塊
170．．．覆蓋結構
參閱附圖與上述有關本發明較佳實施例的詳細說明，能更加了解本發明之上述目的、態樣與優點。該等附圖為：第1圖是根據本發明製造場效電晶體之初始階段的剖面圖；第2、3、4與5圖是根據本發明製造場效電晶體之中間階段的剖面圖；第6圖是根據本發明所大致完成之電晶體的剖面圖；第7圖係一積體電路的剖面圖，其顯示本發明可與P型場效電晶體元件中之內嵌矽鍺結構互相相容。
140．．．STI結構
160．．．矽碳厚層
170．．．覆蓋結構

Claims (15)

  1. 一種形成具有提升電子遷移率之電晶體的方法，該方法包括步驟：形成一凸起隔離結構，該凸起隔離結構延伸進入一矽基材且自該矽基材延伸出；在一通道區域上形成一閘極結構；形成鄰接該通道區域的源極區與汲極區；在該閘極結構與該通道區域至少其中一者以及該隔離結構之間磊晶成長一矽碳材料，並且該矽碳材料具有超過1%原子百分比的碳取代濃度；平坦化該矽碳材料至該閘極結構；及將該矽碳材料蝕刻至該凸起隔離結構的表面或低於該表面。
  2. 如申請專利範圍第1項所述之方法，更包括步驟：使該矽碳材料下凹，以低於該凸起隔離結構的表面。
  3. 如申請專利範圍第1項所述之方法，更包括步驟：形成一應力覆蓋結構覆蓋在該閘極區域上。
  4. 如申請專利範圍第1項所述之方法，更包括步驟：形成一具有內嵌矽鍺結構的場效電晶體。
  5. 如申請專利範圍第1項所述之方法，更包括步驟：形成一覆蓋層於該閘極結構上，且其中該平坦化的步驟包括研磨該覆蓋結構。
  6. 一種由根據申請專利範圍第1項至第5項中之任一項所述之方法所製造的場效電晶體，其包含：一閘極區域、一通道區域以及源極/汲極區，該源極區與汲極區位在該通道區域的末端處且鄰接該閘極區，該通道區域與該源極/汲極區形成於一矽基材內；一凸起隔離結構，其鄰接該源極/汲極區，並且延伸進入該矽基材中且從該矽基材的表面凸出；以及一矽碳材料主體，其延伸跨越該源極/汲極區，一部分的該矽碳材料主體磊晶成長至/自該矽基材的一溝渠中，且具有超過1%原子百分比的碳取代濃度。
  7. 如申請專利範圍第6項所述之場效電晶體，更包括：一應力覆蓋結構(stressed capping structure)，其延伸覆蓋在該閘極區域上。
  8. 如申請專利範圍第7項所述之場效電晶體，其中該應力覆蓋結構包含一拉伸層。
  9. 如申請專利範圍第7項所述之場效電晶體，其中該應力 覆蓋結構包含一壓縮層。
  10. 如申請專利範圍第6項所述之場效電晶體，其中該矽碳材料主體低於該凸起淺溝渠隔離結構的表面。
  11. 一種積體電路，其包括：由根據申請專利範圍第1項至第5項中之任一項所述之方法所製造的複數個第一與第二場效電晶體，該等場效電晶體包含：一閘極區域、一通道區域以及源極/汲極區，該源極區與汲極區位在該通道區域的末端處且鄰接該閘極區，該通道區域與該源極/汲極區形成於一矽基材內；一凸起隔離結構，其鄰接該源極/汲極區，並且延伸進入該矽基材中且從該矽基材的表面凸出；以及其中一第一場效電晶體包含一矽碳材料主體，該矽碳材料主體延伸跨越該源極/汲極區，一部分的該矽碳材料主體磊晶成長至/自該矽基材的一溝渠中並且具有超過1%原子百分比的碳取代濃度；以及其中一第二場效電晶體包含一矽鍺材料主體，其延伸跨越該源極區與汲極區。
  12. 如申請專利範圍第11項所述之積體電路，更包括：一應力覆蓋結構，其延伸覆蓋在該閘極區域上。
  13. 如申請專利範圍第12項所述之積體電路，其中該應力覆蓋結構包含一拉伸層。
  14. 如申請專利範圍第12項所述之積體電路，其中該應力覆蓋結構包含一壓縮層。
  15. 如申請專利範圍第11項所述之積體電路，其中該矽碳材料主體低於該凸起淺溝渠隔離結構的表面。
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