TWI377706B - Mount for semiconductor light emitting device - Google Patents

Mount for semiconductor light emitting device Download PDF

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Publication number
TWI377706B
TWI377706B TW093122563A TW93122563A TWI377706B TW I377706 B TWI377706 B TW I377706B TW 093122563 A TW093122563 A TW 093122563A TW 93122563 A TW93122563 A TW 93122563A TW I377706 B TWI377706 B TW I377706B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
base
region
semiconductor light
Prior art date
Application number
TW093122563A
Other languages
English (en)
Other versions
TW200511612A (en
Inventor
Jerome Chandra Bhat
Cresente S Elpedes
Paul S Martin
Serge L Rudaz
Original Assignee
Philips Lumileds Lighting Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Lumileds Lighting Co filed Critical Philips Lumileds Lighting Co
Publication of TW200511612A publication Critical patent/TW200511612A/zh
Application granted granted Critical
Publication of TWI377706B publication Critical patent/TWI377706B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/64Heat extraction or cooling elements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

1377706 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種用於諸如發光二極體之覆晶架構半導 體發光裝置之底座。 【先前技術】 ▲發光二極體(LED)係具有多重優勢之固態光源。其能夠可 靠地提供高亮度光,因而其尤其可應用於顯示器、交通燈 及指示器中。發光二極體之-重要類別由1多種第職 元素(如鎵、銦或鋁)及第乂族氮族元素製造。該等第出族 氮化LED能夠發出越過可視光譜並進入光譜之紫外範圍之 光,進而可望具有多種應用。其它發光二極體可由二族 構化物及第m料化物材㈣統製成,其發射琥轴色光、 紅色光及光譜之紅外區域光。 傳統地,藉由在基板上沈積—n型摻雜區域、一主動區域 及一P型摻雜區域製造LED。某些LED具有形成於裝置:側 之η型接點及形成於裝置另一側之p型接點,其建立一垂直 裝置。其它LED之兩接點形成於該裝置之同—側,由該等 接點提取光。該結構稱為i晶生長裝置。在垂直裝置與磊 晶生長裳置中,由主動區域產生之大部分光經由p型接點^ 開裝置。由於p型接點通常包括金屬及/或半透明金屬氧化 物以優化其電傳導特性,p型接點一般不易透射光,引起了 一設計問題。 近來提出了-種與此設計問題相關之覆晶架構。如圖丄 所示’在覆晶裝置1〇〇中晶粒11〇安裝於底座114上,其中接 95115.doc 1377706 點朝向底座。由主動區域產生之大部分光經由基板而非接 點離開裝置。所有電接點均可定位於覆晶晶粒之底部。裝 置之完成係藉由形成底座114、疊置於底座上之可焊接層 118-1與118-2及可焊接層上之焊接球122-1與122-2,接著將 晶粒110附接至焊接球122以向晶粒提供電接點。 現有設計藉由將導線接合件置放於具有可焊接層之電接 點内而為電流提供路徑。該導線接合件由形成於可焊接層 上且與導線130-1及130-2連接之焊接球丨^—丨及126_2組 成。接著導線可與發光裝置封裝之封裝引線132-1及132-2 連接。底座及晶粒本身藉由晶粒環氧樹脂附接至導線板 134。 導線接合件式裝置具有若干缺點。第一,導線接合件對 熱敏感。.因而LED設計中之一限制係導線接合件能承受多 少熱量。由於新一代LED計劃在更大壓力及更高溫度環境 下運作’導致運作溫度及熱產生的增加,此問題變得越來 越重要。導線中之電流加熱導線,此方法被稱為歐姆加熱 法。歐姆加熱之程度尤其由電流密度決定。提高之溫度及 重複熱循環可導致導線接合件損壞,諸如焊接球與可焊接 層分離、導線變脆或狹窄截面上之熔融引起導線破損。在 靜電放電(ESD)之狀況下或在諸如打開及關閉裝置之瞬時 期間,該加熱問題亦可發生。提高溫度操作亦可導致增強 焊接球126與可焊接層118之間的界面上之物理脆度及電阻 金屬間相增長,其最終會導致界面失效。 第二’導線接合件不能傳導大量熱量遠離LED。在常規 95115.doc 1377706 操作中在LED中產生熱量。藉由n型層電子與p型層電洞之 再組合在LED中產生光。此再組合之部分為輕射性的,引 起光子發射。然而再組合之相當大部分可為非輻射性的, 反而產生熱量。在某些裝置中,接著必須傳導在裝置中產 生之至少部分熱量遠離晶粒以避免損害LED。導線接合件 具有相對較小之截面區域因而不能傳導大量熱量遠:晶 粒。 第三’導線為較脆的,因而在諸如溫度衝擊、粗加工及 高濕度環境等極端操作條件下通常成為主要失效機構。為 保護脆弱導線接合件,LED必須裝配於對終端用戶有實際 用處之封裝中。 第四,導線接合件冑要在LED佔據面積之外部在底座上 之空間,使得裝置更大且更昂貴。由LED發射併入射於較 大底座上之光可自底座反射,其不恰當地增加了光源尺寸。 最後,導線接合件在LED隨後之封裝中可截留封裝中之 空氣,造成折射率之較大步進,其可降低自LED晶粒提取 光進入外部世界的效率。 【發明内容】 根據本發明之貫施例,一裝置包括一底座及一半導體發 光裝置,其安裝於一覆晶架構組態之該底座第一侧上之第 一導電區域及第二導電區域上,該底座在其第二侧上具有 第二導電區域及第四導電區域。利用該第三與第四導電區 域不需使用導線接合件即可將該底座焊接於諸如板之結構 上。藉由一第一導電層電連接該第一導電區域及該第三導 95115.doc 1377706 電區域’藉由-第二導電層電連接該第二導電區域及該第 四導電區域。該第一導電層及該第二導電層可安置於該底 座之外部或該底座之中。 _ 【實施方式】 根據本發明之實施例,其上安裝LED之底座在相對於led 之側上具有電接點,使得藉由焊料接合點而非導線接合件 可將LED及底座表面黏著於諸如板之另—裝置上。 圖2說明了具有焊料接合點之本發明之一實施例。藉由將 互連件122-1及丨22-2耦接至晶粒形成用於發光裝置1〇〇之晶 粒110之電接點。儘管所說明之實施例提及焊接球,但互連 件可由以下材料製成:基礎金屬、金屬合金 '半導體金屬 合金、焊料、熱性及電性導電膏或化合物(例如環氧樹脂)、 LED晶粒與底座之間不同金屬間之低共熔接合件(例如,鈀 中之鈀(Pd-In-Pd))、Au柱形球(stud-bump)或除球形以外之 焊料組態,諸如桿。在不同實施例中焊接球數目可為三個 或二個以上。三焊接球設計為晶粒11〇提供穩固支撐。在某 些實施例中為p型層提供接點之焊接球數目超過為n型層提 供接點之焊接球數目,例如2個p型焊接球及丨個n型焊接球。 焊接球122電耦接至導電表面118,該導電表面118在經由 焊料接合點可連接至另一結構之表面可黏著底座丨14上。儘 管以下實施例中導電表面118為可焊接層或表面並藉由焊 料接合點與其它裝置連接,除焊料外之其它導電表面及接 合件適合本發明並在本發明之範圍内。焊料接合點包括形 成於底座114及焊接區域13 8-1與138-2上之可焊接層118-1 95115.doc •9· iJ?77〇6 及118-2。在不同實施例中可焊接層與焊料數目可為三個或 三個以上。可焊接層118可形成於底座114之至少兩個表面 上。在某些實施例中可焊接層覆蓋底座114之相對表面,諸 如頂表面與底表面。如圖2所示,可焊接表面可圍繞底座之 側表面延伸,其將可焊接表面之頂部及底部連接。該等設 計提供了焊料138可焊接於其上之較大可焊接表面。焊= 138可僅在底座114之底部接觸可焊接表面或當可焊接表面 提供於底座114之側面上時可延伸至底座114之側面。焊料 138電耦接至形成於諸如印刷導線板之板134上的封裝引線 132-1及132-2。封裝引線132可由各種方式形成,例如,藉 由覆蓋導線板之一個以上的表面。最後,因為經由除頂部 之外的方向上發射產生於晶粒中之光子的一部分,所以底 座114之一或多個表面及面對LED 11〇之板134可為反射性 的或類似於圖1所示反射器133之反射器可附接至板134。反 射器具有一反射性表面,其被定位及塑造以將此等光子再 次導引於較佳發射方向,該方向通常垂直於板之平面。 底座114可自例如Si、SiC、蘭寳石、PCB、A1NX、Al2〇3 或在相關應用中之任何其它已知材料形成。焊料13 8可為, 例如:含Sn之合金(諸如pbSn-或AgSn-二元化合物、三元化 合物及四元化合物);含Au合金(諸如AuSn或AuGe二元化合 物);含一或多種下列金屬之合金:In、Bi、Pb、Sb、Ag、 Cu ;或一種金屬,諸如 Au、Ag、In、Sn、Pb、Bi、Ni、Pd 或Cu。可焊接層118可為例如金、銀、錄、銅、始或適用於 相關應用之其它材料。板134可自例如塑膠、陶瓷(諸如 95H5.doc •10- 1377706
Ab〇3或AIN)、複合層(諸如BN300或FR4)或含Cu、Mo、Ni 或W之金屬板形成。 由於若干原因發光二極體直接耦接至底座114而非導線 板134。第一’在Si底座之狀況下,藉由例如標準集成電路 製造技術ESD保護電路可直接整合於底座。適當ESD保護電 路之實例包括平行於LED之電容器、單一反平行二極體(諸 如Zener或Schottky二極體)及兩個相對耦合式Zener二極 體。第一’底座有助於裝置之良好光反射。第三,較小部 件可开> 成於底座而非導線板上。較小部件尺寸允許將焊接 球定位於緊靠底座上,以潛在地減小裝置之尺寸並改良裝 置之熱提取能力。 圖3說明了本發明之另一實施例。圖3之設計類似於圖2 之設汁。經由焊接球122將晶粒11 〇電耦接至導電層丨丨8。焊 料Π8將底座上之可焊接層實際電連接至形成於板134上之 封裝引線132,板Π4可為一印刷導線板。 此實施例之一態樣為一有效反射器之構型。反射井146 形成為底座114之一部分。可焊接層ι18覆蓋反射井表面之 分。在某些實施例中,基本上整個反射井1 46被可焊接 a 118覆蓋。可焊接層118係由具有合適反射性之材料形 成,使得其可反射大部分入射光。該等材料包括金及銀。 在某些實施例中’反射層可被形成為疊置在可焊接層118之 上,具有特定合適之反射特性。塑造該反射井以在光發射 之較佳方向反射入射光。此方向通常垂直於底座之平面, 但其它設計亦有可能。接著將晶粒定位於反射井中且藉由 95115.doc 1377706 焊接球122將其輕接至可焊接層η8β I置可礙入光輕合材 料丨5〇(諸如環氧樹脂或聚石夕氧)之中。光耦合材料is〇為晶粒 110提供機械及熱保護。光耦合材料亦可有效將所產生之光 導入較佳方向並耦合來自半導體層且進入外部環境之光。 圖4 3兒明了一種形成圖2及圖3所示之發光裝置的方法。圖 4以一平面圖說明了根據本發明之一實施例在晶圓4〇〇上之 底座114之陣列佈局。晶圓4〇〇被分割成在此後形成個別底 座114-1至114-N的區域,其中整數。n型可焊接層丨“」 被形成為疊置在底座114-1之-區域上,圖中標示為各個底 座左上角之減號。ρ型可焊接層118_2被形成為叠置在底座 114上之一與11型可焊接層互補之區域,圖中標示為各個底 座右下角之加號。形成可焊接層118以配合覆晶晶粒11〇之 佈局。 經由焊接球122提供可焊接層118及晶粒u〇之間的電耦 接。底座114被調整成支撐焊接球122〇 η型可濕金屬層154 被形成為疊置在η型可焊接層U8_i上以支撐η型焊接球 122-1。ρ型可濕金屬層^^丨及^卜以皮形成為疊置在ρ型可 焊接層U8-2上以支撐ρ型焊接球122_2及122_3。可濕金屬層 154及158提供合適區域用以焊接焊接球122_1至122_3,因而 在可焊接層118及晶粒11〇之間產生電耦接。在某些實施例 中Ρ型可濕金屬層158超過η型可濕金屬層154之數目,因為 經由至ρ型接點之連接自裝置中提取在主動區域產生教 量最為有效,所以該等連接之表面區域通常被最大化。由 於自η型接點形成之區域移除了主動區域,ρ型層及ρ型可濕 95115.doc -12- 1377706 金屬層提供用於自裝置提取熱量之最直接路徑。 •圖4之實施例具有三個烊接球。此設計具有高度機械穩定 性。在其它實施例中可採用更多焊接球或焊接桿。另外, 在圖4所示之實施例中,僅一個發光裝置與各個底座相連 接。在其它實施例中各個底座上可定位超過一個發光裝置 (作為個別晶粒或作為形成於單個晶粒上之多個裝置)。 在某些實施例中藉由在相鄰底座114-1及114-2之間形成 通道162-1、2形成可焊接層118。通道可為晶圓4〇〇中之一 通孔。在本實施例中通道162-1、2形成於底座114-1及114-2 之間的邊界上。 在某些實施例中藉由在通道162之壁上形成導電板層166 來鍍敷通道162。板層166可為金屬層或高度摻雜之半導體 層。在某些實施例中板層166使底座頂表面上之可焊接層 118耦接至底座底表面上之導電層。本文底座之頂表面界定 為晶粒110_接至底座114之表面。標題為"Sernic〇nduct〇r
Device And Method For Making The Same"之PCT公開案 WO99/59206中描述了 一種形成該等通道之方法。 圖5 §兒明了本發明之一實施例,其中在底座頂表面及底表 面上之可嬋接表面之間的電連接形成於底座之内而非底座 之外側。在圖5之裝置中,底座頂部上之可焊接區域(其上 女置有焊接球122-1及122-2)電連接至底座底部上之可焊接 區域(經由底座内之導電路徑附接至焊料接合點138)。底座 114可為例如具有若干不同區域之矽/玻璃複合底座。矽區 域m-2被金屬化層118^118·2包圍,其形成底座之頂表 95115.doc -13- 1377706 面與底表面之間的導電路徑。諸如ESD保護電路之電路可 形成於由金屬化層118-1及118-2包圍之矽區域η4·2中或其 匕石夕區域114-3中。該等其它石夕區域114_3亦可電接觸晶粒 110或板134。玻璃區域ιΐ4_ι電隔離不同矽區域。可由絕緣 區域135電隔離焊料接合點138,絕緣區域135可為例如介電 層或空氣。圖5之底座可包括圖3所示之整合式反射器罩。 矽/玻璃複合底座在美國專利6,15〇197及6,114,716與已出 版之美國專利申請案200300085416中有詳細描述。 圖6Α-6Ε說明了在圖5之底座上LED晶粒之形成及安裝。 如圖6A所示,生長矽晶圓6〇以包括諸如以上提及之esd保 護電路之任何所要電路。經由習知光罩及蝕刻步驟將孔。 形成於晶圓60内。如圖6B所示,導電層63(諸如一種金屬) 形成於晶圓60之上及孔61之内。接著可圖案化導電層 玻璃層62接著形成於晶圓go之上及孔61之内。 在圖6C中,移除玻璃層62之部分及晶圓6〇以曝露導電層 63。接著可圖案化晶圓下側上之導電層63且可附加並圖案 化額外導電層,結果形成圖所示之底座。可由介電層Μ 隔離不同導電區域63。一旦晶圓之下側被圖案化,可經由 互連件122將LED晶粒11 〇實際電連接至底座上之導電區域 63 〇 如圖6E所示,接著可將所安裝之LED晶粒可被選擇性塗 佈一發光材料層66,該發光材料層66包括諸如磷之發光材 料。可藉由例如模板印刷、絲網印刷、著色、電泳沈積、 喷射著色或靜電沈積來塗覆該發光材料層66。模板印刷 951l5.doc •14- 1377706 在2000年10月13曰申請之標題為"Stenciling Phosphor Layers on Light Emitting Diodes”之申請案第 09/688,053號 中有詳細描述。電泳沈積在美國專利第6,576,488號中有詳 細描述,該專利頒於2003年6月10日,標題為·’Using Electrophoresis to Produce a Conformally Coated Phosphor-Converted Light Emitting Semiconductor Structure”。兩篇申請案均以引用的方式併 入本文中。層66上可形成用於密封或保護發光材料之可選 用塗層67。可選用塗層可為例如環氧樹脂、聚矽氧或旋塗 式玻璃。在所要層被塗覆於所安裝之LED晶粒上之後,在 圖6E箭頭所示區域内之LED之間藉由切塊法可將矽/玻璃 複合底座切成個別裝置。 圖7說明了一具有在底座頂部及底部上的可焊接表面之 間的電連接之底座的替代實施例,該電連接被形成於底座 内而非底座外部。在圖7所示之裝置中,位於電連接至晶粒 下方之底座區域114-2為導電材料(諸如銅)之插塞。藉由諸 如矽區域114-3及114-1電分離導電插塞。諸如ESD保護電路 之電路可形成於矽區域114-1及114-3之中。圖7所示之底座 可包括圖3所示之積體反射器罩。 圖8A-8D說明了 LED晶粒在圖7所示之底座上之形成及安 裝。圖8A提供一矽晶圓,其被製造以包括諸如上述之ESD 保護電路之所要電路。如圖8B所示,通孔81形成於晶圓80 上待定位圖7所示之導電插塞之區域。如圖8C所示,接著將 導電材料填充於通孔81内。接著LED小晶粒110可安裝於晶 圓80上。在某些實施例中,導電插塞82延伸於晶圓80之頂 95ll5.doc -15- 部上且不需使用i連件122即可直接$接至LED小晶粒 110 °
在本發月之某些實施例中,上述安裝於表面可黏著底座 之LED係大功率裝置,意味其在高電流密度下運作。大 功率裝置之面積可大於彻χ4⑻一並可在至少5G 電,密度下運作。大功率裝置之-般尺寸大於或等於lxl mm之面積且電功率消耗大於或等於丄w。在該等裝置中, 必須仔細選定LED與底座之間及底座與其上安裝底座之裝 置之間的互連使得其能夠承受LED產生之熱量,但不要求 在可能損壞LED之溫度下軟溶。另外’咖通常安裝於底座 之上,接著在-單獨步驟中將底座安裝於另一結構。必須 仔,,,田選疋LED與底座之間的連接以承受用於製造底座與其 上女裝底座之裝置之間的連接所要求的溫度。與底座 之間合適之互連件實例包括Au七互連件、8〇%Au2〇%Sn 焊料、88% Au 12。/〇 Ge焊料、97% Au 3% Si焊料、95% 外 5% Sn焊料及90% Pb 1G% Sn焊料,其具有超過·。?之軟溶溫 度。底座與其上安裝底座之裝置之間合適之互連件實例包 括Pb-Sn共熔焊料、Ag_Cu_Sn焊料及以基於扑也之焊料, 其具有低於500卞之軟熔溫度。 在某些實施例中’上述安裝於表面可黏著底座之led具 有小於400x400 —之面積且可在約5誕與約_ mA之間 的電流下運作。 藉由焊料連接表面可黏著至其它裝置之LED底座(諸如 上ϋ圖2 3 5及7中之底座)具有若干優點。表面可黏著底 951I5.doc -16- 1377706 座具有改良(熱特性,與導線接合件底座相比更活躍、更 小且更易裝配。 底座與其上安裝底座之裝置之間的焊料接合點可改良 led底座組合之熱特性。商用LED通常由第ηι·ν族材料形 成。歷來在第III族氮化裝置之狀況下,由於製造高質量第 III族氮化層之難度’裝置之尺寸、裝置所承受之最大電流 密度以及裝置產生之光的量非常小。隨著製造技術的改 良,出現了能夠在更高電流密度下運作之更大裝置。通常, 隨著提供至該裝置之電流量的增加,由led產生之光的量 恰當地增加。然而,隨著提供至LED之電流量增加,該裝 置中產生之熱量亦增加。隨著在第m_ V族led内溫度上 升,最終可觀察到諸如結晶缺陷遷移、暗線形成、生長基 板裂開、半導體裝置層裂開及裝置接點分層等失效機構。 因此,特定LED底座或封裝用以避免產生額外熱量或自led 有效驅散熱量之能力限制了電流密度且因而限制了 led產 生之光的量。上述表面可黏著底座可以兩種方式改良LED 底座組合之熱特性。 第一,底座與其上安裝底座之裝置之間的大型焊料連接 在比導線接合件可能傳播之表面更大的表面上傳播供應至 發光裝置的電流’其減小了連接内之電流密度。較低電流 密度產生較少歐姆熱量。因此,大功率LED可相同材料形 成。 第二,焊料連接提供有效渠道以傳導開晶粒内由非輻射 性再組合產生之熱量,其進一步減少裝置之運作溫度。藉 95115.doc -17- 1377706 由有效傳導熱量遠離led,焊料接合點可增加可運作LED 電流密度,其可増加led產生之光的量。另外,導線接合 件本身易受熱量影響。使用焊料接合點取代導線接合件可 降低或消除與導線接合件相關之各種失效機構。詳言之, 焊料連接不像導線接合件那樣易於釋放其接點,其不變脆 且不融掉,引起電路徑中之斷開。 焊料接合點之另一優點係其並不較脆,不易受極端運作 條件(L括濕性環境、溫度衝擊及粗加工)之不利影響。具有 焊料接合點之LED不需像導線接合件裝置一樣裝配於封裝 中,導線接合件裝置要求封裝保護較脆導線接合件。相反, 可將LED以未封裝之形式提供至終端用戶且終端用戶可將 LED直接併入其產品中,例如,藉由在具體應用中直接將 其焊接至導線板上。 焊料接合點之置放不需要額外空間,而導線接合件需要 額外底座空間。舉例而言,除被LED覆蓋之底座部分外各 個導線接合件需要位於底座上的圓形接合襯墊,及包圍圓 形接合襯墊之額外底座材料以產生易於切成方塊狀之底座 (例如六角形或矩形)。通常,各個圓形空間直徑約為丨5〇 μπι。消除導線接合襯墊允許形成相對較小之裝置,或等效 地,允許在相同尺寸之晶圓上形成更多數目之裝置,其增 加了生產過程之良率。在一更小之裝置中,更少光自底座 反射,其引起較佳之更小光源尺寸,另外,更小底座需要 更少矽,其降低了底座成本。在某些實施例中,底座可小 於安裂於該底座上之LED之佔據面積。 95115.doc -18- 1377706 最後,當磷轉換LED安裝於導線接合式底座上時,底座 上之導線接合襯塾與碟層位於底座之同一側。因此,在鱗 沈積於LED上之後,必須將磷層圖案化以移除覆蓋導線接 合襯墊之鱗層。相反,表面可黏著底座之接點位於底座上 與磷層相對之側。因此,使用表面可黏著底座大幅度簡化 了在LED上塗佈磷之過程,因為不需圖案化磷層以曝露接 合襯墊。 以上討論之實施例僅為例示性的’其並不意欲限制本發 明。熟習此項技術者將認識到所述之實施例之各種變化亦 在本發明之範疇内。同樣地,本發明僅受下列申請專利範 圍限制。 【圖式簡單說明】 圖1說明了 一具有導線接合件之LED。 圖2說明了 一連接至一具有焊料接合點之板的LED底座 組合。 圖3說明了一在底座上具有反射井之LED底座組合。 圖4說明了 一具有通道之底座之晶圓。 圖5說明了一具有在底座内之通道内所提供之前與後底 座接點之間的連接的LED底座組合。 圖6A-6E s兒明了 一在圖5之底座上形成及安裝LED之方 法。 圖7 s兒明了一具有在底座内之通道内所提供之前與後底 座接點之間的連接的LED底座組合之替代實施例。 圖8A-8D說明了 一在圖7之底座上形成及安裝led之方法。 95115.doc •19- 1377706 【主要元件符號說明】 60 梦晶圓 61 子L 62 玻璃層 63 導電層 64 介電層 66 發光材料層 67 可選塗層 80 晶圓i 81 通孔 82 導電插塞 100 覆晶裝置 110 晶粒 114-3 ^區域 114-2 石夕區域 114-1 玻璃區域 114 底座 118-1, 118-2 可焊接層 122-1, 126-1, 122-2, 126-2 焊接球 122-2, 122-3 P型焊接球 122 互連件 130-1, 130-2 導線 132-1, 132-2 封裝引線 95115.doc -20- 1377706 133 反射器 134 導線板 138-1, 138-2 焊接區域 135 絕緣區域 138 焊料/焊料接合點 146 反射井 150 光搞合材料 154 η型可濕金屬層 158-1, 158- -2 Ρ型可濕金屬層 162-1, 162- -2 通道 166 導電板層 400 晶圓 95115.doc -21 ·

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  1. ^//706 十、申請專利範圍: 第093122563號專利申請案 中文申請專利範圍替換本(1〇〇年11月) ,裝置,其包含: 〉年刀月Λ日
    半導體發光裝置,其包含: 一 η型層; 一 Ρ型層; 一插入該η型層與該Ρ型層之主動區域; 電連接至該η型層之η型接點;及 一電連接至該ρ型層之ρ型接點; 其中该η型接點及該ρ型接點形成於該半導體發光裝 置之一相同侧;及 —底座’其包含: 位於該底座之一第一側上之第一導電區域及第二 導電區域; 位於該底座之一第二側上之第三導電區域及第四 導電區域; 半導體區域;及 —絕緣區域,其中該半導體發光裝置之該η型接點 與6亥Ρ型接點係電連接及物理連接至一覆晶構型之該底 座的該第一導電區域及第二導電區域。 如。a求項1之裝置,其中該第一導電區域及第二導電區域 包合之材料係選自一由金、銀、鎳、鉑及銅組成之群。 如明求項1之裝置,其中該第一導電區域及該第三導電區 域藉由一第一導電層電連接,而該第二導電區域及該第 四導電區域藉由一第二導電層電連接。 95115-1001H8.doc I3VVVU〇 4.如請求項3之裝置, 金屬層。 其中該第一導電層及該第二導電層係 導電層及該第二導電層係 5.如請求項3之裝置,其中該第一 高度摻雜之半導體層。 6.如明求項3之裝置 於該底座之外側。 7·如請求項3之裝置 置於該底座之内。 其中該第一導電層及該第二導電層位 其中該第一導電層及該第二導電層安 8. 如明求項7之裝置,其中該第一導電層及該第二導電層各 個至》部分地包圍該底座内半導體材料之-區域。 9. 如明求項7之裝置,其中該第一導電層及該第二導電層包 含銅。 1〇·如請求項1之裝置,其中該半導體發光裝置安裝於形成於 底座上之—井中。 11.如請求項1〇之裝置’其中該井之側面及底部之至少一部 分反射由該半導體發光裝置發射之光。 12_如請求項1〇之裝置,其中至少部分地以光耦合材料填充 該井。 13·如請求項1之裝置,其進一步包含形成於該半導體區域内 之電路。 14. 如請求項!之裝置,其中該絕緣區域包含玻璃。 15. 如請求項】之裝置,其進一步包含: 一板;及 一將該板連接至該第三導電區域及該第四導電區域之 95115.1001118.doc -2- 16.1377706 焊料接合點。 如-月求項1之裝置’其中該半導體發光裝置之面積大於約 400χ400 μιη2。 17. 18. 19. 20. 21. 22. 23. 24. 25. 如。月求項1之裝置’其中該半導體發光裝置能夠在至少% A/cm2之電流密度下運作。 如-月求項1之裝置,其中該半導體發光裝置之面積大於或 荨於約1 χ 1 mm2。 如吻求項1之裝置’其中該半導體發光裝置能夠在大於或 等於1 W之電功率消耗量下運作。 :明求項1之裝置,其中包括該第一導電區域及第二導電 區域之5亥底座之一表面不存在導線接合襯墊。 如靖求項1之裝置,其進一步包含一疊置於該半導體發光 裝置相對於該底座之一表面上的發光材料層。 如喷求項21之裝置,其中該發光材料層疊置於該半導體 發光裝置之一側表面上。 如請求項1之裝置,其中該第一導電區域、該第二導電區 域'該第三導電區域及該第四導電區域各包含可焊接層。 如請求項1之裝置,其中該半導體發光裝置之面積小於約 400x400 μιη2 0 如請求項1之裝置,其中該半導體發光裝置能夠在約5mA 與約1 〇〇 mA之間的電流下運作。 95115-1001118.doc
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JP5030372B2 (ja) 2012-09-19
US20050023548A1 (en) 2005-02-03
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JP5432234B2 (ja) 2014-03-05
EP1503433A3 (en) 2011-03-09

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