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WO1999059206A2 - Semiconductor device and method for making the device - Google Patents

Semiconductor device and method for making the device

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Publication number
WO1999059206A2
WO1999059206A2 PCT/IB1999/000818 IB9900818W WO1999059206A2 WO 1999059206 A2 WO1999059206 A2 WO 1999059206A2 IB 9900818 W IB9900818 W IB 9900818W WO 1999059206 A2 WO1999059206 A2 WO 1999059206A2
Authority
WO
Grant status
Application
Patent type
Prior art keywords
substrate
device
wafer
semiconductor
layer
Prior art date
Application number
PCT/IB1999/000818
Other languages
French (fr)
Other versions
WO1999059206A3 (en )
Inventor
Veen Nicolaas J. A. Van
Antonius J. M. Nellissen
Samber Marc A. De
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Abstract

A semiconductor device comprises a first substrate (10) whose top surface is provided with interconnected conductor patterns (31, 32 and 33), side faces and bottom surface. A second substrate (40) having an electric circuit (41) and connection pads (43) at a connection side (47) is mounted on the first substrate (10) with the connection side (47) facing the top surface (11) of the first substrate (10). The connection pads (43) and the first conductor pattern (31) are interconnected by means of solder bumps (45) which are located between the substrate (40) and the substrate (10).

Description

Semiconductor device and method for making the device.

The invention relates to a semiconductor device comprising a first substrate and at least one second substrate, the first substrate having a first main surface and a number of side faces, and the first substrate being provided with a first conductor pattern on said first main surface, - the second substrate being mounted on said first substrate and comprising an integrated circuit which is electrically connected to said first conductor pattern.

The invention further relates to a method for manufacturing such a semiconductor device.

The invention also relates to a portable electronic device such as a mobile communicator comprising such a semiconductor device.

Such a semiconductor device is known from EP-A-0 729 180. The known semiconductor device comprises a silicon substrate which is provided with a conductor pattern on a front side and a number of chips which are mounted on the same front side of the substrate by means of the so called 'flip-chip' mounting technique. The known semiconductor device is mounted on a printed circuit board with its front side facing the printed circuit board and the conductor pattern on the substrate is connected to a conductor pattern on the printed circuit board by means of solder bumps. A disadvantage of the known semiconductor device is that a recess has to be provided in the printed circuit board to accommodate the chips. Another disadvantage of the known semiconductor device is that the it is relatively large in comparison with the chips of the semiconductor device.

It is an object of the invention to provide a semiconductor device which is relatively small compared to the known semiconductor device and which can be electrically connected to a printed circuit board without bonding wires.

It is a further object of the invention to provide a method for manufacturing such a semiconductor device.

It is another object of the invention to provide a small portable electronic device.

The semiconductor device according to the invention is characterised in that at least one side face of the first substrate is provided with a second conductor pattern which is electrically connected to the first conductor pattern. Due to this measure, the semiconductor device can be contacted, for example by reflow soldering, via the second conductor pattern on the side faces of the first substrate, just like known surface mounted devices. Hence, electrical contact pads on the first main surface of the first substrate for contacting a printed circuit board are not required. As a result, the first substrate can be much smaller than the substrate of the known semiconductor device, and still carry the same second substrate or substrates so that the overall dimensions of the semiconductor device are reduced. Another advantage of the semiconductor device according to the invention is that it can be mounted on a printed circuit board with the second main surface of the first substrate facing the printed circuit board so that no recess in the printed circuit board is required to accommodate the second substrate and no bonding wires are required to connect the semiconductor device.

The measure as defined in dependent claim 2 has the advantage that the semiconductor device according to the invention can be manufactured at low cost, as will be explained hereafter with reference to the drawings. The measures as defined in dependent claim 3 have the advantage that the first substrate can be electrically connected to, for example, a printed circuit board by means of solder bumps between the second main surface of the substrate and the printed circuit board. As a result, the total area on the printed circuit board required to accommodate and connect the semiconductor device is further reduced. The measures as defined in dependent claim 4 have the advantage that the electrical connection of the first substrate to the second substrate does not require any area on the first substrate outside the second substrate.

The measure as defined in dependent claim 5 has the advantage that processes to apply conductor patterns on a silicon wafer are readily available. In addition, if the second substrate also comprises a silicon base, there is a perfect thermal correspondence between the two substrates.

The measure as defined in dependent claim 6 has the advantage that relatively large and/or simple components such as resistors, capacitors and coils can be made in a first process performed on the first substrate and that relatively small and/or complex components can be made in the second substrate. In this way both processes can be optimised and the overall cost minimised.

It is very advantageous to use the semiconductor device according to the invention in a portable electronic device such as a mobile communicator or a personal digital assistant because it is small and thin in comparison with known semiconductor devices. In addition, the first substrate is suitable for accommodating thin film passive components such as coils, so that bulky passive components and the space needed for connecting them to a printed circuit board are saved. In particular, the semiconductor device may be an antenna amplifier. By mounting the second substrate with its top side facing the first substrate, the electromagnetic radiation from this circuit is damped by the first and the second substrate. In addition, the coil or coils needed in such an antenna amplifier can be easily integrated in the first substrate as thin film components, so that the antenna amplifier can be constructed so as to be very small.

The method according to the invention comprises the steps of making a pattern of intermittent slots in a wafer,providing conductor patterns which extend from a main surface of the wafer to side faces defining the intermittent slots, mounting substrates onto the wafer, each substrate comprising an integrated circuit, and electrically connecting the integrated circuits to the conductor patterns and severing the wafer at the location of the intermittent slots so as to obtain individual devices. The method according to the invention is a very advantageous method for making a semiconductor device according to the invention, because all steps can be performed on wafer-scale i.e. entire wafers can be processed, which is much more cost effective and offers better quality control than processing individual devices. For making a pattern of intermittent slots, for example a method as described in US 3,693,302 (incorporated herein by reference) can be used. For providing a conductor pattern, a known lithographic process, for example as disclosed in WO 95/28735 (incorporated herein by reference) can be used. For such a lithographic process it is very advantageous if it can be performed on wafer-scale because the alignment of a lithographic mask is much easier for a whole wafer than for individual substrates. Also for applying and etching the conductive layer, for mounting substrates and, if required, for testing the devices, a wafer can be processed much easier than individual substrates or devices. After performing all steps on wafer-scale, the wafer is severed into individual devices, for example by breaking the wafer at the location of the slots by bending the wafer with a suitable tool or by standard dicing methods.

The measure of dependent claim 9 has the advantage that a wafer of a conductive material can be used.

The measure of dependent claim 10 has the advantage that silicon is widely used in lithographic processes and thin-film processing, so that existing processes can be used. The measure of dependent claim 11 has the advantage that intermittent slots can be made by using a mask of an organic material or a metal. Suitable powders are for example Al2O3 and SiO2 . Alternatively, the intermittent slots can be made by sawing, laser milling or wet or dry etching.

The measure of dependent claim 12 has the advantage that a very small and robust device is obtained. This robustness is even improved if the space between the wafer and the substrate comprising the integrated circuit is filled with a material like silicone resin. Optionally, the substrate comprising the integrated circuit can be covered with a glob-top.

The measure of dependent claim 13 has the advantage that the semiconductor device can be contacted via the second main surface. Patterning the conductor layer on the first main surface, on the side faces and on the second main surface can be done in separate steps but is preferably performed using a lithographic technique as described in WO 95/28735.

The measure of dependent claim 14 has the advantage that contact bumps are provided on wafer-scale so that the costs of the bumps are much lower than if they were applied in individual devices or at a printed circuit board on which the semiconductor device is to be mounted. The measures of dependent claim 15 have the advantage that a good solderable conductor pattern is obtained. Thickening the conductive layer galvanically is facilitated by these measures because the conductive layer can be used as a common electrode. After removal of the masking layer, the parts of the conductive layer which were covered with the masking layer can be easily removed, for example, by etching. The measure of dependent claim 16 has the advantage that the conductor pattern on the side faces can be easily applied.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereafter. In the drawings: Fig. l shows a diagrammatic cross-section of a wafer 1 provided with a powder blasting resist layer 2,

Fig.2 shows a diagrammatic representation of powder blasting slots 3 in the wafer 1 , Fig.3 shows a diagrammatic representation of the wafer 1 after the powder blasting resist layer 2 has been removed, Fig.4 shows a diagrammatic representation of the wafer 1 after a passivation layer 5, a conductive layer 7 and a resist layer 9 have been applied on the top surface 11, the side faces 12 and the bottom surface 13,

Fig.5 shows a diagrammatic representation of the wafer 1 during irradiation of the resist layer 9 through two masks 20 and 21, Fig.6 shows a perspective view of a detail of the wafer 1,

Fig.7 shows a top view of the silicon wafer 1 according to the first embodiment of the invention,

Fig.8 shows a bottom view of the silicon wafer 1 shown in Fig.7, and Fig.9 shows a side view of a semiconductor device after severing the wafer 1.

Fig.10 shows a second embodiment of the semiconductor device according to the invention,

Fig.11 shows a detail of the wafer 1 after galvanically thickening the conductive layer, Fig.12 shows the same detail as Fig.11 after removal of the masking layer and of non-thickened parts of the conductive layer,

Fig.13 shows a top view of an embodiment of the portable electronic device according to the invention, and

Fig.14 shows a cross-sectional view of the device shown in Fig.13. In a first embodiment of the method according to the invention, a silicon wafer 1 is provided with a powder blasting resist layer 2, for example ORDYL BF405 (TOKYO OHKA), as shown in Fig. l. Subsequently, the powder blasting resist is locally removed by known lithographic techniques at the location where slots 3 (see Fig.7) are desired, the powder blasting resist is hardened by postbaking and the wafer is subjected to powder blasting as shown in Fig.2. After slots 3 have been formed through the wafer 1 , the powder blasting resist layer 2 is removed so that the situation as shown in Fig.3 is obtained. The slotted wafer is coated from both sides with a 2 micrometer thick passivation layer 5 of 2 micrometer silicon nitride by means of PECND and a 0.01-0.1 micrometer thick conductive layer 7 of Ti and 0.1-1 micrometer Cu by means of a sputter process (see Fig.4). After application of the Ti/Cu layer the conductive layer 7 is thickened by galvanically growing 5 micrometer Cu. A resist layer 9, for example SHIPLEY ED 2100 is applied electrophoretically so that a top surface 11, a bottom surface 13 and side faces 12 defining the slots 3 are covered as shown in Fig.4.

The resist layer 9 is irradiated through masks 20 and 21 as shown in Fig.5, with beams 15 which subtend an acute angle with the normal to the top surface 11 and the bottom surface 13, so that the beams can reach the resist layer 9 at the location of the side faces 12. The masks 20 and 21 are designed such that a continuous radiation pattern is formed which extends from the top surface 11 via the side faces 12 to the bottom surface. After development of the resist layer 9, the conductive layer 7 is etched such that only parts of the conductive layer which are covered with resist remain. After removal of the resist layer 9, a number of conductor patterns 30 as shown in Fig.6, remain on the wafer 1. These conductor patterns comprise a first conductor pattern 31 on the top surface 11 of the wafer 1, a second conductor pattern 32 on the side face 12 of the wafer 1 and a third conductor pattern 33 on the bottom surface 13 of the wafer 1. The second conductor pattern 33 is electrically connected to the first conductor pattern 31 at the interface between the top surface 11 and the side face 12 and is electrically connected to the third conductor pattern 33 at the interface between the side face 12 and the bottom surface 13.

Fig.7 shows a top view of the silicon wafer 1 according to the first embodiment of the invention. The wafer 1 is provided with slots 3 and a conductor pattern 31 has been formed on the top surface 11. Substrates 40 have been mounted onto the wafer 1 using the so called "flip chip technique" (see Fig.9).

Fig.8 shows a bottom view of the silicon wafer 1 shown in Fig.7. The bottom surface 13 of the wafer 1 has been provided with a conductor pattern 33 which is connected to the conductor pattern 31 via the conductor pattern 32 as shown in Fig.6. Solder bumps 17 have been applied on the third conductor pattern 33 by means of screen printing.

Fig.9 shows a side view of a semiconductor device which results after breaking or dicing the wafer 1 into individual devices at the location of the slots. The semiconductor device comprises a first substrate 10 provided with the conductor patterns 31 , 32 and 33 which have been applied as described above. A substrate 40 having an electric circuit 41 and connection pads 43 at a connection side 47 is mounted on the substrate 10 with the connection side 47 facing the top surface 11 of the substrate 10. The connection pads 43 and the first conductor pattern 31 are interconnected by means of solder bumps 45 which are located between the substrate 40 and the substrate 10. Fig.10 shows a second embodiment of the semiconductor device according to the invention. This semiconductor device has been obtained as follows. A wafer 101 is covered on one main surface with an isolation layer 111 of SiN. Passive components R and L are provided on this isolation layer 111. The components R and L are covered with a second isolation layer 112 of SiN, after which intermittent slots 103 are made in the wafer 101 as described above. During the removal of the powder blasting resist (not shown), the passive components R and L are protected by the second isolation layer 112. Subsequently, a third isolation layer 113 of SiN is provided on all sides of the wafer 101 and contact holes 114 are etched through the layers 112 and 113. A thin layer 115 of CrCu is applied on all sides of the wafer 101 and into the contact holes 114 by means of sputtering. A patterned masking layer 117 (see Fig.11) is applied on top of the layer 115 and a thick layer 116 of 5 micrometers Cu and optionally 50 micrometers Sn is galvanically grown at the location where the CrCu layer 115 is not covered with the masking layer 117. The masking layer is removed and the exposed parts of the layer 115 are etched so that a pattern of conductors 116 remains (see Fig.12). Finally, flip chips 140 are mounted on the substrates 110 and the wafer 101 is severed into individual devices.

Fig.13 shows a top view of an embodiment of the portable electronic device according to the invention. A pager 60 is provided with a screen 61 and control knobs 62. Fig.14 shows a cross-section of the pager 60. The pager 60 is provided with a printed circuit board 63 and a semiconductor device 64 according to the invention. The device 60 can be constructed so as to be very small and thin because of the small dimensions of the semiconductor device 64.

It is to be noted that the invention is not limited to the embodiments described above. The first substrate may, for example, be a ceramic or a glass substrate. Also the resist layer 9 may be applied by other methods such as dip coating or spraying. Also multiple second substrates may be mounted on a first substrate.

Claims

CLAIMS:
1. A semiconductor device comprising a first substrate and at least one second substrate,
the first substrate having a first main surface and a number of side faces, and the first substrate being provided with a first conductor pattern on said first main surface, - the second substrate being mounted on said first substrate and comprising an integrated circuit which is electrically connected to said first conductor pattern, characterised in that at least one side face of the first substrate is provided with a second conductor pattern which is electrically connected to the first conductor pattern.
2. A semiconductor device as claimed in claim 1, characterised in that the first conductor pattern and the second conductor pattern are electrically connected at the interface between the first main surface and said at least one side face.
3. A semiconductor device as claimed in claim 2, characterised in that the first substrate comprises a second main surface opposite said first main surface, the second main surface is provided with a third conductor pattern, and the second conductor pattern and the third conductor pattern are electrically interconnected at the interface between the second main surface and said at least one side face.
4. A semiconductor device as claimed in claim 1, characterised in that the second substrate comprises electrical connection pads located at a main surface, and the second substrate is mounted on the first substrate with said main surface facing the first main surface of the first substrate, the connection pads and the first conductor pattern being interconnected by means of conductors which are located between the first substrate and the second substrate.
5. A semiconductor device as claimed in claim 1 , characterised in that the first substrate is a silicon substrate.
6. A semiconductor device as claimed in claim 5, characterised in that the first substrate comprises a further integrated circuit.
7. A portable electronic device such as a mobile communicator comprising a semiconductor device as claimed in any one of the claims 1 to 6.
8. A method for manufacturing a semiconductor device comprising the steps of
(a) making a pattern of intermittent slots in a wafer,
(b) providing conductor patterns which extend from a main surface of the wafer to side faces defining the intermittent slots,
(c) mounting substrates onto the wafer, each substrate comprising an integrated circuit, and electrically connecting the integrated circuits to the conductor patterns and
(d) severing the wafer at the location of the intermittent slots so as to obtain individual devices.
9. A method for manufacturing a semiconductor device as claimed in claim 8, characterised in that a passivation/isolation layer is applied between steps (a) and (b).
10. A method for manufacturing a semiconductor device as claimed in claim 8 or 9, characterised in that the wafer is a silicon wafer.
11. A method for manufacturing a semiconductor device as claimed in claim 8, characterised in that the slots are made by powder blasting.
12. A method for manufacturing a semiconductor device as claimed in claim 8, characterised in that said substrates are electrically connected to the conductor patterns by means of bumps.
13. A method for manufacturing a semiconductor device as claimed in claim 8, characterised in that the conductor patterns extend from the first main surface via a side face to a second main surface of the wafer, said second main surface being opposite to said first main surface.
14. A method for manufacturing a semiconductor device as claimed in claim 13, characterised in that contact bumps are provided on the second main surface of the wafer before performing step (d).
15. A method for manufacturing a semiconductor device as claimed in claim 8, characterised in that the conductor patterns are provided by: applying a conductive layer, providing a patterned masking layer on top of the conductive layer, thickening the conductive layer galvanically at the locations where the conductive layer is not covered by the masking layer, - removing the masking layer, removing non-thickened parts of conductive layer.
16. A method for manufacturing a semiconductor device as claimed in claim 8, characterised in that the grooves have a width which is larger than 0.5 times the thickness of the wafer.
PCT/IB1999/000818 1998-05-13 1999-05-06 Semiconductor device and method for making the device WO1999059206A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP98201564 1998-05-13
EP98201564.6 1998-05-13

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000548921A JP2002515651A (en) 1998-05-13 1999-05-06 The method of manufacturing a semiconductor device and a semiconductor device
KR20007000345A KR20010021782A (en) 1998-05-13 1999-05-06 Semiconductor device and method for making the device

Publications (2)

Publication Number Publication Date
WO1999059206A2 true true WO1999059206A2 (en) 1999-11-18
WO1999059206A3 true WO1999059206A3 (en) 2000-02-24

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FR2794570A1 (en) * 1999-06-04 2000-12-08 Gemplus Card Int Method for manufacturing a portable device circuitry integrated with electrical conduction paths
US6876008B2 (en) 2003-07-31 2005-04-05 Lumileds Lighting U.S., Llc Mount for semiconductor light emitting device
US6995402B2 (en) 2003-10-03 2006-02-07 Lumileds Lighting, U.S., Llc Integrated reflector cup for a light emitting device mount
JP2006054493A (en) * 2000-10-20 2006-02-23 Silverbrook Research Pty Ltd Multi-chip integrated circuit carrier
JP2006080555A (en) * 2000-10-20 2006-03-23 Silverbrook Research Pty Ltd Method of manufacturing integrated circuit carrier
JP2006080556A (en) * 2000-10-20 2006-03-23 Silverbrook Research Pty Ltd Integrated circuit carrier

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US5471090A (en) * 1993-03-08 1995-11-28 International Business Machines Corporation Electronic structures having a joining geometry providing reduced capacitive loading
US5648684A (en) * 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
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EP0343720A2 (en) * 1988-05-23 1989-11-29 Philips Electronics N.V. Semiconductor wafer and method of dividing it
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JP2002515651A (en) 2002-05-28 application
WO1999059206A3 (en) 2000-02-24 application

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