JP6062429B2 - 半導体デバイスを支持基板に接合する方法 - Google Patents
半導体デバイスを支持基板に接合する方法 Download PDFInfo
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Description
[(CTEgrowth−CTEstresscomp)(Tbond1−Troom )(Estresscomp)]/[(1−νstresscomp)(tstresscomp)]=[(CTEgrowth−CTEsupport)(Tbond2−Troom )(Esupport)]/[(1−νsupport)(tsupport)]であり、式中、CTEgrowthは、成長基板のCTE(サファイアでは約5.8ppm/℃)であり、CTEstresscompは、ストレス補償ウエハのCTE(Siでは約2.6ppm/℃)であり、CTEsupportは、支持基板ウエハのCTEであり、Troomは、室温、しばしば25℃であり、Tbond1は、デバイスウエハとストレス補償ウエハとの間のボンドの温度であり、Tbond2は、デバイスウエハと支持基板ウエハとの間のボンドの温度であり、Estresscompは、ストレス補償ウエハのヤング率であり、Esupportは、支持基板ウエハのヤング率であり、νstresscompは、ストレス補償ウエハのポアソン比であり、νsupportは、支持基板ウエハのポアソン比であり、tstresscompは、ストレス補償ウエハの厚さであり、tsupportは、支持基板ウエハの厚さである。スタックが、冷却中に平坦なままであるように、デバイスウエハ、支持基板ウエハ、及びストレス補償ウエハを含む接合されたスタックが、平衡を保たれたストレスを有するために、式(1)の両辺は、等しくなければならない。幾つかの実施形態において、小量のストレスが、接合されたスタックにおいて許容され得る。例えば、式1の両辺は、幾つかの実施形態において10%以下、幾つかの実施形態において5%以下、また幾つかの実施形態において1%以下異なっても良い。
Claims (16)
- 成長基板上に成長された半導体デバイスのウエハを提供することであって、前記半導体デバイスが、n型領域とp型領域との間に挟まれた発光層を含み、前記半導体デバイスのウエハが、第1の表面、及び前記第1の表面と反対側の第2の表面を有し、前記第2の表面が、前記成長基板の表面であることと、
前記第1の表面を第1のウエハに接合することであって、前記第1のウエハが本体を含むことと、
前記第2の表面を第2のウエハに接合することであって、前記第1及び第2のウエハが、それぞれ、前記成長基板と異なる熱膨張係数を有し、前記第2のウエハが、前記第1のウエハへの接合によって引き起こされる前記半導体デバイスのウエハにおける歪みを低減することと、
前記第1の表面を前記第1のウエハに接合した後で、前記n型領域に電気的に接続された金属を露出させるために、前記本体の全厚さを通して第1のビアをエッチングし、且つ前記p型領域に電気的に接続された金属を露出させるために、前記本体の全厚さを通して第2のビアをエッチングすることと、
前記第1及び第2のビアをエッチングした後で、前記第2のウエハを除去することと、
を含む方法。 - 第1の金属層を前記第1のビアに堆積させることと、第2の金属層を前記第2のビアに堆積させることとを更に含み、前記第1及び第2の金属層が、前記本体の前記第1の表面を、前記第1の表面と反対側の前記本体の第2の表面に電気的に接続する、請求項1に記載の方法。
- ボンディング層が、前記第2の表面と前記第2のウエハとの間に配置され、
前記第2のウエハを除去することが、前記ボンディング層が軟化する温度に前記ボンディング層を加熱することと、前記第2のウエハを前記成長基板からスライドさせるか又はリフトオフすることとを含む、請求項1に記載の方法。 - 前記第2のウエハを除去することが、前記第2のウエハを前記成長基板から研削することを含む、請求項1に記載の方法。
- 前記第2のウエハを除去した後で、前記成長基板を除去することを更に含む、請求項1に記載の方法。
- 前記第2のウエハを除去した後で、前記半導体デバイスのウエハをダイシングすることを更に含む、請求項1に記載の方法。
- 前記成長基板が、サファイアであり、前記第1及び前記第2のウエハが、シリコンである、請求項1に記載の方法。
- 前記第1及び前記第2のウエハが、実質的に同じ厚さである、請求項1に記載の方法。
- 前記第1の表面を第1のウエハに接合すること及び前記第2の表面を第2のウエハに接合することが、単一のボンディングステップで行われる、請求項1に記載の方法。
- 前記第1の表面を第1のウエハに接合することが、前記第2の表面を第2のウエハに接合する前に行われる、請求項1に記載の方法。
- 前記第1の表面を第1のウエハに接合することが、前記第2の表面を第2のウエハに接合した後で行われる、請求項1に記載の方法。
- 成長基板上に成長された半導体デバイスのウエハを提供することであって、前記半導体デバイスのウエハが、第1の表面、及び前記第1の表面と反対側の第2の表面を有し、前記第2の表面が、前記成長基板の表面であることと、
前記第1の表面を第1のウエハに接合することと、
前記第2の表面を第2のウエハに接合することであって、前記第2のウエハが、前記第1のウエハへの接合によって引き起こされる前記半導体デバイスのウエハにおける歪みを低減することと
を含み、
前記第2のウエハの厚さが、[(CTE growth −CTE second )(T bond1 −T room )(E second )]/[(1−ν second )(t second )]=[(CTE growth −CTE first )(T bond2 −T room )(E first )]/[(1−ν first )(t first )]を満たし、式中、CTE growth は、前記成長基板の熱膨張係数であり、CTE second は、前記第2のウエハの熱膨張係数であり、CTE first は、前記第1のウエハの熱膨張係数であり、T room は、25℃であり、T bond1 は、前記半導体デバイスのウエハと前記第2のウエハとの間のボンドのボンディング温度であり、T bond2 は、前記半導体デバイスのウエハと前記第1のウエハとの間の前記ボンドのボンディング温度であり、E second は、前記第2のウエハのヤング率であり、E first は、前記第1のウエハのヤング率であり、ν second は、前記第2のウエハのポアソン比であり、ν first は、前記第1のウエハのポアソン比であり、t second は、前記第2のウエハの厚さであり、t first は、前記第1のウエハの厚さである、
方法。 - 前記半導体デバイスが、n型領域とp型領域との間に挟まれたIII族窒化物発光層を含む、請求項1に記載の方法。
- 第1のボンディング層が、前記第1の表面と前記第1のウエハとの間に配置され、第2のボンディング層が、前記第2の表面と前記第2のウエハとの間に配置される、請求項1に記載の方法。
- 前記第1のボンディング層が、前記第2のボンディング層より高い温度で接合される、請求項14に記載の方法。
- 前記第1のウエハが、シリコンであり、永続的なボンディング材料によって前記第1の表面に接合され、
前記第2のウエハが、シリコンであり、一時的ボンディング材料によって前記第2の表面に接合され、
前記第2のウエハが、前記第1のウエハより厚い、請求項14に記載の方法。
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