TWI361437B - Test apparatus - Google Patents

Test apparatus Download PDF

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Publication number
TWI361437B
TWI361437B TW097107830A TW97107830A TWI361437B TW I361437 B TWI361437 B TW I361437B TW 097107830 A TW097107830 A TW 097107830A TW 97107830 A TW97107830 A TW 97107830A TW I361437 B TWI361437 B TW I361437B
Authority
TW
Taiwan
Prior art keywords
memory
defective
count
unit
bad
Prior art date
Application number
TW097107830A
Other languages
English (en)
Chinese (zh)
Other versions
TW200903506A (en
Inventor
Masaru Doi
Shinya Sato
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of TW200903506A publication Critical patent/TW200903506A/zh
Application granted granted Critical
Publication of TWI361437B publication Critical patent/TWI361437B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • G11C29/4401Indication or identification of errors, e.g. for repair for self repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208Error catch memory

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)
TW097107830A 2007-03-08 2008-03-06 Test apparatus TWI361437B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/054573 WO2008107996A1 (ja) 2007-03-08 2007-03-08 試験装置

Publications (2)

Publication Number Publication Date
TW200903506A TW200903506A (en) 2009-01-16
TWI361437B true TWI361437B (en) 2012-04-01

Family

ID=39737901

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097107830A TWI361437B (en) 2007-03-08 2008-03-06 Test apparatus

Country Status (5)

Country Link
JP (1) JPWO2008107996A1 (ja)
KR (1) KR101015488B1 (ja)
CN (1) CN101627445A (ja)
TW (1) TWI361437B (ja)
WO (1) WO2008107996A1 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4889792B2 (ja) * 2007-11-14 2012-03-07 株式会社アドバンテスト 試験装置
KR101312348B1 (ko) * 2009-03-10 2013-09-27 가부시키가이샤 어드밴티스트 시험 장치 및 시험 방법
TWI401691B (zh) * 2009-03-20 2013-07-11 Phison Electronics Corp 具快閃記憶體測試功能的控制器及其儲存系統與測試方法
JP2013007710A (ja) * 2011-06-27 2013-01-10 Advantest Corp 試験装置および試験方法
KR20150006167A (ko) 2013-07-08 2015-01-16 에스케이하이닉스 주식회사 반도체 시스템 및 그 리페어 방법
KR101980689B1 (ko) 2017-02-14 2019-05-22 주식회사 투엔 배송 중개서비스를 위한 역경매 기반 배송비 산정 방법
CN108121628B (zh) * 2017-12-19 2021-01-05 珠海市君天电子科技有限公司 一种读写速度的测试方法、装置及电子设备

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0933615A (ja) * 1995-07-19 1997-02-07 Advantest Corp 半導体メモリ試験装置のメモリ不良解析装置
JPH11102598A (ja) * 1997-09-29 1999-04-13 Toshiba Corp メモリ不良救済解析装置
JP2001014890A (ja) * 1999-06-30 2001-01-19 Mitsubishi Electric Corp 半導体装置および半導体装置のテスト方法
JP4601119B2 (ja) * 2000-05-02 2010-12-22 株式会社アドバンテスト メモリ試験方法・メモリ試験装置
JP2003228997A (ja) * 2002-02-05 2003-08-15 Mitsubishi Electric Corp 半導体記憶装置
JP4119417B2 (ja) 2004-11-15 2008-07-16 株式会社アドバンテスト 試験装置及び試験方法

Also Published As

Publication number Publication date
CN101627445A (zh) 2010-01-13
KR101015488B1 (ko) 2011-02-22
WO2008107996A1 (ja) 2008-09-12
KR20100004983A (ko) 2010-01-13
JPWO2008107996A1 (ja) 2010-06-10
TW200903506A (en) 2009-01-16

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MM4A Annulment or lapse of patent due to non-payment of fees