TWI355678B - Method of reducing sti divot formation during semi - Google Patents

Method of reducing sti divot formation during semi Download PDF

Info

Publication number
TWI355678B
TWI355678B TW094106204A TW94106204A TWI355678B TW I355678 B TWI355678 B TW I355678B TW 094106204 A TW094106204 A TW 094106204A TW 94106204 A TW94106204 A TW 94106204A TW I355678 B TWI355678 B TW I355678B
Authority
TW
Taiwan
Prior art keywords
forming
layer
nitride
stop layer
nitride polishing
Prior art date
Application number
TW094106204A
Other languages
English (en)
Chinese (zh)
Other versions
TW200535945A (en
Inventor
Douglas J Bonser
Johannes Groschopf
Srikanteswara Dakshina-Murthy
John G Pellerin
Jon D Cheek
Original Assignee
Globalfoundries Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Us Inc filed Critical Globalfoundries Us Inc
Publication of TW200535945A publication Critical patent/TW200535945A/zh
Application granted granted Critical
Publication of TWI355678B publication Critical patent/TWI355678B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW094106204A 2004-03-04 2005-03-02 Method of reducing sti divot formation during semi TWI355678B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/791,759 US7091106B2 (en) 2004-03-04 2004-03-04 Method of reducing STI divot formation during semiconductor device fabrication

Publications (2)

Publication Number Publication Date
TW200535945A TW200535945A (en) 2005-11-01
TWI355678B true TWI355678B (en) 2012-01-01

Family

ID=34911706

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094106204A TWI355678B (en) 2004-03-04 2005-03-02 Method of reducing sti divot formation during semi

Country Status (8)

Country Link
US (1) US7091106B2 (https=)
JP (1) JP2007526652A (https=)
KR (1) KR20060129037A (https=)
CN (1) CN1926679B (https=)
DE (1) DE112005000512B4 (https=)
GB (1) GB2426126B (https=)
TW (1) TWI355678B (https=)
WO (1) WO2005093825A1 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100568259B1 (ko) * 2004-12-14 2006-04-07 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 그 형성 방법
US20080204580A1 (en) * 2007-02-28 2008-08-28 Micron Technology, Inc. Method, apparatus and system providing imaging device with color filter array
US20090053834A1 (en) * 2007-08-23 2009-02-26 Vladimir Alexeevich Ukraintsev Use of scatterometry for in-line detection of poly-si strings left in sti divot after gate etch
KR100880227B1 (ko) * 2007-10-09 2009-01-28 주식회사 동부하이텍 플래시 메모리 소자의 제조방법
US7745320B2 (en) * 2008-05-21 2010-06-29 Chartered Semiconductor Manufacturing, Ltd. Method for reducing silicide defects in integrated circuits
US8546268B2 (en) 2009-04-30 2013-10-01 X-Fab Semiconductor Foundries Ag Manufacturing integrated circuit components having multiple gate oxidations
US8274114B2 (en) * 2010-01-14 2012-09-25 Broadcom Corporation Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region
US8283722B2 (en) 2010-06-14 2012-10-09 Broadcom Corporation Semiconductor device having an enhanced well region
US9123807B2 (en) 2010-12-28 2015-09-01 Broadcom Corporation Reduction of parasitic capacitance in a semiconductor device
US20120292735A1 (en) 2011-05-20 2012-11-22 GLOBALFOUNDRIES Singapore Pte.Ltd. Corner transistor suppression
US9263556B2 (en) * 2012-06-29 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide process using OD spacers
US8716102B2 (en) * 2012-08-14 2014-05-06 Globalfoundries Inc. Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process
US8603895B1 (en) 2012-09-11 2013-12-10 Globalfoundries Inc. Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence
US9219059B2 (en) 2012-09-26 2015-12-22 International Business Machines Corporation Semiconductor structure with integrated passive structures
JP6591347B2 (ja) 2016-06-03 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6629159B2 (ja) 2016-09-16 2020-01-15 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN111341724B (zh) * 2018-12-19 2022-11-04 上海新微技术研发中心有限公司 浅沟槽隔离工艺及浅沟槽隔离结构
KR102821368B1 (ko) * 2019-06-21 2025-06-17 삼성전자주식회사 반도체 소자 및 그 제조 방법
US12002707B2 (en) 2020-08-06 2024-06-04 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
CN113611604A (zh) * 2021-03-19 2021-11-05 联芯集成电路制造(厦门)有限公司 半导体元件的制作方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US98661A (en) * 1870-01-11 Ikank l
US5177028A (en) * 1991-10-22 1993-01-05 Micron Technology, Inc. Trench isolation method having a double polysilicon gate formed on mesas
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
US5665633A (en) * 1995-04-06 1997-09-09 Motorola, Inc. Process for forming a semiconductor device having field isolation
US5616513A (en) * 1995-06-01 1997-04-01 International Business Machines Corporation Shallow trench isolation with self aligned PSG layer
JPH098135A (ja) * 1995-06-26 1997-01-10 Toshiba Corp 半導体装置の製造方法
JP3125719B2 (ja) * 1997-07-28 2001-01-22 日本電気株式会社 半導体装置及びその製造方法
JP3053009B2 (ja) * 1997-09-29 2000-06-19 日本電気株式会社 半導体装置の製造方法
US6555476B1 (en) * 1997-12-23 2003-04-29 Texas Instruments Incorporated Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric
CN1219328C (zh) * 1998-02-19 2005-09-14 国际商业机器公司 具有改善了注入剂的场效应晶体管及其制造方法
JP3178416B2 (ja) * 1998-05-22 2001-06-18 日本電気株式会社 半導体装置の製造方法
US6599810B1 (en) * 1998-11-05 2003-07-29 Advanced Micro Devices, Inc. Shallow trench isolation formation with ion implantation
US6248641B1 (en) * 1999-02-05 2001-06-19 United Microelectronics Corp. Method of fabricating shallow trench isolation
JP2001185731A (ja) * 1999-12-24 2001-07-06 Toshiba Corp 半導体装置及びその製造方法
KR100346842B1 (ko) * 2000-12-01 2002-08-03 삼성전자 주식회사 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 디바이스및 그 제조방법
US6432797B1 (en) 2001-01-25 2002-08-13 Chartered Semiconductor Manufacturing Ltd. Simplified method to reduce or eliminate STI oxide divots
US20020142531A1 (en) * 2001-03-29 2002-10-03 Hsu Sheng Teng Dual damascene copper gate and interconnect therefore
US6673695B1 (en) * 2002-02-01 2004-01-06 Chartered Semiconductor Manufacturing Ltd. STI scheme to prevent fox recess during pre-CMP HF dip
JP4318892B2 (ja) * 2002-05-30 2009-08-26 富士通マイクロエレクトロニクス株式会社 電子装置の設計方法および製造方法
US6566215B1 (en) * 2002-06-06 2003-05-20 Chartered Semiconductor Manufacturing Ltd. Method of fabricating short channel MOS transistors with source/drain extensions

Also Published As

Publication number Publication date
GB2426126B (en) 2008-07-23
GB0617207D0 (en) 2006-10-11
CN1926679B (zh) 2010-10-06
JP2007526652A (ja) 2007-09-13
KR20060129037A (ko) 2006-12-14
DE112005000512T5 (de) 2007-01-11
GB2426126A (en) 2006-11-15
US20050196928A1 (en) 2005-09-08
US7091106B2 (en) 2006-08-15
TW200535945A (en) 2005-11-01
CN1926679A (zh) 2007-03-07
DE112005000512B4 (de) 2011-09-08
WO2005093825A1 (en) 2005-10-06

Similar Documents

Publication Publication Date Title
TWI355678B (en) Method of reducing sti divot formation during semi
JP4001866B2 (ja) 浅溝分離（ｓｔｉ）プロセス後のディボット形成を制限する方法
TWI255012B (en) Method of manufacturing a flash memory cell
JP4150661B2 (ja) Ｃｍｏｓトランジスタを製作するためのゲート・パターン形成用の３層ハードマスク
TW200522171A (en) Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
JPH1012718A (ja) トレンチ素子分離方法
JP2003008012A (ja) 隆起したソース／ドレーン領域を有するトランジスタを形成する方法
KR19990055121A (ko) 반도체 소자 제조 방법
JP3539483B2 (ja) 半導体装置の製造方法
KR100521707B1 (ko) 금속 게이트 상보성 금속 산화물 반도체 및 그 제조 방법
TW200411815A (en) Method of forming an isolation layer in a semiconductor devices
TWI251308B (en) Method of manufacturing flash memory device
US7361571B2 (en) Method for fabricating a trench isolation with spacers
JP2002359369A (ja) 半導体装置の製造方法
TWI337390B (en) Method for semiconductor device performance enhancement
TWI286798B (en) Method of etching a dielectric material in the presence of polysilicon
US6323112B1 (en) Method of fabricating integrated circuits
TWI244726B (en) Spacer approach for CMOS device
KR100503746B1 (ko) 반도체 소자의 제조방법
KR100617051B1 (ko) 반도체 소자의 제조방법
TW388923B (en) Method for producing self-aligned T-gate FET with gate oxide sidewall protection
US20130189821A1 (en) Methods for fabricating semiconductor devices with reduced damage to shallow trench isolation (sti) regions
CN115881620A (zh) 衬底结构的制造方法以及衬底结构
KR100430582B1 (ko) 반도체 소자의 제조 방법
KR100541704B1 (ko) 금속 살리사이드 구조를 갖는 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees