TWI354354B - - Google Patents

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Publication number
TWI354354B
TWI354354B TW094123950A TW94123950A TWI354354B TW I354354 B TWI354354 B TW I354354B TW 094123950 A TW094123950 A TW 094123950A TW 94123950 A TW94123950 A TW 94123950A TW I354354 B TWI354354 B TW I354354B
Authority
TW
Taiwan
Prior art keywords
conductive portion
semiconductor device
plating layer
layer
metal foil
Prior art date
Application number
TW094123950A
Other languages
English (en)
Other versions
TW200618212A (en
Inventor
Chikao Ikenaga
Kentarou Seki
Kazuhito Hosokawa
Takuji Okeyui
Keisuke Yoshikawa
Kazuhiro Ikemura
Original Assignee
Dainippon Printing Co Ltd
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dainippon Printing Co Ltd, Nitto Denko Corp filed Critical Dainippon Printing Co Ltd
Publication of TW200618212A publication Critical patent/TW200618212A/zh
Application granted granted Critical
Publication of TWI354354B publication Critical patent/TWI354354B/zh

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

1354354 η) 九、發明說明 【發明所屬之技術領域】 本發明是屬於表面安裝型的半導體裝 更詳而言之’是屬於無引線構造的表面安 置的技術領域》 【先前技術】 一般’半導體裝置是其構件之一使用 ’但爲了實現多針腳化，會要求引線架之 化。但’若引線本身的寬度縮小，則引線 導致因引線彎曲等而發生短路現象。因此 的間距’不得不使封裝體形成大型化。如 線架的半導體裝置會形成封裝體尺寸大且 而提案一種無引線架的影響，亦即所謂無 安裝型的半導體裝置。 [專利文獻1]特開平9-25201 4號公報 [專利文獻2]特開2001-210743號公幸1 圖9(a) (b)是表示記載於專利文 置。此半導體裝置的製造方法是首先在基 箔，以能夠在所定部份殘留金屬箔之方式 蝕刻之後，在具有與半導體元件1 02同 1 03 a (晶片焊墊）之上使用接合劑丨04來 1 02，且藉由金屬線1 〇5來進行半導體元 1 0 3 b的電性連接，利用金屬模來以密封程 置的技術領域， 裝型的半導體裝 金屬製的引線架 引線的間距微細 的強度會下降， ，爲了確保引線 此一來，使用引 厚。因應於此， 引線構造之表面 獻1的半導體裝 材1 0 ]貼附金屬 進行該金屬箔的 等大小的金屬箔 固著半導體元件 [牛102與金屬箔 过脂〗〇6進行傳 -5- (2) 1354354 送模製（transfer mold)(圖9(a))。最後，從基材 • ]〇1分離所被成形的密封樹脂106，藉此完成封裝體的半 - 導體元件（圖9(b))。但，藉此製造方法而取得的半 導體裝置，由於在半導體元件102有接合劑104及金屬箔 l〇3a (晶片焊墊M)附隨存在，因此由所欲小型且薄的半 導體裝置的立場來看，尙存在問題。 圖l〇(a) (b)是表示專利文獻2中所被記載的半 φ導體裝置。此半導體裝置是藉由其次的方法來製造。首先 ’取得一在基材的金屬板形成斗狀的凹溝201a的金屬板 201。其次’使用接合劑203來將半導體元件202固著於 金屬板20 1 ’然後在設計上必要的場所打線接合形成金屬 線2 04，以密封樹脂205來進行傳送模製（圖1() ( 3)) 。其次’硏磨金屬板201及接合劑203，且依設計尺寸與 密封樹脂205 —起切斷金屬板201，而取得半導體裝置（ 圖l〇(b))。但，在此製造方法中，所取得的半導體裝 φ置’由於在半導體元件202之下有接合劑層203或金屬板 201附隨存在’因此對於產業界所期望之薄型化的半導體 裝置而言，有其困難點。 如此一來，以往的製造方法難以取得薄型化的半導體 裝置。因此，爲了取得薄型化的半導體裝置，必須使半導 體元件（晶片）本身硏磨更薄’在該製造工程中容易發生 半導體元件的破裂或缺口，導致成本提高。 如此的一面密封型的半導體裝置，在晶片焊墊上搭載 半導體元件之後，會在該晶片焊墊上實施接地接合。此情 -6 - (3) (3)1354354 況，在與半導體元件的下面同一面上有接合部。由於半導 體元件與基板及密封樹脂的熱膨脹分別不同，因此從半導 體元件的下面外周部沿著密封樹脂與基板的界面而發生剝 離時，該剝離會使最終位於同一平面内的接地接合部的金 屬線也同時剝離，導致會有形成電性開啓的問題點。 【發明內容】 本發明是有鑑於這樣的問題點而硏發者，其目的是在 於提供一種可低成本且薄型化的無引線構造，高可靠度的 表面安裝型的半導體裝置，以及使用於該製造的半導體裝 置製造用基板及其製造方法。 本發明之半導體裝置的特徵係具備： 晶片焊墊； 半導體元件，其係搭載於晶片焊墊上，且具有電極； 複數個導電部，其係配置於晶片焊墊的周圍； 金屬線，其係連接半導體元件的電極與導電部；及 密封樹脂，其係至少密封導體元件，導電部及金屬線 ♦ 又，導電部係具有金屬箔，及設置於金屬箔的i下兩 側的導電部電鍍層； 晶片焊墊具有設置於與導電部的下側的導電部電鍍層 同一平面的晶片焊墊電鍍層； 導電部的下側的導電部電鍍層與晶片焊墊的晶片焊墊 電鍍層係其背面會往密封樹脂的外方露出 (4) 1354354 本發明之半導體裝置的特徵爲：晶片焊墊具有在内部 * 形成凹部的土堤部，該土堤部具有導電部的金屬箔及設置 . 於分別與上下兩側的導電部電鍍層同一平面的金屬箔及上 下兩側的電鍍層，且土堤部的下側的電鍍層係於晶片焊墊 電鍍層一體形成，半導體元件係配置於土堤部的凹部内， 半導體元件的電極與土堤部會藉由追加金屬線來連接。 本發明之半導體裝置的特徵爲：半導體元件的電極係 φ藉由金屬線來與導電部的上側的導電部電鍍層連接，且藉 由追加金屬線來與土堤部的上側的電鍍層連接。 本發明之半導體裝置的特徵爲：導電部的上下兩側的 導電部電鍍層係分別具有含貴金屬電鍍層的多層構成。 本發明之半導體裝置的特徵爲：導電部及土堤部的中 央的金屬箔係對上下兩側的導電部電鍍層成蜂腰狀。 本發明之半導體裝置的特徵爲：導電部的下側的導電 部電鍍層，土堤部的下側的電鍍層，及晶片焊墊電鍍層皆 φ從密封樹脂往外方突出。 本發明之半導體裝置的特徵爲：在土堤部設置密封樹 脂通過用的通路。 本發明之半導體裝置製造用基板，係用以製造半導體 裝置的半導體裝置製造用基板，其特徵爲具備： 接合薄板，其係具有基材層，及基材層上的接合劑層 y 晶片焊墊，其係設置於接合薄板的接合劑層上；及 複數個導電部，其係配置於晶片焊墊周圍； -8- (5) 1354354 又，導電部係具有金屬箔，及設置於金屬箔的上下兩 * 側的導電部電鍍層； . 晶片焊墊具有設置於與導電部的下側的導電部電鍍層 同一平面的晶片焊墊電鍍層。 本發明之半導體裝置製造用基板的特徵爲：晶片焊墊 具有在内部形成凹部的土堤部，該土堤部具有導電部的金 屬箔及設置於分別與上下兩側的導電部電鍍層同一平面的 φ金屬箔及上下兩側的電鍍層： 土堤部的凹部爲半導體元件用的凹部。 本發明之半導體裝置製造用基板的特徵爲：導電部的 上下兩側的導電部電鍍層係分別具有含貴金屬電鍍層的多 層構成。 本發明之半導體裝置製造用基板的特徵爲：導電部及 土堤部的中央的金屬箔係對上下兩側的導電部電鍍層成蜂 腰狀。 φ 本發明之半導體裝置製造用基板的特徵爲：在土堤部 設置密封樹脂通過用的通路。 本發明之半導體裝置製造用基板的特徵爲：接合薄板 的基材層係成金屬製。 本發明之半導體裝置用基板的製造方法，係半導體裝 置製造用基板的製造方法，其特徵爲具備： 準備金屬箔之工程； 在對應於金屬箔的導電部的部份，及對應於金屬箔的 晶片焊墊的部份，分別設置部份電鍍層之工程： -9- (6) (6)1354354 將設有部份電鍍層的金屬箔的下側貼附於具有基材層 與接合劑層的接合薄板的接合劑層側之工程； 以部份電鍍層作爲阻絕層來蝕刻金屬箔，藉此形成具 有金屬箔及設置於金屬箔的上下兩側的導電部電鍍層之導 電部，且形成具有設置於與導電部的下側的導電部電鍍層 同一平面的晶片焊墊電鍍層之晶片焊墊之工程；及 加工接合薄板，而來決定接合薄板的外形之工程。 本發明的半導體裝置爲不使用引線架的無引線構造， 且謀求在半導體元件下僅存在晶片焊墊電鍍層的薄型化。 又，由於接地接合部位於比其平面更高的位置，因此即使 從半導體元件的下面發生剝離，也不會對接地接合部造成 影響，可防止電性開啓，發揮提高可靠度的效果。 【實施方式】 以下，一邊參照圖面一邊詳細說明本發明的實施形態 〇 圖1是是以縱剖面來顯示本發明的半導體裝置之一例 的槪略構成圖。圖2是省略其金屬線以透視狀態來平面顯 示圖1的半導體裝置之說明圖，該圖2的A— A剖面會對 應於圖1。 如圖1所示，半導體裝置P具備： 晶片焊墊20 ; 半導體元件30，其係搭載於晶片焊墊20上，且具有 電極3 0a; -10- (7) (7)1354354 複數個導電部10，其係配置於晶片焊墊20的周圍； 金屬線3，其係連接半導體元件30的電極30與導電 部1 〇 ;及 密封樹脂40，其係至少密封半導體元件30，導電部 1 〇及金屬線3。 其中，導電部1〇具有：由銅或銅合金所構成的金屬 箔1，及設置於該金屬箔1的上下兩側的導電部電鍍層2 ’ 2。並且，晶片焊墊20具有設置於與導電部1〇的下側 的導電部電鍍層2同一平面的晶片焊墊電鍍層2b，在此 晶片焊墊電鍍層2b上搭載有半導體元件30。 亦即，晶片焊墊20具有土堤部21，該土堤部21形 成有用以在内部收容半導體元件30的凹部22，土堤部21 具有：設置於與導電部10的金屬箔1同一平面的金屬箔 la，及於金屬箔la的上下兩側設置於與導電部1〇的導電 部電鍍層2，2同一平面的電鍍層2a，2a。 如上述，導電部10的金屬箔1是由銅或銅合金所構 成，土堤部21的金屬箔la是由與導電部10的金屬箔1 同一材料所構成。 又，土堤部21的上下兩側的電鍍層2a，2a是由與導 電部10的上下兩側的導電電鍍層2，2同一材料所構成。 如此，晶片焊墊20的土堤部2〗的層構成2a，la， 2a是形成與導電部10的層構成2’ 1，2大略相同。 又，晶片焊墊20的土堤部21的下側的電鍍層2a是 與晶片焊墊電鍍層2b —體形成。 -11 - (8) 1354354 半導體元件30是被收容於藉由晶片焊墊 . 21所圍繞的凹部22内，半導體元件30的電 • 電部1〇的上側的導電部電鍍層2會藉由金屬 連接，半導體元件30的電極30a與晶片焊墊 21的上側的電鍍層2a會藉由金屬線（追加途 電性連接而進行接地接合。 又’藉由密封樹脂40來密封半導體元件 Φ 10，金屬線3 ’4。晶片焊墊20的晶片焊墊電 堤部21的下側的電鍍層2a，及導電部1〇的 部電鍍層2，其背面會從密封樹脂40來露出 最好晶片焊墊20的晶片焊墊電鍍層2b，土堤 側的電鍍層2a，及導電部1〇的下側的導電部 僅該厚度量自密封樹脂40突出。 另外’導電部10的上下兩側的導電部電彳 土堤部2 1的上下兩側的電鍍層2 a，2 a，及晶 $層2b皆是具有含貴金屬電鍍層的多層構成。 又’由於此無引線構造的半導體裝置P在 30之下僅存在晶片焊墊電鍍層2b，因此可提 薄型化且可靠度高的半導體裝置。又，如圖 10及晶片焊墊20的土堤部21是中央的金屬 導電部電鍍層2及電鍍層2a成蜂腰狀（中間 導電部電鍍層2及電鍍層2a會形成突出狀態 出部份2，2a會在密封樹脂40中發揮固定（ 果，因此導電部I 〇及晶片焊墊20與密封樹脂 2〇的土堤部 極30a與導 線3來電性 2〇的土堤部 ί屬線）4來 30，導電部 鍍層2 b，土 下側的導電 至外方，且 :部21的下 :電鍍層2， 渡層2，2， 片焊墊電鍍 半導體元件 供一種能夠 示，導電部 范1 ， la對 變細），且 。由於此突 anchor )效 40的接合 -12- (9) 1354354 強度會變高。並且，導電部10的導電部電鍍層2，晶片 • 焊墊2〇的土堤部21的電鍍層2a，及晶片焊墊電鍍層2b • 會形成從背面側突出的狀態，亦即形成支座（stand-off ) 的狀態，因此在半導體裝置P的安裝時，可防止因安裝基 板上的凹凸或異物而造成導電部（端子）浮起，可提高安 裝時的可靠度。又，亦具有防止焊錫膏被壓碎而產生短路 〇 φ 圖3(a) —（d)是表示圖1所示之半導體裝置的製 造方法的工程圖，以下根據該圖來說明製造的程序。 首先，如圖3(a)所示，準備一接含薄板50，該接 合薄板50具有基材層51及設置於基材層51上的接合劑 層52，在該接合薄板50的接合劑層52上形成晶片焊墊 20，該晶片焊墊20具有複數個導電部10及形成有凹部 22的土堤部21，而製成一基板B。如圖示，導電部10及 晶片焊墊20的土堤部21具有分別突出於上下的突出部份 φ 2，2a，有關形成如此導電部1 0及晶片焊墊20的基板作 成工程會在往後敘述。 其次，如圖3 ( b )所示，將半導體元件3 0設定於晶 片焊墊20的凹部22中，在晶片焊墊20的晶片焊墊電鍍 層2b上使用銀膏（paste)、晶片黏著薄膜（Die Attach Film)等市售的晶片黏著（Die Attach)材來固定半導體 元件3 0之後，以金屬線4來接地接合土堤部21的上面與 半導體元件30的電極30a，且藉由金屬線3來電性連接 導電部10的上面與半導體元件30的電極30a。由於如此 -13- (10) 1354354 在晶片焊墊電鍍層2b上固著半導體元件30，因此 • 的半導體裝置相較之下，可形成厚度100〜200微 . 型化。 其次，如圖3 ( c )所示，以密封樹脂40來密 體元件30，金屬線3, 4，導電部10及晶片焊墊 於接合薄板50上形成半導體裝置。密封樹脂40的 藉由通常的傳送模製法，而利用金屬模來進行。在 φ時，爲了使晶片焊墊20的凹部22之密封樹脂40 佳，可於土堤部21設置圖2所示那樣的通路21ί 而言，如圖4(a)那樣，在對傳送樹脂的流向X 直角方向的土堤部21設置通路21a，或如圖4(t 去除直角方向的土堤部21本身，或如圖4(c)那 與流向X呈直角方向的雙方土堤部2]設置複數 21a，藉此可使密封樹脂40的迴轉變佳。在該等的 a)〜（c)中，右側與下側的圖是由各方向來看的 Φ 。另外，在模製後，因應所需，進行密封樹脂40 化加熱。後硬化加熱，可在後述的接合薄板5 0的 或之後。接著，如圖3 ( d )所示，由密封樹脂4 0 接合薄板50,而取得圖1所示的半導體裝置P。 圖5(a) -（e)是表示上述基板作成工程， 接合薄板50的接合劑層52上形成複數個導電部 片焊墊20之程序。以下說明該工程。 準備導電部及晶片焊墊的素材，亦即由銅或銅 構成的金屬箔60。由強度的觀點，此金屬箔60爲 與以往 米的薄 封半導 20，而 密封是 此模製 的迴轉 。具體 而言呈 )那樣 樣，在 個通路 圖4 ( 側面圖 的後硬 分離前 來分離 亦即在 〇及晶 合金所 使用厚 -14- (11) 1354354 度0·01〜0.11 nm者。又，首先，在金屬箔的兩面貼合乾 • 薄膜阻絕層，如圖5 ( a )所示，藉由光蝕刻微影法，以 . 和導電部及晶片焊墊的形狀相反的圖案來分別使金屬箔 60兩面的乾薄膜阻絕層61圖案化。 其次，如圖5 ( b )所示，以乾薄膜阻絕層61作爲光 罩，將部份電鍍層62設置於對應於導電部10的金屬箔 60的上下兩側，且將部份電鍍層62設置於對應於晶片焊 φ墊的形狀的金屬箔60的上下兩側，如圖5(c)所示*去 除薄膜阻絕層61。此部份電鍍層62，如圖6的擴大圖所 示，是由具有作爲銅的擴散阻擋層63的鎳電鍍層，及設 置於該擴散阻擋層63上的貴金屬電鍍層64之多層構成所 形成。在此，使用於貴金屬電鍍層64的貴金屬，至少爲 Au，Ag，Pd的其中一個。又，貴金屬電鍍層64可以1層 或2層以上來構成。 就部份電鍍層62的具體例而言’例如有在作爲擴散 Φ阻擋層63之電鍍厚5微米的鎳電鍍上’重疊作爲貴金屬 電鍍層64之電鍍厚0.1微米的鈀電鍍’及電鍍厚〇·〇5微 米的金電鍍層而形成之形態。當然並非限定於此，可按照 所製造之半導體裝置的要求，以各種的組合及厚度來形成 ，但部份電鍍層62的總厚是以0.1〜程度爲適。 接著，如圖5(d)所示，一邊將對應於導電部〗〇及 晶片焊墊20而使部份電鍍層62部份形成於表背的金屬箔 80加壓於接合薄板50的接合劑層52側’—邊在部份電 鍍層6 2埋入接合劑層5 2的狀態下貼附。而且’在此貼附 -15- (12) 1354354 的狀態下，如圖5 ( e )所示，以部份電鍍層62作爲阻絕 • 層來蝕刻金屬箔60，形成由金屬箔1及設置於該金屬箔1 . 的上下兩側的導電部電鍍層2，2所構成的導電部10，且 形成具有：由金屬箔la及設置於該金屬箔la的上下兩側 的電鍍層2a，2a所構成的土堤部21 ’及晶片焊墊電鍍層 2b之晶片焊墊20。此情況’藉由蝕刻金屬箔60的側面 60a，如圖示形成一在金屬箔60的上下設置由部份電鍍層 φ 62所構成的突出部份之形狀。如此’在完成金屬箔60的 蝕刻工程之後，藉由沖壓加工等的切斷手段來進行接合薄 板50的外形加工，取.得半導體裝置製造用基板B。 圖7是以縱剖面來顯示本發明的半導體裝置的其他例 之槪略構成圖。該圖7所示的半導體裝置P與圖1的半導 體裝置P相較之下，是形成省略晶片焊墊20的土堤部21 之構造，接地接合4或電源接合3是被連接至從晶片焊墊 20獨立的導電部10。如此的構造亦與圖1的半導件裝置 φ P同様可提供一種能夠薄型化且高可靠度的半導體裝置。 另外，本發明之半導體裝置的製造方法是集中複數個 半導體裝置來製造爲實用。圖8是表示該例。該圖8是表 示半導體裝置製造用基板B的平面圖模式説明圖’在接合 薄板50的上面，以1個晶片焊墊20及形成於其周圍的導 電部10作爲1個區塊70，該區塊70會被斗狀多數形成 。在圖8中，例如，接合薄板50的寬度（W )爲65 mm ，經由所定的工程在接合薄板50上形成複數個區塊70， 連續性的製作捲於滾筒的基材。以能夠在其次的半導體元 -16· (13) 1354354 件搭載工程，樹脂密封工程形成必要的區塊數之方式來適 ' 當地切斷如此取得之寬度65 mm的半導體裝置製造用基 - 板B而使用。在如此一次樹脂密封複數個半導體元件時， 是在樹脂密封後分離接合薄板之後，以切割機切割或沖壓 來切斷成所定的尺寸，而形成單片化，藉此取得半導體裝 置。 本發明之半導體裝置的製造方法中所使用的接合薄板 φ 50，最好是樹脂密封工程終了爲止卻實地固著於半導體元 件30或導電部20，且從半導體裝置Ρ分離時可容易剝離 。如此的接合華板50，如前述具有基材層51及接合劑層 5 2。基材層5 1的厚度並無特別加以限制，通常爲丨2〜 200#m程度，更理想爲50〜150ym。又，接合劑層52 的厚度並無特別加以限制，通常爲1〜50 # m程度，更理 想爲5〜20// m。 又’就接合薄板50而言，最好是使用其基材層51之 讀•於200 °C的彈性率爲1.0 GPa以上，且接合劑層52之於 200 °C的彈性率爲0_1 MPa以上者。此外，彈性率的測定 詳細是根據實施例所記載的方法β 在被施以打線接合等的半導體元件搭載工程中，溫度 是被放置於大略150〜200 °C程度的高溫條件。因此，在接 合薄板50的基材層51及接合劑層52會被要求能夠耐此 溫度的耐熱性。由該觀點來看，基材層51最好是使用在 200°C之彈性率爲1.0 GPa以上，更理想爲1() 〇pa以上者 。基材層51的彈性率’通常是以1〇 GPa〜1〇〇〇 GPa程 -17- (14) 1354354 度爲理想。又，接合劑層52最好是使用彈性率爲0.1 MPa以上，更理想爲0.5 MPa以上，最理想爲1 MPa以上 • 者。接合劑層52的彈性率，通常是以0.1〜100 MPa程度 爲理想。該彈性率的接合劑層52是在半導體元件搭載工 程等中難以引起軟化•流動，可形成更安定的結線。 又，接合劑層52爲使用彈性率高者，藉此於圖5(d )所示的工程中加壓貼合下，導電部電鍍層62的部份會 鲁埋設於接著劑層52中，在圖3(d)所示的最終階段，位 於導電部10與晶片焊墊20的下側之導電部電鍍層2，電 鍍層2a及晶片焊墊電鍍層2b可形成由密封樹脂40的表 面突出之所謂支座（stand-off )的狀態，具有提高半導體 裝置安裝時的可靠度之效果。 接合薄板50的基材層51可爲有機物或無機物，但若 考量搬送時的處理性，模製時的彎曲等，則最好使用金屬 箔。如此的金屬箔，例如有SUS箔，Ni箔，A1箔，銅箔 # ，銅合金箔等，但若由可價格便宜地取得及種類豐富的觀 點來看，可選擇銅或銅合金。又，形成如此基材層51的 金屬箔，爲了確保與接合劑層52的固定性，最好一面施 以粗化處理。粗化處理的手法，可使用以往公知的噴沙法 等之物理性的粗化手法，或者蝕刻，電鍍等之化學性的粗 化手法。 形成接合薄板5 0的接合劑層5 2之接合劑並無特別加 以限定，但最好是使用環氧樹脂，環氧硬化劑，含有彈性 體的熱硬化性接合劑。在熱硬化性接合劑時，通常，基材 -18- (15) 1354354 的貼合可在未硬化之所謂的B階段（stage )狀態，亦即 ' 150°C以下的較低溫進行貼合，且於貼合後使硬化，藉此 - 可提高彈性率，使耐熱性提升。 在此，就環氧樹脂而言，例如有縮水甘油胺型環氧樹 脂，雙酚F型環氧樹脂，雙酚A型環氧樹脂，雙酚漆用 酚醛型環氧樹脂，甲酚漆用酚醛型環氧樹脂，雙酚型環氧 樹脂，萘型環氧樹脂，脂肪族環氧樹脂，脂環族環氧樹脂 φ ，雜環式環氧樹脂，含螺環之環氧樹脂，鹵化環氧樹脂等 ，可單獨使用，或混合2種以上。就環氧硬化劑而言，例 如有各種咪唑系化合物及其衍生物，胺系化合物，雙氰胺 ，肼化合物，苯酚樹脂等，可單獨使用，或混合2種以上 。又，就彈性體而言，例如有丙烯酸樹脂，丙烯腈丁二烯 共聚物，苯氧樹脂，聚醯胺樹脂等，可單獨使用，或混合 2種以上。 又，對接著劑層52的試驗用金屬箔之接合力最好爲 • 0.1 〜15 N/20 mm。更理想爲 0.3 〜15 N/20 mm。在此 ，接合力可依據導電部的大小來適當選擇於上述範圍內。 亦即，導電部的尺寸大時，接合力設定成較小，導電部的 尺寸小時，接合力設定成較大。具有此接合力的接合薄板 具有適度的接合力，在基板作成工程〜半導體元件搭載工 程中，固著於接合劑層的導電部不易發生偏移。並且’在 薄板分離工程中，來自半導體裝置之接合薄板的分離性良 好，可減少對半導體裝置的損傷。另外，接合力的測定詳 細是根據實施例的記載方法。 -19- (16) 1354354 又’因應所需’可對接合薄板50賦予靜電防止功能 •。對接合薄板50賦予靜電防止功能的方法，例如有在基 .材層51，接合劑層52混合帶電防止劑，導電性塡充物之 方法。又’有在基材層51與接合劑層52的界面，或基材 層51的背面塗佈帶電防止劑之方法。藉由賦予該靜電防 止功能’可抑止從半導體裝置分離接合薄板時發生的靜電 〇 φ 帶電防止劑，只要是具有靜電防止功能者即可，並無 特別加以限制。具體而言，例如可使用丙烯系兩性，丙烯 系正離子，順酐-苯乙烯系陰離子等的界面活性劑等。帶 電防止層用的材料，具體而言，例如有邦地普PA,邦地 普PX，邦地普P ( Konishi Co.，Ltd製）等。又，導電性 塡充物可使用慣用者，例如，Ni，Fe，Cr，Co，Al，Sb ，Mo’ Cu’ Ag’ Pt’ Au等的金屬，該等的合金或氧化物 ’碳黑等的碳等等。該等可單獨或組合2種以上使用。導 #電性塡充物可爲粉體狀或纖維狀。此外，在接合薄板中可 添加老化防止劑，顔料，可塑劑，充塡劑，黏著賦予劑等 以往公知的各種添加物。 〔實施例1〕 〔接合薄板的製作〕 將雙酣 Α 型環氧樹脂（Japan Epoxy Resins Co.，Ltd. 製「埃比考特1002」）100重量部，丙烯腈丁二烯共聚物 (日本ΖΕΟΝ Corporation製「倪波爾1 072：!」）35重量 -20- (17) 1354354 部’苯酚樹脂（荒川化學社製「P-180」）4重量部，咪 ' 唑系化合物（四國法英社製「C11Z」）2重量部溶解於甲 ' 基乙基甲酮3 50重量部，取得接合劑溶液。予以塗佈於厚 度 1〇〇 // m 的一面粗化銅合金箔（JAPAN ENERGY CORPORATION 公司製「Β Η Y -1 3 B - 7 0 2 5」）之後，使於 1 50°C下乾燥3分鐘，藉此取得一形成厚度15/im的接合 劑層之接合薄板50。此接合薄板50的接合劑層52的硬 φ化前之於100°C的彈性率爲2.5x10 ―3 Pa，硬化後之於200 °C 的彈性率爲4·3 MPa，對銅箔的接合力爲12 N/ 20 mm。 另外’作爲基材層51使用的銅箔之於200 °C的彈性率爲 1 3 0 GPa。 〔半導體裝置製造用基板的製作〕 首先，在厚度40/zm的銅箔（「Olin 7025」）60的 兩面層疊乾薄膜阻絕層61 (東京應化公司製「歐弟爾 φ AR3 3 0」）。然後，藉由光蝕刻微影法，以和導電部相反 的圖案來使該乾薄膜阻絕層圖案化。其次，以所被圖案化 的乾薄膜阻絕層作爲光罩，在銅箔的兩面依次施以鎳電鍍 與Au電鍍，而形成導電部電鍍層62，然後，去除乾薄膜 阻絕層。接著，在接合薄板5 0經由接合劑層5 2側來貼附 部份配置有鎳電鍍層與Au電鍍層的積層物。而且，以電 鍍部與接合劑層間不會形成間隙之方式來充分地加熱加壓 。其次，在此貼附狀態下，以Au電鍍層作爲阻絕層來蝕 刻銅箔60，而形成導電部1 0及晶片焊墊20。在此蝕刻加 -21 - (18) 1354354 工時，亦蝕刻銅箔60的側面，藉此在銅箔的上下 • Au及鎳所構成的突出部份60。最後，藉由沖壓加 工接合薄板的外形。 而且，以圖8的例（W爲65 mm)所示的圖案 合薄板50上形成導電部及晶片焊墊。在1個區塊 2所示的圖案來形成導電部10及晶片焊墊20。 φ 〔半導體元件的搭載〕 將試驗用的銘蒸著砂晶片（6 mmx6 mm) 30 上述接合薄板50之晶片焊墊20的凹部22內。具 ，使用分配器在晶片焊墊上塗佈晶片黏著劑之後， 搭載矽晶片30，以晶片黏著劑内不會殘留氣泡之 分地擠壓之後，以1 5 0 °C加熱加壓1小時。其次， 徑25#m的金屬線來接合矽晶片30的電極30a與 墊20的土堤部21之間及矽基片30的電極30a與 籲1 〇之間。 針對上述1單位（4個χ4個）的10單位，亦 個鋁蒸著晶片進行打線接合。打線接合的成功率爲 。接著，藉由傳送成形來模製密封樹脂40 (日東 「HC-100」）。樹脂模製後，在室溫下剝離接合 且’以1 75°C ’ 5小時，在乾燥機中進行後硬化。 使用切割機來切斷成1區塊單位，取得半導體裝置 以軟X線裝置（微聚焦X線電視透視裝置：島 所製「SMX-10O」）來對此半導體裝置p進行内部 設置由 工來加 ，在接 70以圖 固著於 fflitti Τ77Γ -=· 體而g 在其上 方式充 使用直 晶片焊 導電部 即1 60 1 00% 電工製 薄板。 然後， P。 津製作 觀察時 -22- (19) 1354354 ’確認出無金屬線變形或晶片偏移等，且導電部]〇的突 出部份2會形成埋入密封樹脂中的狀態，可取得導電部 10與密封樹脂的接合強度非常高的半導體裝置^ 另外’有關打線接合條件’傳送模製條件，彈性率測 定方法’接合力測定方法，打線接合成功率方面如以下所 述。 φ 〔打線接合條件〕
裝置：SHINKAWA LTD.製「UTC-300BI SUPER」 超音波頻率·· 115KHz 超音波輸出時間：1 5毫秒 超音波輸出：1 20mW 接合負荷：101 8N 搜索負荷：1 03 7N #〔傳送模製條件〕
裝置：TOWA成形機 成形溫度：1 7 5 °C 時間：90秒 箝位壓力：200KN 傳送速度：3mm /秒 傳送壓：5KN 〔彈性率測定方法〕 -23- (20) 1354354 基材層及接著劑層皆是 • 評價機器·· Rheometric公司製的黏彈性光譜器r . ARES j 昇溫速度：5°C /min 頻率：1 Hz 測定模式：拉伸模式 φ 〔接合力測定方法〕 以120°〇0.5 MPax〇.5 m/min的條件來將寬度20 mm’長度50 mm的接合薄板50疊層成35//m銅箔（ JAPAN ENERGY CORPORATION 公司製「C7025」)之後 ’在1 5 0 °C的熱風烤箱放置1小時後，於溫度2 3 °C，溼度 65%RH的環境條件下，以拉伸速度300 mm/min，將35 V m銅箔拉伸於1 80°方向，以其中心値作爲接合強度。 φ 〔打線接合成功率〕 使用rhesca公司製的接合測試器「PTR-30」，且以 測疋模式：牽引測試，測定速度：〇. 5 m m / s e e的條件來 測定打線接合的牽引強度。牽引強度爲0.04N以上時成功 ’小於0.04N時爲失敗。打線接合成功率是由該等的測定 結果來算出成功比例的値。 〔實施例2〕 在實施例1中，除了金屬箔爲使用18/zm的銅-鎳 -24- (21) 1354354 合金箔(JAPAN ENERGY CORPORATION 公司製「C7025 •」）以外，其餘則與實施例1相同製造半導體裝置。打線 . 接合的成功率爲100%。在進行半導體裝置的内部觀察時 ，確認出無金屬線變形或晶片偏移等，可取得導電部與密 封樹脂的接合強度非常高的半導體裝置。 以上，詳細說明有關本發明的實施形態，但本發明的 半導體裝置及其製造方法並非限於上述實施形態，只要不 Φ脫離本發明的主旨範圍’當然亦可實施各種的變更。 【圖式簡單說明】 圖1是以縱剖面來顯示本發明的半導體裝置之一例的 槪略構成圖。 圖2是省略其金屬線以透視狀態來平面顯示圖1的半 導體裝置之說明圖。 圖3(a) —（d)是表示圖1所示之半導體裝置的製 φ造方法的工程圖。 圖4(a) — （c)是表示在晶片焊墊的土堤部設置通 路時之説明圖。 圖5(a) — (e)是表示基板作成的程序之工程圖。 圖6是表示圖5(b)的部份擴大圖。 圖7是以縱剖面來顯示本發明的半導體裝置的其他例 的槪略構成圖。 圖8是表示本發明的半導體裝置的製造方法之基板作 成工程中在接合薄板形成導電部的狀態的上面圖。 -25- (22) (22)1354354 圖9(a) (b)是表示形成無引線構造的以往半導體 裝置的一例的説明圖。 圖10(a) (b)是表示形成無引線構造的以往半導 體裝置的其他例的説明圖。 【主要元件符號說明】 1，1 a :金屬箔 2，2a:導電部電鍍層 2b :晶片焊墊電鍍層 3 :金屬線 4 :金屬線（追加金屬線） 1 〇 :導電部 20 :晶片焊墊 21 : 土堤部 22 :凹部 3 0 :半導體元件 3 0a :電極 40 :密封樹脂 50 :接合薄板 5 1 :基材層 5 2 :接合劑層 60 :金屬范 61 :乾薄膜阻絕層 62 :部份電鍍層 -26 - (23)1354354 63 :擴散阻擋層 64 :貴金屬電鍍層 70 :區塊 1 0 1 :基材 102 :半導體元件 103a ， 103b :金屬箔 1〇4 :接合劑 1 〇 5 :金屬線 106 :密封樹脂 201 :金屬板
2 0 1a:凹溝 202 :半導體元件 2 0 3 :接合劑 2 〇 4 :金屬線 2 0 5 :密封樹脂 P _·半導體裝置 -27

Claims (1)

1354354 年月·曰修正替換頁 Uoo· m— 第094123950號專利申請案中文申請專利範圍修正本 民國100年5月17日修正 十、申請專利範圍 1· 一種半導體裝置，其特徵係具備： 晶片焊墊； 半導體元件，其係具有電極； 複數個導電部，其係配置於晶片焊墊的周圍； 金屬線，其係連接半導體元件的電極與導電部；及 密封樹脂，其係至少密封導體元件，導電部及金屬線 又，導電部係具有金屬箔，及設置於金屬箔的上下兩 側的導電部電鍍層； 晶片焊墊具有設置於與導電部的下側的導電部電鍍層 同一平面的晶片焊墊電鍍層； 半導體元件係搭載於晶片焊墊的晶片焊墊電鍍層上； 導電部的下側的導電部電鍍層與晶片焊墊的晶片焊墊 電鍍層係其背面會往密封樹脂的外方露出。 2.如申請專利範圍第1項之半導體裝置，其中晶片 焊墊具有在内部形成凹部的土堤部，該土堤部具有導電部 的金屬箔及設置於分別與上下兩側的導電部電鍍層同一平 面的金屬箔及上下兩側的電鍍層，且土堤部的下側的電鍍 層係於晶片焊墊電鍍層一體形成，半導體元件係配置於土 堤部的凹部内，半導體元件的電極與土堤部會藉由追加金 屬線來連接。 1354354 ..1' ··—. 3.如申請專利範圍第2項之半導體裝置，其中半導 體元件的電極係藉由金屬線來與導電部的上側的導電部電 鍍層連接，且藉由追加金屬線來與土堤部的上側的電鍍層 連接。 4. 如申請專利範圍第2項之半導體裝置，其中導電 部的上下兩側的導電部電鍍層係分別具有含貴金屬電鏟層 的多層構成。 5. 如申請專利範圍第2項之半導體裝置，其中導電 部及土堤部的中央的金屬箔係對上下兩側的導電部電鍍層 成蜂腰狀。 6. 如申請專利範圍第2項之半導體裝置，其中導電 部的下側的導電部電鍍層，土堤部的下側的電鍍層，及晶 片焊墊電鍍層皆從密封樹脂往外方突出。 7. 如申請專利範圍第2項之半導體裝置，其中在土 堤部設置密封樹脂通過用的通路。 8. —種半導體裝置製造用基板，係用以製造半導體 裝置的半導體裝置製造用基板，其特徵爲具備： 接合薄板，其係具有基材層，及基材層上的接合劑層 晶片焊墊，其係設置於接合薄板的接合劑層上；及 複數個導電部，其係配置於晶片焊墊周圍； 又，導電部係具有金屬箔，及設置於金屬箔的上下兩 側的導電部電鍍層； 晶片焊墊具有設置於與導電部的下側的導電部電鍍層 -2- ^54354 I fnA日器替換頁 I xl/U-* . *1 · ψ-.—— 同一平面的晶片焊墊電鍍層。 9. 如申請專利範圍第8項之半導體裝置製造用基板 ，其中晶片焊墊具有在内部形成凹部的土堤部，該土堤部 具有導電部的金屬箔及設置於分別與上下兩側的導電部電 鍍層同一平面的金屬箔及上下兩側的電鍍層； 土堤部的凹部爲半導體元件用的凹部》 10. 如申請專利範圍第9項之半導體裝置製造用基板 ’其中導電部的上下兩側的導電部電鍍層係分別具有含貴 金屬電鍍層的多層構成。 11.如申請專利範圍第9項之半導體裝置製造用基板 ’其中導電部及土堤部的中央的金屬箔係對上下兩側的導 電部電鍍層成蜂腰狀。 12.如申請專利範圍第9項之半導體裝置製造用基板 ’其中在土堤部設置密封樹脂通過用的通路。
13. 如申請專利範圍第8項之半導體裝置製造用基板 ’其中接合薄板的基材層係成金屬製。 14. —種半導體裝置用基板的製造方法，係半導體裝 置製造用基板的製造方法，其特徵爲具備： 準備金屬箔之工程； 在對應於金屬箔的導電部的部份，及對應於金屬箔的 晶片焊墊的部份，分別設置部份電鍍層之工程； 將設有部份電鍍層的金屬箔的下側貼附於具有基材層 與接合劑層的接合薄板的接合劑層側之工程； 以部份電鍍層作爲阻絕層來蝕刻金屬箔，藉此形成具 -3- 1354354 - (w ·-* - -r» 有金屬箔及設置於金屬箔的上下兩側的導電部電鍍層之導 電部，且形成具有設置於與導電部的下側的導電部電鍍層 同一平面的晶片焊墊電鍍層之晶片焊墊之工程；及 加工接合薄板，而來決定接合薄板的外形之工程。
-4-
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