TWI353054B - Tri-gate and gate around mosfet devices and method - Google Patents
Tri-gate and gate around mosfet devices and method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
1353054 第93101516號專利申請案 (99年2月25日) 玖、發明說明 【發明所屬之技術領域】 本發明係有關於一種半導體製造方法,更詳而言之, 係有關於一種三閘極與閘極環繞之金屬氡化半導體場效應 電晶體裝置及其製造方法。 【先前技術】 裝置尺寸的縮小已成為驅使積體電路性能的改進與積 體電路成本降低之重要因素。由於閘極氧化物(gate_〇xide) 的厚度與源極/汲極(S0UrCe/drain ; S/D)接面深度之限制, 將現有的金屬氧化半導體場效應電晶體裝置塊體(_)縮 小至0.1微米以下之製程,即使可能的話’也是很困難的。 是故,需要新的裝置結構與新的材料來改進場效應電晶體 性能。 e雙閘極(double-gate)金屬氧化半導體場效應電晶體係 選用來取代現有的平面金屬氧化半導體場效應電晶體之新 裝置。於雙閘極金屬氧化半導體場效應電晶體中,詨雔閘 極係用以控制該通道,俾有效的防止短通道(sWt-cilnL) 效應之發生。鰭式場效應電晶體(FinFET)係為—種包括於 :直鰭部(fin)中形成有通道之雙閘極結構。儘管有雙閘極 結構’鰭式場效應電晶體仍於佈局與製程技術方面與現有 的平面金屬氧化半導體場效應電晶體類似。相較於其他摊 = 鰭式場效應電晶體亦提供通道長度的:佈: CMOS相容性、以及較大的填裝密度。 【發明内容】 (修正本)92529 5 1353054 第93101516號專利申請案 《99年2月25曰) 结本發明所揭露之技術内容係提供一種三閘極與閘極環 繞之金屬氧化半導體場效應電晶體裝置及其製造方法。 據本發明之一個態樣,本發明之三閘極金屬氧化半 :a昜效應電BB體包括鰭部結構、形成於鄰接該鰭部結構 之第—側邊的第一閘極 '形成於鄰接該鰭部結構相對於該 第侧邊之第一側邊的第二閘極以及形成於該鰭部結構上 端的上端閘極。 _ 本發明之另—態樣’本發明之問極環繞金厲氧化 ..半V體%效應電晶體係包括複數韓部形成於鄰接該複數鰭 部其中一韓部之第一側壁閘極結構,形成於鄰接該複數趙 ^其中另一個韓部之第二側壁閘極結構,形成於該複數鶴 -P ’、中個或多個鰭部上之上端閘極結構以及形成於該複 .數鰭部其中一者或多個鰭部下之底部閘極結構。 依據本發明之又一態樣,本發明係提供一種於金屬氧 化半導體場效應電晶體中形成閘極之方法。該方法係包括 攀於基板上形成II部結構;於鄰接該韓部結構處形成側壁問 極結構;以及於該鰭部結構上形成上端間極結構。 - 依據本發明之再—態樣,本發明係提供一種於金屬氧 .化半導體場效應電晶體令形成閘極之方法。該方法係包括 於基板上形成鰭部結構;於鄰接該鰭部結構處形成侧壁閘 極結構;移除該鰭部結構的一個或多個部分以形成複數鰭 部’·於該些鐘部之下形成至少一個額外的閘極結構;以及 於该些鰭部之上形成至少一個額外的閘極結構。 併入並構成本說明書之一部份的圖式係連同說明部份 (修正本)92529 6 丄 第93101516號專利f請案 (99年2月25日) 而用來說明顯示本發明之實施例用 【實施方式】 特定的具體實施例說明本發明之實施方 式…。此技蟄之人士可由本說明書所揭示之内容_易地 瞭解本發明之其他優點| + 1 ^ ^ 門谷粒易地 的且辦眘*… 本發明亦可藉由其他不同 的具體貫把例加以施行或鹿 _ 可基於不同觀點盘應用,: :、中的各項細節亦 種修飾與變更。、 ^本發明之精神下進行各 明實施例之詳細說明將伴隨圖式揭露如下,於不 同圖式中的相同元件符號係用以表示相同或相似的元件。 此外’ ^下之詳細說明並非用以限定本發明。相反地,本 發明之範_係由所附之申請專利範圍或其等效者所定義。 本發明所揭露之技術内容係提供—種三閑極與閑極環 繞之金屬减半導體場效應€晶體裝置及其製造方法。 [三閘極金屬氧化半導體場效應電晶體] 第1圖係為例示的流程圖,用以顯示依據本發明所揭 露之方法製造三閘極金屬氧化半導體場效應電晶體的製 程。第2至第6圓係為例示的剖面圖,用以顯示依據第i 圖之製程所製造之三閘極金屬氧化半導體場效應電晶體。 請同時參閲第1與第2圖,製程可由半導體裝置· 開始。半導體裝置20"包括絕緣層上覆邦iiie〇n 〇n
Insuiat〇r; S〇I)結構,該結構包括石夕基板21〇、埋入氧化声 220以及於該埋入氧化層220上W埋入氧化層 220與石夕層230可透過習知的方法形成於石夕基板21〇上。 (修正本)92529 7 丄妁:3〇54 第93101516號專利申請索 (99年2月25日)' 該埋入氧化層220之里庳 义厚度可例如為約500埃(Α)至3000埃 之間。該矽層230之里庠-ρνι, 、 厚度可例如為200埃至1000埃之間。 應了解到該矽磨230 # ^ 一 仏用以形成該鰭部。於可替代的其他 貫施例中,石夕暮你9〗Λ ”矽層230可包括其他半導體材料 鍺)或,、他如錯切等半導體材料的化合物。埋入氧化 層220可包括卜石々—、 夕或其他類型的介電材料。 閑極介電層2 4 0 "st、©11 了選擇性的透過沉積或熱生長於該矽 層230上(步凝| n 0a 1 a 驟)。閘極介電層240可於大約5埃至3〇 Ϊ L度二圍間予以形成。間極介電層2 4 °可包括習知如 卜 —化石夕)之介電材料。於其他的實施方式中,如 鼠化石夕之介電材料可用以作為該閑極介電材料。 、上端閘極電極層250可選擇沉積於該閘極介電層24〇 亡以形成該上端閉極(步驟12〇)。上端閘極電極層㈣可以 大約100埃至1〇〇〇埃 F # 矢之马度靶圍間予以形成。一些導 材料可用為該上端闡搞士托;a a " 電極声… 舉例而言,上端閘極 私 匕括金屬(如.鎢'鈕、鋁、鎳、釕、鍺、鈀、 鉑、鈦、鉬等),包含化合 .^ ^ ^ 金屬(如.虱化鈦、氮化鉅、 氧化舒朴或㈣的半導體材料(如多晶⑦、多晶料等)。 ^層260(或硬遮罩)可選擇形成於該上端閉極電極 曰 之上端以支援圖案最佳化並於後續的製程中保護上 端閘極電極層250(步驟13 ^ /平巧句5,覆盍層260可包 括氦化梦材料或—也並它類划的分把 ^ 一 型的材枓,而能夠於後續的勢 程中保護該閘極電極。覆芸《 7、杀β 、 拉 透過如化學氣相沉積 (CVD)而沉積大約介於!⑼埃至_埃之厚度範圍。 (修正本)92529 8 1353054 第93101516號專利申請案 (99年2月25曰) 矽$ 230、閘極介電層24〇以及上端閘極電極層Μ。 可透過白知的微影技術(如電子光束(EB)微影技術)予以圖 案化。如第3圖所示1層230與層24G/250接著可利用 習知的姓刻技術予以姓刻藉以形成結構 構300包括鰭部31〇、門炻入士思〇) ^ 310閘極介電層240 '上端閘極電極層 250以及覆盖層260。链邱人 % °丨J 1 υ的見度可大约介於50埃至 1 ο ο 〇埃範圍之間。 、 、依據該結構300的形態,埋入氧化層220的部分可透 過如習^之-種或多種㈣技術加以移除(步驟150)。於其 中種只把方式尹,埋入氧化層22〇可被姓刻至大約㈣ 埃至⑽埃間的深度範圍。如第4圖所示,於姓刻期間, 可移除於鰭部310下方之埋入氧化層220的部分。 如第4圖所示,側壁閘極41〇與42〇可接著予以形成 (步驟副)。舉例而言,間極介電層㈣可選㈣的利Μ 知技術以沉積或熱生長於該結構3〇〇的側表面上。閑極介 電層430可於大約5埃至3〇 令 < 与度靶圍間予以形成。閘 極介電層430可包括習知的介雷 屯材料’如氧化物(如二氧化 砂)。於另一實施方式中,氮化 ΒΒ 矽或其他材料可用以形成該 閘極介電層。 如第4圖所不,接菩沉籍pq & 者儿槓閘極電極層440於半導體穿 ^上,以形成側壁閑極電極。閉極電極層44〇可於: 約100埃至1000埃之厚度範圊 番k 又乾圍間予以形成。與該上端閘極 %極層250相同者,一也材粗^^^ Δ 用以形成該閘極電極層 。如第4圖所示,該 e 440可使用例如化學機 (修正本)92529 9 1353054 第93101516號專利中嗜姿 (99 年 2 月 25
械研磨(Chemical-M cwuanicai 备 〇llshing ; CMP)予以平土曰 化’籍以暴露出該覆蓋層26〇之 一 側壁間極410與420。 丨表面並形成二個分離的 /第5圖所示,接著可選擇移除覆蓋層260'上端門 極,極層250以及閘極介電層24〇(步驟勢舉例而+甲, 遮罩或相似的結構可以習知的方法予以利用,以令覆: 勝上端間極電極層請以及閘極介電層 ^ 時=壁閘極一。的影響減至最,卜於二 。方式閘極介電層240可選擇原封不動的留下來如 不與覆盍層260以及上端閘極電 包仪嘈250 一同移除)。 如弟6圖所示,接著可選遲 180)。兴初& ^ 成上端閘極61〇(步驟 j/ 間極介電材料620可選擇性的再次生+ =Γ部310上。於此情況下,間極介電材料^ 介於於間極介電層240相同的材料,且可形成大約 以保/ ^的厚度範圍。此外,閘極介電層24〇可予 介電著可選擇性沉積電極材料㈣於開極 介電材料620上,以形成上端…0。 =:電材料63。可包括與用於上端閘極電極層25。 二材料,且可透過沉積形成大約介於 %的厚度範圍。 峽主1000 如,二::::Γ半導體裝置2〇°可包括三個閘極(例 用的金Γ 、側壁間極420以及上端閉極㈣)。習 魏+導體場效應電晶體製程 ,金屬氧化半導體場效應電晶體之電晶體:: (修正本)92529 10 1353054 第93101516號專利申請案 (99年2月25日) 源極與汲極區域)、接點 '内連結構以及層間(inter_level) 介電層。 [閘極環繞金屬氧化半導體場效應電晶體] 第7圖係為例示的流程圖,用以顯示依據本發明所揭 露之方法製造閘極環繞金屬氧化半導體場效應電晶體的製 程。第8至第i ;z圖係為例示的剖面圖;甩以顯示依據第7 圖之製程所製造之閘極環繞金屬氧化半導體場效應電晶 肢。製程可由半導體裝置8〇〇開始。半導體裝置8〇〇可包 括絕緣層上覆石夕結構,該絕緣層上覆♦結構包括石夕基板 8 1 〇、埋入氧化層820以及矽層83 0 〇該絕緣層上覆矽結構 可類似於第2圖所揭露之結構。可選擇的,閘極介電層84〇 (步驟710)、上端閘極電極層85〇(步驟72〇)以及覆蓋層86〇 (步驟730)可以同於前述第】圓中步驟11〇至13〇所揭露之 方法而形成於該絕緣層上覆矽結構上。 矽層830、閘極介電層84〇以及上端閘極電極層85( 可透過習用的微影技術(如電子光束微影技術等)進行圖案 化。如第9圖所示,石夕層δ3〇以及層84〇/85〇接著可透過 習知的蝕刻技術進行蝕刻,以形成結構9〇〇(步驟74〇)。社 構_包括鶴部91〇、間極介電層84〇、上端閑極電極層 “Ο以及覆蓋層860。依據本發明,鰭部91〇相當寬。舉例 而言,該縫部9Η)之寬度的範圍可大約介於5〇埃至劇 埃間。 、干u iu /日<邵分可 如習知的触刻技術予以移除(步 々夕丨示(少驟750)。於—個實施 π (修正本>92529 丄: 第93101516號專利申請案 (99年2月25曰) Γ可制埋入氧化層82G至約⑽埃至、約500埃之深度 摩•如第Μ圖所示,於_過程中,鰭部则下的埋入 氧化層820之部分可予以移除。 卜圖所示,接著可形成側壁閘極1 0 1 〇與1 020(步 驟760)。舉例而言,閉 v 』蚀;丨電層1 〇3〇可利用習知技術加 、積或,,、' 生長之。閘極介電層i030可包括習用如氧化物 (如二氧切)等之介電材料。於其他實施方式巾,氛化石夕 或/、他的材料均可用作為該閘極介電材料。 側壁問極電極層1040可沉積於該半導體裝置800上。 側:鳩電極層1040可形成在大約100埃至测埃的厚 度乾圍内。盘却μ Λα, «Β » /、上而閘極電極層850相同者,多數的材料 :用為側壁開極電極層1〇4〇。如第1〇圖所示,側壁閘極 B…〇可利用如化學機械研磨予以平坦化,藉以暴露 s 860之上表面並形成二個分離的側壁閘極101 〇 與 1020 。 如弟U圖所示,接著可選擇性移除覆蓋層㈣、上端 閘極电極層850、閘極介電層84〇以及—個或多個鰭部川 枯/刀(步驟770)。舉例而言,習用的圖案化技術與钱刻 術I用以在最不影響側壁閘極1010與1020的情況下移 示覆现層860、上端間極電極層85〇、閑極介電層mo以及
::或多個鰭部910的部分。於另一實施方式巾,閘極介 電層84 0可误渥,)4 K 、擇的原封不動地留存於鰭部9 1 0未移除的 部分上。如第1 ]圖糾_ 弟 圖所不,鰭部910的蝕刻可終止於埋入最 化層820之上’藉以形成二分離的鰭部111 0。每一個鰭部 (修正本)92529 10 第93101516號專利中請幸 (99年2月25日] mo具有大約在50埃至]〇〇〇柃ps
^ _ 峡主1000埃間的寬度範圍。如第U 圖所不,形成有兩個鰭部丨m ^ 、乃一貫施方式中,可形 成超過二個以上的鶴部1 1 1 〇。 如第12圖所示’接著閘極介電材料1210可透過熱生 長於該鰭部11_1〇暴露的表 ^ ^驟780)。舉例而言,閘 極介電材料1210可生成至女约ς % 成 习D铁芏約30埃間的厚度。 ^介電材料mo可包括與用為閘極介電層84〇相同的材 '。可選擇的’閘極介電層840可保留於鰭部⑴0的上表 面上’而該閘極介電材料 的側表面上。 了生長於該鰭部⑴。暴露 如第圖所示,接著可形成額外的閘極(步驟州。 2而言,間極電極材料1220可選擇性的沉積於該閑極介 電層840/閘極介電材料121〇 ^ M I成額外的閘極。閘 極電極材料1220可包括與用 丄碲閘極電極層850及/或 側壁閘極電極層i 〇4〇相同的 ..= 仞7叶且j,儿積至大約介於1 00 夭至1000埃範圍内的厚度。 如第12圖所示’半導體裝置刚可包括四 側壁閘極1010 '侧壁閉極10 工挪闸極1230以及底都 閘極1240)。上端間極】23〇可形成於韓部】】】〇之上,-而 底部閘極1240則可形成於鰭部111〇之下。習 化半導體場效應電晶體製程可用以實現柽广 屬氧化半導體場效應電晶體之電晶體(如形 榀F a、 & 成该源極與汲 °°域)、接點、内連結構以及層間介電層。 [本發明之其它實施例] (修正本)92529 13 1353054 第931〇ι516號專利申請案 (99年2月25日) 於現有的技術中所極f要的便是將多晶㈣極中換雜 :擴散與活動所要求的熱預算減至最少。第η至第㈣ „ , 用以顯不將多晶矽閘極中擴散活動摻 雜物所需求的熱預算減至最少,第13圖所示,韓部13〇〇 可形成於如絕緣層上覆石夕基板等之基板上。韓部Η。"使 用例如前述該些實施方式中所揭露的製程而予以形成。 h如第14圖所示’薄形多晶碎材料1彻可沉積於趙部 300之上。可執行離子植入製程藉以推雜換雜物至多晶矽 材料1400中。接著執行習知的退火⑻製程。如第 15圖所示:此些步驟可重複-次或更多次。換言之,鰭部 uoo可接受多次的多晶矽沉積 '植入以及退火製程藉以將 摻雜該多晶矽所要求的熱預算減至最少。 、另-個於現有的技術中所亟需要的則是形成高摻雜的 不連續接面。第1 6至第1 8圖係為例示的流程圖,用以顯 示形成高摻雜不連續接面之製程。第16圖係用以顯示例示' 的韓式場效應電晶冑16G()的上視圖。鋒式場效應電晶體 1600包括鰭部161〇與閘極電極162〇。第17圖係用以顯示 鰭式場效應電晶體1 600的側視圖。鰭式場效應電晶體】6〇〇 包括源極區域1710、汲極區域172〇以及通道173〇。源極 區域1710以及汲極區域172〇可植入摻雜物。 如第18圖所示,於摻雜製程之後,源極區域ΐ7ι〇以 及汲極區域1720可透過沉積金屬於源極/汲極區域而予以 矽化,並隨著退火製程而形成金屬_矽化物材料。摻雜物可 累積於該通道介面藉以形成高濃度的不連續接面。 (修 JL 本)92529 14 1353054 第93101516號專利申請案 (99年2月25日) [結論] 依,¾本發明之原則所福咬夕者# + 2 斤揭路之貝鈿方式係提供一種三閘 極與閘極環繞之金屬氧 匕牛導體%效應電晶體裝置及其製 遺方法。 田本發明之實施例之前述敘述提供了說明與敘述,而非 ^限制本發明1於上述教示進行修飾與變化,或者可 由本發明之實施而取得修飾與變化。 舉例而&,於前述之内空_ φ,担山—. ^ ^ 、心内合中楗出了多數具體的細節, 如特定的材料 '結構、化學物品、製程等等’藉以透徹的 了解依據本發明的各種實施方式。然而,前述的該些實施 方式或其他的實施方式係可在不憑藉於此所述的細節而予 以貫現m f知的製程結構並未詳細揭露於本說 明書中,以避免不必要的模糊了本發明之特徵所在。於實 施本發„,可利用習知的沉積、微影以及飯刻等技術, 而S亥些技術的細節於此將不予贅述。 雖然業已詳細說明關於第i與第7圖之一系列步驟, 但是可依據本發明的其他實施方式來改變該等步驟之順 序。此外,這些步驟可予以同時執行而不互相依持者。 除非於說明書已明有說明,否則沒有任何使用於本案 說明書中之元件' 步驟或指示對本發明而言是關鍵性或不' 可或缺者。此外,本說明書中所使用的「一」係包括「一 個」或「多個」項目。僅於特別強調「—個」時^才7*使i用“〇ne” 或類似之語詞。本發明之範4係由申請專利範圍及其等效 者所定義。 、 (修正本)92529 15 1353054 第93101516號專利申請案 (99年2月25日) 【圖式簡單說明】 第1圖係為例示的流程圖,用以顯示依據本發明之實 %方法製造三閘極金屬氧化半導體場效應電晶體的製程; .. 第2至第6圖係為例示的剖面圖,用以顯示依據第1 圖所述之製程所製造之三閘極金屬氧化半導體場效應電晶 •體; 第7圖係為例示的流程圖,用以顯示依據本發明之實 ®施方法製造閘極環繞金屬氧化半導體場效應電晶體的製 程; 弟8至弟12圖係為例示的剖面圖,用以顯示依據第7 圖之製程所製造之閘極環繞金屬氧化半導體場效應電晶 •體; 〜 • 弟13至弟1 5圖係為以將於多晶石夕閘極中擴散活動摻 雜物所需求的熱預算(budget)減至最少之例示的流程圖; 以及 第16至第18圖係為例不的流程圖,用以顯示形成高 摻雜不連續接面之製程。 - 【主要元件符號說明】 • 、120、130、140、150、160、170、180 ' 71〇、72〇、 730、740 ' 750、760、770、780、790 步驟 200、800半導體裝置 210、810矽基板 220、82 0埋入氧化層 230、830矽層 240、43 0、840、1〇3〇 閘極介電層 250 上端閘極電極層 260、S60覆蓋層 (修正本)92529 16 1353054 · 第93101516號專利申請索
300、900 結構 310、910、1 1 10 ' 1300、1610 鰭部 410、420 側壁閘極 610、1230上端閘極 63 0 上端閘極電極材料 1010、1020侧壁閘極 1220 閘極電極材料 1400多晶矽材料 1620 閘極電極 1720汲極區域 440 閘極電極層 620、 1 2 1 0閘極介電材料 850 上間極電極層 1040 側壁閘極電極層 1240 底部閘極 1600 韓式場效應電晶體 1710 源極區域 1730 通道 (修正本)92529 17
Claims (1)
- U53〇54第93101516號專利申請索 (99年9月 16日) -拾、申請專利範圍: ..種於金屬氧化物半導體場效應電晶體(MOSFET) (200)中形成閘極的方法,包括下列步驟: 形成鰭部結構(31〇)於基板上(2 1〇); * 形成閘極介電層(240)於該鰭部結構(wo)之上; 开’成上端閘極電極層(25〇)於該閘極介電層(240) 形成複數個鄰接該鰭部結構(3 1 〇)之側壁閘極結構 (410、420);以及 形成上端閘極結構(6 1 〇)於該鰭部結構(3丨〇)之上端 上; 其中’該形成上端閘極結構(6 1 0)之步驟包括: 移除該上端閘極電極層(250)。 2.如申請專利範圍第丨項之方法,其中,該形成上端閘極 % 結構(61〇)之步驟復包括: 移除該閘極介電層(240)以暴露該鰭部結構(3 1〇); 形成閘極介電層(620)於該鰭部結構(31〇)之上;以 及 沉積閘極材料(630)於該鰭部結構(3 10)之上。 3 •—種於金屬氧化物半導體場效應電晶體(M0SFET) (8 0 〇)中形成閘極的方法,包括: 形成鰭部結構(9 10)於基板(8 10)上; 形成複數個鄰接該鰭部結構(9 1 0)之側壁閘極結構 (1010 ' 1020); 18 (修正本)92529 1353054 93101516號專利申請案 99_年9月 16日) 移除該鰭部結構(9 10)之一個或多個部分,以形成 複數個鰭部(1110); 形成一個額外的閘極結構(1 240)於該等韓部(丨丨丨〇) 之下;以及 形成一個額外的閘極結構(1230)於該等鰭部(丨〗丨〇) 之上。 4. 如申請專利範圍第3項之方法,其中,該形成一個額外 的閘極結構(1230)之步驟包括: 形成閘極介電材料(1210)於該等鰭部(111〇)上;以 及 沉積閘極電極材料(1220)於該閘極介電材料(12〗〇) 上。 5. —種閘極環繞金屬氧化物半導體場效應電晶體 (MOSFET)(800),包括: 複數個鰭部(1 1 10); 第一侧壁閘極結構(10 10),係鄰接於該等鳍部(111〇) 之其中一者而形成; 第二側壁閘極結構(1020),係鄰接於該等鰭部(1 i 1〇) 之其中另一個而形成; 上端閘極結構(1230),係形成於該等複數個雜部 (1110)上,•以及 … 底部閘極結構(1240),係形成於該等複數個鰭部 (11 1 0)之下。 (修正本)92529 19
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- 2003-01-23 US US10/348,911 patent/US7259425B2/en not_active Expired - Lifetime
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TW200417013A (en) | 2004-09-01 |
DE602004008034D1 (de) | 2007-09-20 |
EP1593150B1 (en) | 2007-08-08 |
US20040145000A1 (en) | 2004-07-29 |
JP2006517060A (ja) | 2006-07-13 |
EP1593150A1 (en) | 2005-11-09 |
CN102214585B (zh) | 2014-02-26 |
CN102214585A (zh) | 2011-10-12 |
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