TWI347443B - Delay circuit and testing device - Google Patents
Delay circuit and testing deviceInfo
- Publication number
- TWI347443B TWI347443B TW093139598A TW93139598A TWI347443B TW I347443 B TWI347443 B TW I347443B TW 093139598 A TW093139598 A TW 093139598A TW 93139598 A TW93139598 A TW 93139598A TW I347443 B TWI347443 B TW I347443B
- Authority
- TW
- Taiwan
- Prior art keywords
- delay circuit
- testing device
- testing
- delay
- circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
- G01R31/3191—Calibration
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31922—Timing generation or clock distribution
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
- H03K2005/00032—Dc control of switching transistors
- H03K2005/00039—Dc control of switching transistors having four transistors serially
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
- H03K2005/0013—Avoiding variations of delay due to power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
- H03K2005/00202—Layout of the delay element using FET's using current mirrors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00267—Layout of the delay element using circuits having two logic levels using D/A or A/D converters
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003421617 | 2003-12-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200521459A TW200521459A (en) | 2005-07-01 |
TWI347443B true TWI347443B (en) | 2011-08-21 |
Family
ID=34697311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093139598A TWI347443B (en) | 2003-12-18 | 2004-12-20 | Delay circuit and testing device |
Country Status (7)
Country | Link |
---|---|
US (1) | US7511547B2 (zh) |
EP (1) | EP1699134A4 (zh) |
JP (1) | JP4558649B2 (zh) |
KR (1) | KR101177150B1 (zh) |
CN (1) | CN100563103C (zh) |
TW (1) | TWI347443B (zh) |
WO (1) | WO2005060098A1 (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4825131B2 (ja) * | 2004-09-27 | 2011-11-30 | 株式会社アドバンテスト | 消費電流バランス回路、補償電流量調整方法、タイミング発生器及び半導体試験装置 |
JP4925630B2 (ja) * | 2005-09-06 | 2012-05-09 | 株式会社アドバンテスト | 試験装置および試験方法 |
JPWO2007114379A1 (ja) | 2006-03-31 | 2009-08-20 | 株式会社アドバンテスト | 可変遅延回路、試験装置および電子デバイス |
KR101324341B1 (ko) | 2006-08-24 | 2013-10-31 | 가부시키가이샤 어드밴티스트 | 가변 지연 회로, 타이밍 발생기 및 반도체 시험 장치 |
US7456672B1 (en) * | 2006-09-11 | 2008-11-25 | Lattice Semiconductor Corporation | Clock systems and methods |
US8729944B2 (en) * | 2011-12-21 | 2014-05-20 | Advanced Micro Devices, Inc. | Clock generator with integrated phase offset programmability |
CN103226180A (zh) * | 2012-01-31 | 2013-07-31 | 哈尔滨建成集团有限公司 | 一种电子延时器测试系统 |
DE102012107024B3 (de) | 2012-08-01 | 2013-08-29 | Infineon Technologies Ag | Schaltung zum strombegrenzten Umladen eines Knotens |
US9000822B2 (en) | 2013-04-09 | 2015-04-07 | International Business Machines Corporation | Programmable delay circuit |
US9628059B2 (en) | 2015-06-18 | 2017-04-18 | International Business Machines Corporation | Fine delay structure with programmable delay ranges |
US9715941B2 (en) * | 2015-10-30 | 2017-07-25 | Sony Semiconductor Solutions Corporation | State machine controlled MOS linear resistor |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05145382A (ja) * | 1991-11-25 | 1993-06-11 | Nec Eng Ltd | パルス遅延回路 |
JPH05327425A (ja) * | 1992-05-15 | 1993-12-10 | Nec Corp | 発振回路 |
JP3399616B2 (ja) * | 1994-01-31 | 2003-04-21 | 富士通株式会社 | オシレータ回路、そのオシレータ回路を用いたセルフリフレッシュ用オシレータ及び基板バイアス回路 |
JPH08139573A (ja) * | 1994-11-08 | 1996-05-31 | Hitachi Ltd | ワンショットパルス発生回路 |
JP3688392B2 (ja) * | 1996-05-31 | 2005-08-24 | 三菱電機株式会社 | 波形整形装置およびクロック供給装置 |
JPH11306757A (ja) * | 1998-04-27 | 1999-11-05 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP4394788B2 (ja) * | 1999-05-10 | 2010-01-06 | 株式会社アドバンテスト | 遅延時間判定装置 |
JP2001028195A (ja) * | 1999-07-14 | 2001-01-30 | Matsushita Electric Ind Co Ltd | 遅延回路および半導体メモリ |
JP2001185993A (ja) * | 1999-12-24 | 2001-07-06 | Oki Electric Ind Co Ltd | 電圧制御発振回路 |
JP2002176340A (ja) * | 2000-12-06 | 2002-06-21 | Toshiba Corp | 遅延回路及び電圧制御発振回路 |
JP2002223149A (ja) * | 2001-01-29 | 2002-08-09 | Hitachi Ltd | 半導体集積回路 |
JP4866514B2 (ja) * | 2001-06-29 | 2012-02-01 | 株式会社アドバンテスト | 遅延回路、及び試験装置 |
JP4133814B2 (ja) * | 2001-07-27 | 2008-08-13 | 株式会社アドバンテスト | タイミング発生器及び半導体試験装置 |
JP4093961B2 (ja) * | 2001-10-19 | 2008-06-04 | 株式会社アドバンテスト | 位相ロックループ回路、遅延ロックループ回路、タイミング発生器、半導体試験装置及び半導体集積回路 |
US7089135B2 (en) | 2002-05-20 | 2006-08-08 | Advantest Corp. | Event based IC test system |
US6909316B2 (en) | 2003-02-21 | 2005-06-21 | Agilent Technologies, Inc. | Variable delay circuit with high resolution |
-
2004
- 2004-12-17 KR KR1020067014436A patent/KR101177150B1/ko not_active IP Right Cessation
- 2004-12-17 CN CNB2004800376777A patent/CN100563103C/zh not_active Expired - Fee Related
- 2004-12-17 JP JP2005516373A patent/JP4558649B2/ja not_active Expired - Fee Related
- 2004-12-17 WO PCT/JP2004/018943 patent/WO2005060098A1/ja active Application Filing
- 2004-12-17 EP EP04807300A patent/EP1699134A4/en not_active Withdrawn
- 2004-12-20 TW TW093139598A patent/TWI347443B/zh not_active IP Right Cessation
-
2006
- 2006-06-05 US US11/446,855 patent/US7511547B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060267656A1 (en) | 2006-11-30 |
CN1894852A (zh) | 2007-01-10 |
US7511547B2 (en) | 2009-03-31 |
EP1699134A4 (en) | 2010-12-08 |
TW200521459A (en) | 2005-07-01 |
JPWO2005060098A1 (ja) | 2007-07-12 |
KR20070031857A (ko) | 2007-03-20 |
CN100563103C (zh) | 2009-11-25 |
JP4558649B2 (ja) | 2010-10-06 |
EP1699134A1 (en) | 2006-09-06 |
KR101177150B1 (ko) | 2012-08-24 |
WO2005060098A1 (ja) | 2005-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1610135A4 (en) | TESTING DEVICE AND TEST PROCEDURE | |
TWI349367B (en) | Semiconductor device and making thereof | |
GB2418258B (en) | Analyte testing device | |
GB0508689D0 (en) | Electrical circuit testing device | |
GB0320642D0 (en) | Sensing devices and sensing circuits | |
EP1632999A4 (en) | BATTERY-ASSISTED INTEGRATED CIRCUIT EQUIPMENT | |
HK1072678A1 (en) | Electronic device | |
HK1130142A1 (en) | Integrated circuit device and system thereof | |
GB2396055B (en) | Circuit device construction | |
EP1658809A4 (en) | MEASURING DEVICE AND MEASURING PROCEDURE | |
AU2003245446A8 (en) | Methods and apparatus for delay circuit | |
TWI347443B (en) | Delay circuit and testing device | |
GB2406728B (en) | An integrated circuit device | |
GB0422306D0 (en) | Tester device | |
EP1646034A4 (en) | FLAT DISPLAY SETUP AND INTEGRATED CIRCUIT | |
GB0308070D0 (en) | Integrated circuit design and testing | |
EP1640736A4 (en) | TEST FACILITY | |
GB0310718D0 (en) | Pressing device for thin-film circuit and terminal | |
GB2401438B (en) | Isolator test device | |
EP1612572A4 (en) | TEST DEVICE AND SETTING METHOD | |
EP1653239A4 (en) | TEST EQUIPMENT | |
EP1686384A4 (en) | DEVICE AND METHOD FOR MEASURING INSTABILITY | |
TW572564U (en) | Clammer-typed electronic device | |
EP1666993A4 (en) | ELECTRONIC EQUIPMENT | |
EP1666899A4 (en) | SEMICONDUCTOR TEST EQUIPMENT |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |