TWI332693B - Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion - Google Patents

Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion Download PDF

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Publication number
TWI332693B
TWI332693B TW095123654A TW95123654A TWI332693B TW I332693 B TWI332693 B TW I332693B TW 095123654 A TW095123654 A TW 095123654A TW 95123654 A TW95123654 A TW 95123654A TW I332693 B TWI332693 B TW I332693B
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Taiwan
Prior art keywords
conductive
matrix
particles
die
embedded
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TW095123654A
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English (en)
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TW200715495A (en
Inventor
Leonel Arana
Michael Newman
Devendra Natekar
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Intel Corp
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Publication of TW200715495A publication Critical patent/TW200715495A/zh
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Publication of TWI332693B publication Critical patent/TWI332693B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

1332693 (1) 九、發明說明 【發明所屬之技術領域】 本發明有關於微電子領域，更詳而言之，但非排他， 關於堆疊封裝件以及導電穿透矽通孔。 【先前技術】 積體電路設計的演化已造成較高操作頻率、增加的電 Φ 晶體數量以及實體上更小的裝置。此持續的趨勢產生積體 電路之持續增加的面積密度。欲進一步增加積體電路可能 的密度，於一些實例中可能希望透過導電穿透矽通孔電性 - 耦合晶粒上之主動電路層至在相同或不同晶粒上之另一主 - 動電路層。一典型的穿透矽通孔可簡單地爲晶粒之塊矽部 分內的孔，其塡充有大致上均勻成分之塊材，如銅合金◊ 由於溫度改變’許多材料會經歷物理膨脹或收縮。熱 膨脹係數（CTE )代表針對一單位之溫度改變，塊材中一 ® 單位體積之的改變。若第一塊材之體積在給定溫度以零應 力圍住具有與第一塊材不同熱膨脹係數之第二塊材，溫度 之改變可能導致非零的應力在不同塊材的介面產生。於一 些情況中，在足夠的溫度改變下或足夠次數的溫度脫羈週 期，在不同塊材之介面處的應力可能超過特定臨界應力並 且於塊材之一或另一或兩者中導致永久性的變形或斷層。 或者’積體電路置之44能會由於在不同塊材的介面處之 增加的應力而變差，而非|料經歷永久性變形或斷層。 在正常的製造週期期間，包含積體電路之封裝件會經 -5- (2) 1332693 過各種程序，其中一些會在升高的溫度時發生。例如，包 含積體電路之封裝件會在也許處於室溫之後經歷回焊程 序。於焊料回塡程序中，封裝件中的各種組件，包含積體 電路以及積體電路所耦合之連同的塊矽會接近或甚至超過 焊料回塡之溫度，如針對代表性的無鉛焊料爲大槪爲 23 0°C，與例如大槪爲25t之正常儲存溫度間的差距懸 殊。於目前的範例中，封裝件與其之組件會經歷明顯的溫 # 度改變，例如根據目前的範例，高達或超過205t。 此外，在正常操作下，如處理器之積體電路會產生熱 量，其導致封裝件中的各種組件，包含積體電路以及積體 電路所耦合之連同的塊矽會經歷溫度變化。雖然在正常操 - 作下溫度脫羈也許不會如在製造程序中受感受到的那般極 端，在產品之設計壽命期間，封裝件中與其之組件，包含 積體電路以及積體電路所耦合之連同的塊矽可能會因正常 操作而經歷到多次溫度脫羈。 • 與具有約爲2.6 ppm/1之容積線性CTE的矽相比，銅 具有約爲16.5 ppm/°C之容積線性CTE。因此，一單位體 積之銅比一單位體積的矽膨脹許多。由於典型穿透矽通孔 可簡單地爲塡充有銅合金之積體電路晶粒之塊矽部分內的 孔，而各材料之CTE幾乎有十倍之差，當封裝件經歷溫度 脫羈時，機械應力會在銅-矽介面處產生。 例如，第1 (a)圖代表一群傳統的穿透矽通孔，其顯 示具有積體電路1〇〇之塊矽晶粒的一部分。傳統的穿透矽 通孔112可經由導電種子層114電性耦合至金屬墊108。 -6- (3) 1332693 在導電種子層I 1 4以及塊矽晶粒1 02的一部分之間可爲鈍 化或電性絕緣層1 16。可由層間介電質（1LD )材料】04 隔開金屬墊1〇8以及塊矽晶粒102的一部分。耦合至金屬 墊108間之塊矽晶粒102的部分的一層ILD 104係位在— 層鈍化材料Π〇或保護層106之下。第1(b)圖與第】 (c)圖分別代表受到應力產生之脫層120與晶粒破裂1 I 8 之機械性破壞。傳統的穿透矽通孔可具有大小實質上與連 # 續金屬相的容積（bulk) CTE類似並且實質上與矽之容 積CTE不同的容積CTE，導致在溫度脫羈時會有明顯的主 應力。而明顯的主應力會導致積體電路之機械性的破壞， *- 如脫層120或晶粒破裂118。此外，明顯的主應力，雖不 - 致於導致脫層120或晶粒破裂118仍會造成積體電路內性 能的下降。 欲在給定的溫度脫羈維持因CTE的不匹配而導致之機 械性應力在任一塊材的臨界應力以下，可減少通孔尺寸、 ® 增加相鄰通孔之間的間隔或可遠離主動電路地設置通孔。 這些解決方法的每一個會導致晶粒尺寸的增加、電路之密 度比否則可實現者較低或每晶粒的成本增加。 【發明內容及實施方式】 在此揭露提供具有希望之熱膨脹容積係數之穿透矽通 孔的方法、裝置與系統。於下列實施方式中，參照形成在 此之一部分的附圖，其中類似的符號代表全文中類似的部 分，以及其中例示性顯示可實施之特定實施例。應了解到 (4) 1332693 可利用其他的實施例並可做出結構或邏輯上的改變而不背 離所提之申請專利範圍的範疇。並且，應了解到可使用方 向與參考（如上、下、頂部、底部、主要側、後側等等） 來輔助圖之討論且非意圖限制所提之申請專利範圍之應用 寬度。因此，下列實施方式不應視爲限制性且可能的實施 例之範圍僅由所附之申請專利範圍以及其等效者界定》 參照第2圖，描述所呈現之實施例可用於其中之許多 # 可能的系統之一。積體電路封裝件200可包含分別與第6 圖到第 18圖中所示之矽晶粒 600、700、800、900、 1000、 1100、 1200' 1300、 1400、 1500、 1600、 1700 以及 - 1 800部分類似之矽晶粒部份。於一實施例中，積體電路封 - 裝件200可包含微處理器。於一替代實施例中，積體電路 封裝件200可包含應用專門IC ( ASIC )。亦可封裝在晶 片組（如圖形、聲音與控制晶片組）或記憶體中之積體電 路。 ® 針對第2圖所示之實施例，系統90可包含主記憶體 202、圖形處理器204、大量儲存裝置206以及輸入/輸出 模組208，其透過匯流排21 0互相耦合，如所示。記憶體 202之範例包含但不限於靜態隨機存取記億體（SRAM ) 與動態隨機存取記憶體（DRAM)。大量儲存裝置206之 範例包含但不限於硬碟機、快閃機、光碟機（CD )以及多 功能數位碟片機（DVD )等等。輸入/輸出模組208之範 例包含但不限於鍵盤、游標控制裝置、顯示器、網路介面 等等。匯流排210之範例包含但不限於週邊控制介面 -8 - (5) 1332693 (PCI )匯流排以及工業標準構造（ISA )匯流排等等。於 各種實施例中，系統90可包含無線行動電話、個人數位 助理、口袋PC、平板PC、桌上型電腦、機上盒、音頻/視 頻控制器、DVD控制器、網路路由器、網路交換裝置或伺 服器。 第3圖描述用來塡充有5 00微米間距之通孔陣列中一 20微米的通孔之材料的歸一化（參考CTE爲銅之CTE) 9 的容積CTE與第一主應力之有限元素模擬結果的圖。0.16 之歸一化的CTE代表矽。第3圖之資料顯示隨著通孔材料 的容積CTE越來越接近矽的CTE，第一主應力會降低。 ' 第4圖描繪進一步的有限元素模擬之圖，其顯示20 微米純銅通孔以及由具有銅25%之CTE的材料製成的20 微米通孔之通孔間距與第一主應例的變化。第4圖之資料 顯示若具有降低之CTE的塊材形成通孔則在小間距時第一 應力明顯的減少。此外，在較大之間距，降低的CTE通孔 ^ 會比傳統CTE通孔產生更低的第一主應力。 塡充粒子之散佈相可改變一或更多穿透矽通孔之塊材 料特性。例如，形成連續相之金屬矩陣以及形成散佈相之 嵌入球形塡充物之合成的所得之電阻率可由下列式子來估 算：（註：請插入第8頁第5行之式子），其中 代表所得之容積電阻率、仏代表球形塡充物之容積電阻率 以及尤·?代表矩陣金屬之容積電阻率以及；？代表球形塡充 物與容積合成體積之體積分數。 此外’形成連續相之金屬矩陣以及形成散佈相之嵌入 • 9 - (6) 1332693 球形塡充物之合成的所得的CTE可由下列式子估算： (註：請插入第8頁第11行之式子），其中 代表所得之容積 CTE、代表球形塡充物之容積 CTE、CrS?代表矩陣金屬之容積CTE而p代表球形塡充 物與容積合成體積之體積分數。 第5圖描繪顯示具有CTE小於矩陣金屬之球形塡充物 的增加的體積分數可單調地降低矩陣金屬與嵌入球形塡充 Φ 物所產生的合成的容積CTE。此外，第5圖描繪具有電阻 率大於矩陣金屬之球形塡充物的增加的體積分數可單調地 增加矩陣金屬與嵌入球形塡充物所產生的合成的電阻率。
• 再者’第5圖之資料暗示塡充材料之選擇包括降低的CTE - 與增加的電阻率之折衷。惟，塡充粒子體積分數可高達 8 0 %以上。 雖然爲了計算之簡單性而模型化球形粒子，球形粒子 在實際上可爲任意的形狀。此外，包含散佈相之塡充粒子 ® 可爲矽土、礬土、氮化硼、鎢、因鋼（lnvar)、超因鋼 (Super Invar)、科華合金（Kovar)或其他具有CTE小 於諸如矽之通孔會通過之周圍的塊晶粒材料的其他材料之 任一者或其結合。再者，可於磁場輔助的電鍍程序中使用 鐵磁材料，如 Invar、Super Invar 或 Kovar。 一實施例使用許多金屬之一作爲矩陣。範例矩陣材料 包含銅（Cu)、金（Au)、錦（A1)、鎢（W)、銀 (Ag )以及共熔焊料與非共熔焊料兩者。範例的共熔焊料 包含錫-鉛（Pb/Sn)焊料以及金-錫（Au/Sn)焊料。 -10- (7) 1332693 第6圖描繪具有積體電路600之晶粒的一部分之—實 施例。於一實施例中，穿透矽通孔612可經由導電種子層 614電性耦合至金屬墊608。於又一實施例中，穿透矽通 孔612可爲合成’其中通孔612之容積CTE小於矩陣金屬 之容積CTE。於再一實施例中，降低的CTE穿透矽通孔 612可包含形成連續相之矩陣金屬以及具有CTE小於矩陣 金屬之嵌入粒子’嵌入粒子形成散佈相並且降低的CTE穿 φ 透矽通孔6丨2具有小於矩陣金屬之容積CTE的容積CTE。 在導電種子層614以及塊矽晶粒602的一部分之間可爲鈍 化或電性絕緣層6 1 6。可由層間介電質（ILD )材料604 ·. 隔開金屬墊608以及塊矽晶粒602的一部分。耦合至金屬 墊608間之塊矽晶粒602的部分之一層ILD 604係位在一 層鈍化材料610或保護層606之下。 第7圖至第18圖描繪經歷用以製造穿透包含積體電 路之晶粒之通孔的方法之物件。 ® 第7圖描繪可施加製造方法之基底700。可由層間介 電質（ILD )材料604隔開金屬墊608以及晶粒602的一 部分。於一實施例中，晶粒602爲矽。於又一實施例中， 耦合至金屬墊608間之塊矽晶粒602的部分之一層ILD 6〇4係位在一層鈍化材料610或保護層606之下。 第8圖描繪第7圖之基底，其中具有積體電路8〇〇之 晶粒的部分中’在接近金屬墊608附近的材料被移除掉。 於一實施例中，晶粒602爲矽。可藉由光微影技術跟隨著 乾或濕蝕刻來達成晶粒材料的移除。替代地，移除可爲微 -11 - (8) 1332693 機械技術。於一實施例中，微機械技術可爲爆炸' 鑽孔或 其他微機械技術或其結合。另外，可類似地移除在接近金 屬墊附近之ILD 504的部分。如同第7圖中，可由層間介 電質（ILD )材料6〇4隔開金屬墊60 8以及晶粒602的一 部分。耦合至金屬墊608間之塊矽晶粒602的部分之一層 ILD 604係位在一層鈍化材料610或保護層606之下。 第9圖描繪在製造期間之第8圖之基底，其顯示具有 # 積體電路900之晶粒的部分。於第9圖中，可沉積一層材 料616於晶粒602的表面上。於一實施例中，晶粒602爲 矽。材料層616可爲鈍化層。替代地，材料層616可爲電 ·· 性絕緣材料。如於前圖中，可由層間介電質（ILD)材料 604隔開金屬墊608以及晶粒602的一部分。耦合至金屬 墊608間之塊矽晶粒602的部分之一層ILD 604係位在一 層鈍化材料610或保護層606之下。 第1〇圖描繪在製造期間之第9圖之基底，其顯示具 • 有積體電路1 000之晶粒的部分。於第10圖中，移除接近 金屬墊608之材料層616，以重新暴露出先前露出的金屬 墊608。如於前圖中，晶粒602可爲矽並且可由層間介電 質（ILD )材料604隔開金屬墊608以及晶粒602的一部 分。耦合至金屬墊608間之塊矽晶粒602的部分之一層 ILD 604係位在一層鈍化材料610或保護層606之下。 第11圖描繪具有積體電路1100以及沉積於先前沉積 之材料層616的表面上之第二材料層614之第10圖之基 底的部分。第二材料層614可爲阻障層。替代地，材料層 -12- (9) 1332693 614可爲種子層以輔助後續的電鍍程序。如於前圖中，可 由層間介電質（ILD )材料604隔開金屬墊608以及晶粒 6 02的一部分。耦合至金屬墊608間之塊矽晶粒602的部 分之一層ILD 6〇4係位在一層鈍化材料610或保護層606 之下。 第12圖描繪具有積體電路1 200以及沉積於先前沉積 之材料614層的表面上之光阻圖案1202之第II圖的基 φ 底。如於前圖中，材料層616可位在塊矽晶粒502之上與 第二材料層614之下。可由層間介電質（ild)材料6 04 隔開金屬墊608以及晶粒6〇2的一部分。耦合至金屬墊 - 608間之塊矽晶粒602的部分之一層ILD 6〇4係位在一層 . 鈍化材料610或保護層606之下。 第13圖描繪第12圖之基底，其顯示浸泡於電鍍池 13〇0中之具有積體電路之晶粒的部分。於第13圖中，電 鍍池13 02可包含於溶液或懸浮中之具有相對·於沉積之矩 ® 陣金屬降低之CTE的粒子13〇4。如於前圖中，材料層616 可位在塊矽晶粒502之上與第二材料層614之下。可由層 間介電質（ILD )材料6〇4隔開金屬墊608以及晶粒602 的一部分。耦合至金屬墊608間之塊矽晶粒602的部分之 —層ILD 6〇4係位在一層鈍化材料61〇或保護層6〇6之 下。 第I4圖描繪第13圖之基底，其具有浸泡在電鍍池 】4〇0中之積體電路。於第14圖中，通孔14〇2的—部分可 沉積在先前於晶粒602中產生的孔內。於一實施例中，通 -13- (10) 1332693 孔1402可爲穿透矽。於一實施例中，晶粒602可爲矽》 電鍍池1302可包含於溶液或懸浮中之具有相對於沉積之 矩陣金屬降低之CTE的粒子1304。在電鍍程序期間，塡 充粒子1304可共同沉積於降低的CTE穿透矽通孔1402的 一部分中。此外，爲了幫助共同沉積塡充粒子〗3〇4，施加 驅動勢ό驅動勢可爲引力或可作用於電鍍池13〇2或塡充 粒子13 04上之其他的驅動勢。如於前圖中，材料層616 Φ 可位在塊矽晶粒502之上與第二材料層614之下。可由層 間介電質（ILD)材料6〇4隔開金屬墊608以及晶粒602 的一部分。耦合至金屬墊608間之塊矽晶粒602的部分之 • —層1LD 604係位在一層鈍化材料61〇或保護層606之下 - 並可進一步有光阻圖案1 202。 第15圖描繪第16圖之基底，其具有浸泡在電鍍池 15 00中之積體電路。於第14圖中，可完全沉積降低的通 孔612 ’該通孔爲合成，其包含具有比晶粒602較大之 ® CTE的形成連續相之金屬矩陣以及具有比金屬矩陣較小之 CTE的形成散佈相之塡充粒子，該合成呈現出小於矩陣金 屬之容積CTE的容積CTE。於一實施例中，晶粒602實質 上爲矽。如於前圖中，電鍍池1302可包含於溶液或懸浮 中之具有相對於沉積之矩陣金屬降低之CTE的粒子 13〇4。在電鍍程序期間’塡充粒子13〇4可共同沉積於降 低的CTE穿透矽通孔1402的一部分中。此外，爲了幫助· 共同沉積塡充粒子13 〇4’施加驅動勢。驅動勢可爲引力或 可作用於電鍍池1 302或塡充粒子13〇4上之其他的驅動 *14- 1332693 ' (11) 勢。如於前圖中，材料層616可位在塊矽晶粒502之上與 第二材料層614之下。可由層間介電質（ILD)材料604 隔開金屬墊608以及晶粒602的一部分。耦合至金屬墊 608間之塊矽晶粒602的部分之一層ILD 604係位在一層 鈍化材料610或保護層606之下並可進一步有光阻圖案 1 202 ° 第16圖描繪第15圖之基底，其顯示移除掉電鑛池之 # 具有積體電路1 600之晶粒的部分。如於前圖中，晶粒602 可爲矽，材料層616可位在塊矽晶粒502之上與第二材料 層614之下。可由層間介電質（ILD )材料604隔開金屬 墊608以及晶粒602的一部分。耦合至金屬墊608間之塊 . 矽晶粒602的部分之一層ILD 604係位在一層鈍化材料 61〇或保護層606之下並可進一步有光阻圖案12 02。 第17圖描繪第16圖之基底，其顯示移除掉光阻之具 有積體電路1 700之晶粒的部分。如於前圖中，材料層616 ® 可位在塊矽晶粒502之上與第二材料層614之下。可由層 間介電質（ILD )材料604隔開金屬墊608以及晶粒602 的一部分。耦合至金屬墊608間之塊矽晶粒602的部分之 一層ILD 604係位在一層鈍化材料610或保護層606之 下。 第18圖描繪第17圖之基底，其顯示具有積體電路 1800以及蝕刻於新沉積的通孔612之間的第一層614與第 二層616而暴露出晶粒602的一部分之塊矽晶粒的部分。 晶粒602可爲矽。如於前圖中，材料層6 1 6可位在塊矽晶 -15- (12) 1332693 粒502之上與第二材料層614之下。可由層間介電質 (ILD )材料6〇4隔開金屬墊608以及晶粒602的一部 分。耦合至金屬墊608間之塊矽晶粒602的部分之一層 ILD 604係位在一層鈍化材料610或保護層606之下。 第19圖描述形成包含矩陣與散佈的塡充粒子之穿洞 通孔之方法。於第19圖所示之方法中，可自具有主要側 與背側之塊矽晶圓的背側移除1 902材料。暴露出1 904整 φ 合於塊矽晶圓之主要側上的金屬墊。沉積第一層材料於暴 露的金屬墊上並藉由材料移除1906在塊矽晶圓內的孔中 產生內部表面。可蝕刻該層材料以暴露出金屬墊1 90 8之 區域。可沉積一層導電材料在暴露的金屬墊區域以及先前 . 沉積的材料上1910。可沉積光阻圖案於導電材料層上 19]2。可施加電鍍技術以沉積導電穿透矽通孔1914，其由 兩相塊材所製成：連續相爲矩陣金屬而散佈相爲嵌入之塡 充粒子。移除1916光阻圖案並蝕刻1918沉積在塊矽晶圓 • 之背側上的兩材料層。 第20圖描述可用於合成通孔之一實施例中的材料之 不完全的表單，以及數個關聯之材料特性。 雖爲了說明較佳實施例已圖解並描述了特定實施例， 熟悉該項技藝者應可理解到各種計畫達成相同目的之替代 以及/或等效實施可取代所圖示與描述之特定實施例而不 背離意圖之範疇。例如，替代實施例可存在於其中塡充粒 子塡充在晶粒內之開放式通孔洞之中以及可使用化學蒸氣 沉積（CVD )或物理蒸氣沉積（PVD )程序（如噴鍍、蒸 -16- (13) 1332693 發、噴射蒸氣沉積）來塡充沒有塡充粒子的任何體積之穿 洞。另一實施例可存在於其中含有塡充粒子之焊料球可回 焊至晶粒內之開放式通孔洞內。又一實施例可在真空下回 焊含有塡充粒子之焊料球以避免空氣塡入完成的通孔內之 孔洞中。因此，熟悉該項技藝者可迅速理解到可使用非常 廣泛的實施例來達成實施。此說明書意圖涵蓋於此討論之 實施例的任何改變與變化。故，很明顯地應僅申請專利範 φ 圍與其等效者可限制可能實施例之範圍。 【圖式簡單說明】 ·- 第〗圖描繪單相塊材之傳統穿透矽通孔（第1(a) . 圖）代表圖以及導致脫層（第1(b)圖）與晶粒破裂（第 1 ( c )圖）。 第2圖描繪包含包括粒子塡充之具有降低熱膨脹之穿 透矽通孔的電子封裝組件的系統之一實施例。 9 第3圖描繪針對給定穿透矽通孔陣列之歸一化之材料 應力變化與歸一化之熱膨脹係數的曲線圖。 第4圖描繪針對塡充有純銅的通孔以及塡充有25%純 銅之CTE的塊材的通孔之歸一化之材料應力變化與通孔陣 列間隔的曲線圖。 第5圖描繪兩種不同的塡充材料之CTE之變化與電阻 率之變化以及嵌入粒子之體積分數。 第6圖描繪由塊材製成之導電穿透矽通孔之一實施 例，該塊材由形成連續相的矩陣金屬以及形成散佈相之嵌 -17- (14) 1332693 入粒子所組成。 第7圖描繪在處理前矽晶粒的一部分。 第8圖描繪具有多個區域的材料移除掉之第7圖之矽 晶粒的部分。 第9圖描繪具有沉積在塊矽的表面上以及金屬墊的下 側之第一層材料之第8圖之矽晶粒的部分。 第10圖描繪在藉由部分移除沉積之第一層材料而暴 φ 露出金屬墊之後的第9圖之矽晶粒的部分。 第11圖描繪具有沉積於暴露之金屬墊以及第一層材 料上之第二層材料的第10圖之矽晶粒的部分。 ·. 第12圖描繪具有施加的光阻之第11圖之矽晶粒的部 分。 第13圖描繪浸泡在具有散佈之粒子的電解池中之第 1 2圖之矽晶粒的部分。 第14圖描繪具有散佈之粒子的部分沉積的穿透矽通 # 孔之第1 3圖之矽晶粒的部分。 第15圖描繪具有散佈之粒子的完全沉積的穿透矽通 孔之第.14圖之矽晶粒的部分。 第16圖描繪電解移除掉之第15圖之矽晶粒的部分。 第17圖描繪光阻移除掉之第16圖之矽晶粒的部分。 第18圖描繪在穿透矽通孔之間的第一與第二層材料 移除掉之第圖之砂晶粒的部分。 第19圖描述降低的CTE之穿透矽通孔之製造方法。 第20圖描述用於形成合成通孔之可能的材料表。 -18- (15) 1332693 【主要元件符號說明】 90 :系統 100 :積體電路 102、602:塊矽晶粒 104、604:層間介電質（ILD)材料 106、 606:保護層
108 、 607 :金屬墊 1 1 0、6 1 0 :鈍化材料 112、612:穿透矽通孔 114、614:導電種子層 1 1 6、6 1 6 :鈍化或電性絕緣層 1 1 8 :晶粒破裂 1 20 :脫層 200 :積體電路封裝件 202 :主記億體 204 :圖形處理器 206 :大量儲存裝置 208 :輸入/輸出模組 2 1 0 :匯流排 1 3 00、 600、 700、 8 00、 900、 1 000 ' 1100、 1 200 ' 1400、1 500、1 600、1 700、1 800：積體電路 1 2 0 2 :光阻圖案 1300、 1302、 1400 ：電鍍池 -19- 1332693 (16) 1 3 0 4:粒子 1 4 0 2 :通孔

Claims (1)

1332693 U修正 1曰補充 十、申請專利範圍 附件g A : 第95 1 2 3 65 4號專利申請案 中文申請專利範圍替換本 民國99年3月9曰修正 1. 一種半導體封裝件，包含： 積體電路；及 Φ 形成耦合至該積體電路之導電穿洞通孔之材料，其中 該材料包含一導電矩陣，該矩陣具有塡充粒子嵌入於其中 ，其中該塡充粒子包含鐵磁材料。 - 2.如申請專利範圍第1項之半導體封裝件，其中形成 -該通孔之該材料的塊材特性與該導電矩陣的塊材特性不同 3. 如申請專利範圍第2項之半導體封裝件，其中該塊 材特性爲熱膨脹係數。 4. 如申請專利範圍第2項之半導體封裝件，其中該塊 料特性爲電阻率。 5 ·如申請專利範圍第1項之半導體封裝件，其中形成 該通孔之該材料具有比該導電矩陣較低之熱膨脹係數。 6. 如申請專利範圍第1項之半導體封裝件，其中該導 電矩陣包含由銅（Cu )、金（Au )、鋁（A1 )、鎢（W ) 、銀（Ag)、共溶焊料以及非共熔焊料構成之族群的選出 之一° 7. 如申請專利範圍第6項之半導體封裝件，其中該共 1332693 熔焊料包含由錫-錯（Pb/Sn)焊料以及金-錫（Au/Sn)焊 料構成之族群之一。 8. 如申請專利範圍第1項之半導體封裝件其中該塡 充粒子包含由矽土、礬土、氮化硼、鎢、因鋼（Invar)、 超因鋼（Super InVar )以及科華合金（K〇var )所構成之 族群的選出其中之一。 9. 一種形成穿洞通孔之方法，包含： 自晶粒移除材料；以及 於該晶粒中形成與該晶粒不同導電材料的導電通孔， 該導電通孔的該導電材料爲形成連續相之導電矩陣以及形 成於該導電矩陣內而呈現散佈相之嵌入粒子之合成，其中 該嵌入粒子包含鐵磁材料。 1 〇 _如申請專利範圍第9項之方法，其中於該晶粒中 形成導電通孔進一步包含由電鏟、化學蒸氣沉積（Cvd) 、物理蒸氣ί几積（PVD)、噴鑛、蒸發、噴射蒸氣沉積以 及回塡含有塡充粒子之焊料所構成之族群的其中之一。 11.如申請專利範圍第10項之方法，其中該電鍍進一 步包含提供驅動勢給第一濃度之該嵌入粒子，以導致該導 電通孔之該材料中之該嵌入粒子的第二濃度。 1 2 .如申請專利範圍第1 1項之方法，其中該嵌入粒子 的該第二濃度大於該嵌入粒子的該第一濃度。 1 3 ·如申請專利範圍第】1項之方法，其中該驅動勢包 含由重力以及磁場所構成之族群的其中之一。 1 4.如申請專利範圍第9項之方法，其中該導電通孔 -2- 1332693 罐 之塊材具有與該導電矩陣不同之材料特性。 15.如申請專利範圍第14項之方法，其中該 爲熱膨脹係數’該導電通孔之材料具有比該矩陣 膨脹係數。 1 6.如申請專利範圍第9項之方法，其中該 由銅（Cu)、金（Au)、鋁（A1)、鎢（W)、 、共熔焊料以及非共熔焊料所構成之族群的選出 〇 1 7 .如申請專利範圍第1 6項之方法，其中該 包含由錫-鉛（Pb/Sn)焊料以及金-錫（Au/Sn) 成之族群的其中之一。 18.如申請專利範圍第9項之方法，其中該 包含由矽土、礬土、氮化硼 '鎢、因鋼（Invar) (Super Invar)以及科華合金（Kovar)所構成 選出其中之一。 1 9 . 一種半導體封裝件，包含： 積體電路；以及 該積體電路內之穿洞通孔，其中該穿洞通孔 屬矩陣及嵌入於該金屬矩陣中之鐵磁塡充粒子所 成。 20·—種具有通孔之裝置，包含： 矽基底；以及 該矽基底內之穿洞通孔，其中該穿洞通孔包 矩陣及嵌入於該金屬矩陣中之鐵磁塡充粒子所組 材料特性 更低之熱 矩陣包含 銀（A g ) 其中之一 共熔焊料 焊料所構 嵌入粒子 、超因鋼 之族群的 包含由金 組成的合 含由金屬 成的合成 -3- 1332693 2 1 .—種形成通孔之方法，包含： 自矽基底移除材料；以及 於該矽基底中形成與該矽基底不同導電材料的導電_ 孔，該導電通孔的該導電材料爲形成連續相之導電矩陣以 及形成於該導電矩陣內而呈現散佈相之鐵磁嵌入粒子之合 成。 -4 -
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