TWI325110B - Memory hub and access method having internal row caching - Google Patents

Memory hub and access method having internal row caching Download PDF

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Publication number
TWI325110B
TWI325110B TW092121285A TW92121285A TWI325110B TW I325110 B TWI325110 B TW I325110B TW 092121285 A TW092121285 A TW 092121285A TW 92121285 A TW92121285 A TW 92121285A TW I325110 B TWI325110 B TW I325110B
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memory
column
coupled
interface
request
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TW092121285A
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TW200421087A (en
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M Jeddeloh Joseph
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Micron Technology Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Description

-ι\ ：- Λ -- 玖、發明說明： 【發明所屬之技術領域】 本％明係關於電腦系統，且特別有_於__種具有_記憶 體市線益之電腦系統’該記憶體集線器係將數個記憶體裝 置耦合至一處理器或其他記憶體存取裝置。 【先前技術】 電知系統係使用諸如動態隨機存取記憶體（DRAM)之類 己憶體裝置以儲存處理器所存取之指令及資料。記憶體 破置通书用作電腦系統中之系統記憶體。在一典型電腦系 、-先中’處理益係透過系統匯流排及記憶體控制器以與系統 ^憶體相通信。處理器發出—記憶體請求，其包括記憶體 才曰7如項取指令，以及包括一位址，該位址指定欲被讀 取之貝料或指令的位置。記憶體控制器係使用這些指令及 位址以產生適當的命令信號’以及產生行及列位址，其係 被施加至系統記憶體。回應於該等指令及位址資料在系 統兄憶體及處理器之間傳遞。記憶體控制器通常為一系統 控制器的一部f分，而該系統控制器另外包括匯流排橋接電 路，其用以將該處理器匯流排耦合至一擴充匯流排，如pci 匯流排。 雖然記憶體裝S之操作速度持續增力口，然此增加並無法 與處理器操作速度之增加並駕其驅。將處理器麵合至記憶 體裝置之記憶體控制H ’其操作速度之增加已經更趙緩 了。記憶體控制器及記憶體袭置之相對低速限制了處理写 與記憶體裝置間之資料頻寬。 除了處理态及記憶體裝置間之頻寬受限外，電腦系統之 87196-980921.doc 1325110 執行亦因料（lateney)問題而受到限n料問題係御 加了由系統記憶體裝置讀取資料所需的時間。更明確： 之，當一記憶體裝置讀取命令被柄合至-諸如同步 DRAM(“SDRAM”）裝置的系統記憶體時，僅於數個時脈週期 之延遲後，該讀取資料才由兮_ 貝了叶不由邊SDRAM裝置輸出。因此， SDRAM裝置可以高資料速率夾 寸疋+來冋步地輪出叢發資料（bum data)’然而’這種於初始提供資料期間内的延遲，卻會造 成使用這類的SDRAM裝置的電腦系 J电細系統的操作速度大幅降 低0 一種減輕上述記憶體潛時問題之方法，乃是使用多個透 過記憶體集線器而麵合至處理器的記憶體裝 體集線器架構内，一李统枇制々 l，z' 數個2…… 或記憶體控制器係耗合至 數個δ己隐體模組，母一記憶體 ^ ^ ^ ^ ^ 供、、且係包括—耦合至數個記 隱體裝置之記憶體集線器。該 々愔驴# 隐體集線器係有效地安排 。己隐體6月求及回應於控制器及 m n- iEm ^ ^ ϋ u肢裒置之間的路徑。使 用此架構之電腦系統可擁有較 汊 态可存取一記憶體裝置，而 处 4, ^ ^ 守另一 §己憶體裝置正回應一 先刖的δ己憶體請求。舉例而言， 心 至季统中地里15可輪出所寫入資料 至糸統中之邊寺記憶體裝置的告一 十 -記憶體裝置則正準備提供讀 @同時系統中另 體集線态之電腦系統可提 使用。己
錄插备r > 較佳效施’然而其時常因A 種種因素而無法以最佳速度操作。例吟吊口為 可提供雷艦备 雖5己憶體集線器 J扠仏兒恥糸統一較大記憶體頻 1 55 都之臀日卑ρ弓BS 乃θ受制於上述類 歪之潛日守問題。更明確言之 义頰 值详眘袓口士 …田另—记憶體裝置準備 傳达貝枓日守，該處理器可與— 有 己隱體裝置通信，但在來自 87196-980921.doc
LIU 二=;Γ資料可被使用之前，有時必須接收來自另 。己L、體裝置之賢料。在資料 前被另—記憶體裝置接收而方可㈣之广體裝置接收之 會繼續讓電腦系統之操作速度更為降低情況下，潛時問題 種已用來減少記憶體裝置内潛時時間的技 取記憶體，其係儲存最近由系統記憶體 ' 2憶體-般為靜態隨機存儲存記憶體(二=广 其與典型上用作系統記憶體的動態隨機…:體 (“dram”）相比，只目士 4上 崎风仔取。己fe、體
^ ^ 有相▲短之存取時間。此外，SRAM 器，般乃透過—處理器匯流排來直接搞合至處理 記憶體^ ^系統㈣11等類似裝置’後者對DRAM系統 〜-疋，、1情況。由於快取記憶體之速度較快，並 t記憶體比較靠近處理器，結果，使用快取記憶體可大幅 降低記憶體讀取操作時之潛時情況。 ‘ 存；：ΓΓ記憶體已經減少習知電腦系統中的記憶體 存取/曰寺，然而，於使用記憶體集線器的電腦系統中快 尚未以一種可提供最佳效能的方式來被使用。 ^其疋與典型記憶體集線器系統記憶體之遠遠大得多的容 董相比’由於快取命中（Caehe Hit)較不會發生， 記憶體有限的儲存容量乃造成快取記憶體之價值更低。、將 二4=至隨後可能為記憶體請求對象的快取記憶體時所 ㈣㈣題更為嚴重„更明七之’报難將隨後 所需資枓透過記憶體控制器而由全部的記憶體槿植耦人至 處理器，接著再將該資料由處理器輕合至快取記㈣:再 87196-980921.doc %1月74: 丨狂替換頁 者 > * 而耦合至卢使用多個記憶體集線器及一透過處理器匯流排 取-致性Γ理11之絲記憶體的€腦线之中，欲維持快 的硬體資、vTheeGhereney)，乃是十分困難的，會需要龐大 Λ、以維持快取一致性。此外，為维牲也& 所須之時Η 马維持快取一致性 體之諸心’可能會讓記憶體性降低到喪失使用快取記憶 優點的程度。 器=之1要—種電腦架構，該電腦架構提供記憶體集線 低，藉此：‘點？使這類系統中常見之潛時問題降至最 r 供具向頻寬及低潛時之記憶體裝置。 【發明内容】 個记憶體模組係耦合至一位一 器。該等記憶體模組當中每一者传包括統内之控制 以及一印，! 奋邮 考糸匕括複數個記憶體裝置 ° 體集線器。該記憶體集線芎俜包& Μ . 控制器之鏈接人而、 干咪盗係包括-耦合至該 體裝置介& ;| ，以及一耦合至該等記憶體裝置之記憶 求，用以料i & 术目該控制态之記憶體請 憶體=:Γ憶體裝置當中至少之一者内的-列的記 記声體f置:予取°錢接介面傳送該等記憶體請求至該 至該等記憶體裝置，以對該等記憶體裝置當= 之一者㈣-列的記憶體單元進行存取。 回應至少該等記憶體請求當中至少 ^接者 V愔舻驻罢A 干者而接收來自該等 5己隐體裝置之所項取資料。料記憶體集線器當中 亦包括^合至該記憶體裝置介面之列快取記憶體，用以 回應該等記憶體請求當巾至少之—者而接收及儲存所 87196-980921.doc 之資料。-包含於該記憶體集線器内的排序器係耦合至該 鏈接介面，該記憶體裝置介面'以及該列快取記憶體。該 排序器係ϋ及搞合記憶#請求至t亥記憶體褒置介面以 從-列的記憶體單元來讀取資料，該列的記憶體單元係回 應從該鏈接介面至傳送至該記憶體裝置介面之記憶體請求 而被存取。來自回應所產生之記憶體請求而被存取之該列 的記憶體單元的所讀取資料亦被儲存於該列快取記憶體 内於車义佳的it況下，當s己憶體請求不被從該控制器接收 時’該排序器係產生該等記憶體請求。 【實施方式】 圖1所不為根據本發明之一範例之電腦系統1〇〇。電腦系 統1 〇 〇係包括一處判i 〇 4 ’其用以執行各種計算功用，譬如 是執行用來實施特定計算及工作之特定軟體。處理器刚包 括-處理器匯流排106’其通常包括：一位址匯流排、一控 制匯流排，以及一資料匯流排。該處理器匯流排106典型上 係耦合至-快取記憶體108’其如先前所言，通常為靜態隨 機存儲存B(SRAM)。最後，處理II®流排應雜合至-系 、.先&制益110,其有時候亦稱為「北橋（N〇rth Bridge)」或「記 憶體控制器」。 系統控制5 110係為其他種種元件供作—個通往處理器 104之通彳5路徑。更明確言之，系統控制器1⑺包括一圖形 埠°亥圖形埠典型上係耦合至—圖形控制器丨12，該圖形控 制器112依序地耦合至_視訊終端ιι4。系統控制器u。亦耦 合至一或更多個輸入裝置118，例如：一鍵盤或一滑鼠，以 87196-98092l.doc
令一刼作者能與電腦系 ^ ^ ^ 乎、、，先100聯蘩。典型上，電腦系統100 亦包括一或更多個輸出赉 / j ®裝置120，例如為一印表機，其經 糸統控制器11 〇而搞合至声… 处里益1 〇4。一碑更多個資料儲存裝 置124典型上亦透過系統^ ^ ^ ^ % ϊ工利為110而耦合至處理器丨〇4，以 ^處理器刚能儲存資料，或由内部或外部儲存媒體（未顯示） 來擷取f料。典型儲存裝置124之範例係包括硬碟及軟碟、 磁帶E ’以及唯讀光碟（c〇mpact μ _响咖〇心 CD-ROM)。 ’ 系統控制器合至數個記憶、體模组l3〇a，b n，其乃 供作電腦线1G G之系統記憶體。記憶體模組13 G於較佳的情 况下係透過·"南速鏈接（High_Speed而耗合至系統 控制H1H)’該高速鏈接可為—光學或電學通信路徑，或任 其他種類之通信路徑。舉例而言：於高速鏈接134被實施成 為一光學通信路徑之情況下，該光學通信路徑譬如可為一 或更多個光學纖維之m這種狀況下，系統控制器ιι〇 及記憶體模組係包括一耦合至該光學通信路徑之光學輸入 /輸出淳或多個不同的輸入及輸出埠。記憶體模組13〇顯示為 耦合至以多點排列（Multi-Drop Arrangement)之系統控制器 no，在這種多點排列中，該單一的高速鏈接134乃耦合至全 部的記憶體模組130。然而，須了解，亦可使用其他種類的 拓樸結構’譬如為點對點耦合排列（Point_t〇 p〇int C〇upling Arrangement)，其使用不同的高速鏈接（未顯示）以將每一個 記憶體模組130耦合至系統控制器丨丨…亦可使用一種交換拓 樸結構（Switching Topology)，其中系統控制11〇係透過一開 87196-9S092I.doc -J0-
1S 1325110 货年丨日f二:樓頁 關（Switch)(未顯示）而選擇性地鉍 . k详f生地耦合至各記憶體模組13〇。對 熟習此技藝者而言，其他種可使帛> 4 u 便用之拓樸結構乃顯而易見。 該等記憶體模組130當中每一者係 β 1 丁、匕枯έ己憶體集線器14〇， 其用以控制對六個記憶體裝置148之存取，其如圖2所示之範 例中，乃為同步的動態隨機存取記憶體（SDRAM)裝置。缺 而’可使用較少或較多數目之記憶體裝置148，當然，亦可 使用SDRAM裝置以外的其他種記恃 U體裝置。記憶體集線器 i40係透過匯流排系統15G_合至系統記憶體裝置爾中 每-者，其通常包括：一控制匯流排、一位址匯流排，以及 一資料匯流排。 圖！之記憶體集線器刚的一個範例乃顯示於圖2。記億體 集線器14G包括-鏈接介面152，其係耗合至上述高速鍵接 13[鏈接介面152之性質乃依高速鏈接134之特徵而定。例 如：在使用光學通信路徑來實現高速鏈接n4之情況下，鏈 接介面152乃包括一光學輸入/輸出埠，並且透過光學通信路 徑而將光學訊號轉換成電子訊號。於任何情況下，鏈接介 面152較佳的情況是包括一緩衝器，譬如是一先進先出緩2 器154，用以在δ己憶體請求透過高速鏈接134而被接收時接 收及儲存這些記憶體請求。這些記憶體請求係被儲存於緩 衝器154之内，直到它們可被記憶體集線器14〇處理為止。 當記憶體集線器140能夠處理一記憶體請求時，儲存於緩 衝器154當中的一個記憶體請求即被傳送至—記憶體排序 器160。該記憶體排序器16〇係將記憶體請求由系統控制器 110之輸出格式加以轉換成一種可為記憶體裝置148使用之 87196-980921.doc U25110 修：皆換頁 格式。此重新格式化之請求訊號通常包括記憶體命令訊 號’其乃由記憶體集線器140所接收之記憶體請求内所含的 記憶體命令來導出，以及包括列及行位址訊號，其乃由記 憶體集線器14〇所接收之記憶體請求内所含的一位址來導 出。在記憶體請求為一寫入記憶體請求之情況下，重新格 式化之請求信號通常包括寫入資料信號，其乃由記憶體集 線·« 140所接收之§己憶體請求内所含的寫入資料來導出。例 士田D己憶體裝置148記憶體裝置148為習知DRAM裝置，記 憶體排序器16〇會輸出複數個列位址訊號，一列位址選通 Ww Addfess Strobe ; “㈣”)訊號一主動高寫入/主動低 讀取訊號（“聰*，，）、數個行位址訊號，及以-行位址選通 (上、Address Str〇be ; “CAS”）訊號。重新格式化之記憶 體月求於較佳的情況下，乃以將被記憶體裝置⑷使用之順 序，來由排序器160輸出。 、 己隐體排序益16〇將這些重新格式化之記憶體請求施加 至-記憶體裝置介面166。記憶體裝置介面 記憶體裝置148之料科；^ 貝U徠依 八特徵而疋。於任何情況下，此記憶體裝置 ⑽，其用以於-或衝4如為—腦緩衝器 ..* 一夕個5己憶體清求由鏈接介面152而被接 :時，接收及儲存這些記憶體請求。 存於緩衝器168,直5 日χ ι 一。匕隐體叫求乃儲 而，在記憶體C被記憶體裝置148處理為止。然 記憶體裝置介==存:個記憶體請求之情況下， 些記憶體請求可以錢體請求重新排序，以令這 二八他種順序來被施加至這些記憶體 87196-980921.doc 12 m 裝置。舉例言之，這此愔 求之方〇 一己隐體s月求可依一種會造成某種讀 方式來儲存於介面166 請求（嬖如寫人μ、 s如疋欲於其他種 冩入凊求）之前被處理之讀取請求。 -體凊求予以上係描述為由記憶體集線器140以 憶體’而這種格式與這些記憶體請求被施加至記 來自V理各式不相同。然而’系統控制器110可改為將 —< S1G4 (圖⑽記憶體請求重新格式化為一種可被 5己憶體裝置148所使用之格式。在 4叭在知·種狀況下，排序器160 不需將記憶體諳灰舍, 重新秸式化。相反地，排序器16〇僅將被 重新格式化之記憶體請求訊號依記憶體裝置148使用所需 順序來加以排程。用^^ .. a ;一或更夕個記憶體請求之記憶體請 ’訊號隨後乃被傳送至記憶體裝置介面166，故其可於隨後 施加至記憶體裝置148。 如以上所解釋，使用記憶體集線器的缺點之—，乃是這 些記憶體集線器有時候會造成潛時增加。同樣如上所述， -於處理器104内或_合至處理器匯流排1G6 (圖D之快取記 憶體，其為減少記憶體讀取潛時之習知手段，然並不適用 於-種使用記憶體集線器之記憶體系統。於圖2所示之記憶 體集線器140範例，乃藉由於記憶體集線器14〇當中每一者中 包含-列快取記憶體17G之方式，來提供相當:之記憶體讀 取潛時。列快取記憶體170於設計上乃類似於習知快取系 統’其包括一Μ料記憶體（未顯示），_標籤記憶體（未顯 示），以及習知位址比較邏輯（未顯示）。列快取記憶體170 係將多個記憶體單7L之—或更多個定址列中所含的資料， 87196-980921.doc 13
1325110 儲存在模組140之一或更多個記憶體裝置ι48中。列快取記憶 - 體170係經由鏈接介面152來接收數個形成一記憶體請求之 部分的位址，這些位址係與被快取之資料相比較。在位址 相付之情況下’即表示被記憶體請求所提取之資料乃儲存 於列快取記憶體170中，則記憶體170輸出所請求的資料及— 表示快取命中之列命中（R0W HIT)訊號。此R〇w HIT訊號會 被施加至一多工器176’以使得來自快取記憶體ι7〇之資料能 參被耦合至鏈接介面152。於列快取遺漏（row cache miss)之情 況下，則多工器176將來自記憶體裝置介面166的資料傳送到 鏈接介面152。此ROW HIT訊號亦被施加至記憶體排序器 ' 160 ’以便於列命中之情況下排序器不會將記憶體請求耦合 至記憶體裝置介面166，原因在於該記憶體請求所要求的資 料已經被列快取記憶體17〇提供。 雖然列快取記憶體170僅可儲存來自先前已存取列中之 數個行之資料，當記憶體集線器14〇不忙於回應系統控制器
110之記憶體請求時，記憶體170較佳上係從被快取的列中許 多或所有的行來預先提取資料。更明確言《，記憶體排序 器160係包括習知電路，該習知電路係用以追蹤—被存取的 列中那些行已將其中所儲存的資料傳送至列快取記憶體 17〇。當排序器160不忙於服務鏈接介面152 時’則排序請產生記憶體請求，這些記憶二= 加至記憶體裝置介面’以令一定址列之剩餘行中所儲存之 資料被傳送至列快取記憶體170。結果，由於典型上是對於 相同列中之-連串記憶體位置來進行記憶體存$，因此列 87196-980921.doc •14· iS] 卸^丨日修正替換頁 =記憶體m可能會儲存後續記憶體請求中欲被掏取之 記憶體集線器M0能使用種種不同的程序，以處理—指向 :二’體衣置148 t之-新的列的記憶體單元之後續記憶 體h未。例如：若列快取記憶體17〇有能力儲存來自多於一 =之資料，則排序器⑽可簡單地使儲存於後續存取列中的 資料傳送至列快取記憶體17〇。若列快取記憶體⑺僅有能力 儲存來自單—列的記憶體單元之資料，或快取記憶體17〇已 'Ϊ!!達其容量，則儲存於新存取列之記憶體單元的資料可 簡單地覆寫先前所儲存之資料。 雖未於圖2中顯示或於Μ討論，記憶體集線器刚較佳而 言係包括用以使用記憶體快取技述以維持快取—致性之電 路。例如：在-個寫人至—位置之記憶體請求接續—個自 7 一位置讀取之記憶體請求的情況下，集線器14〇可採用一 「寫入（Write Through)」操作模式或一「寫回（Wrhe Bac 操作模式。 經由上述應了解，雖然本發明之特定實施例為了說明目 的而於文中样述’然而可在不違反本發明之精神和範圍下 作各式修改。因此，本發明僅受限於後附之申請專利範圍。 【圖式簡單說明】 圖1為一根據本發明範例之電腦系統方塊圖，其中各複數 個記憶體模組包括一記憶體集線器。 圖2為一用於圖1之電腦系統之記憶體集線器方塊圖。 【圖式代表符號說明】 87196-980921.doc 1325110 ir.u
100 電腦糸統 104 處理器 106 處理器匯流排 108 快取記憶體 110 系統控制器 112 圖形控制器 114 視訊終端 118 輸入裝置 120 輸出裝置 124 儲存裝置 130a,b... η記憶體模組 134 高速鏈接 140 記憶體匯流排 148 記憶體裝置 150 匯流排系統 152 鏈接介面 154 先進先出緩衝器 160 記憶體排序器 166 記憶體裝置介面 168 緩衝器 170 列快取記憶體 176 多工器 is 1 87l96-980921.doc -16-

Claims (1)

  1. 拾、申請專利範園： 一種電腦系統，包括： 一中央處理器（“CPU”）； 一系統控制器，耦合至Γρττ 主CPU ’该系統控制器具有一輸 入埠及一輸出埠； 一輸入裝置，經由系统批 T、九徑制器耦合至該CPU ; 一輪出裝置，經由系绥批制口 于研*控制态耦合至該CPU ; 一儲存褒置，經由系統控制器輕合至該cpu; 複數個記憶體模組，該等記憶體模組當中每一者係包 括： 複數個記憶體裝置；及 一記憶體集線器，其包括： 一鏈接介面’其具有一輸入埠及一輸出埠， 該鏈接’I面經由該輸入埠接收記憶體請求，以回應該等 記憶體請求而存取該等記憶體裝置當中至少一者内之一 列的記憶體單元，並經由該輸出埠輸出資料； —S己憶體裝置介面’其耦合至該等記憶體裝 置’ 4 β己憶體裝置介面可操作以將記憶體請求耦合至該 記憶體裝置’用以存取該等記憶體裝置當中至少之一者 内的一列的記憶體列單元，以及用以回應該等記憶體請 求當中至少若干者而接收所讀取之資料，該等記憶體請 求當中至少若干者係耦合至回應經由該鏈接介面而傳送 至該記憶體裝置介面之記憶體請求之該等記憶體裝置； 一列快取記憶體，其耦合至該記憶體裝置介 87196-990125.doc 1325110 面，用以由一列的記憶體單元接收及儲存所讀取之資 料，該列的記憶體單元係回應於被由該記憶體裝置介面 搞合至該等記憶體裝置當中至少之一者之該等記憶體請 求當中至少之一者而被存取’以及 一排序器，其耦合至該鏈接介面及該記憶體 裝置介面及該列快取記憶體’該排序器可操作以產生及 耦合記憶體請求至該記憶體裝置介面，以由所存取之列 的記憶體單元内的記憶體單元來讀取資料，由所存取之 該列的記憶體单元所讀取之該資料係被儲存於該列快取 記憶體内；及 一通信鏈接，其將該系統控制器之該輪出埠耗合至 該等記憶體模組當中每一者之該記憶體集線器内的該輸 入埠，以及將該系統控制器之該輸入埠耦合至該等記憶 體模組當中每一者之該記憶體集線器内的該輸出埠。 2·如申請專利範圍第！項之電腦系統，其中該記憶體裝置介 面更包括：一先進先出緩衝器，纟可操作以接收及 自該鏈接介面及自該排序器所接枚之記憶體請求，以及 將所儲存之該等記憶體請求依其被接 等記憶體裝置當中至少之一^ 只斤料至遠 3:申第1項之電腦系統，其中該鏈接介面包 請求，且將所儲存之該等=作以接收及儲存記憶體 傳送至該記㈣裝置介面4求依其被接收的順序 4.如申凊專利範圍第3項之電腦系統，其中該記憶體裝置介 87196-990125.doc 面更包括·一先進先出緩衝器，其可操作以接收及儲存 自4鏈接介面及自該排序器所接收之記憶體請求，且將 諸存之°亥等5己憶體請求傳送至該該等記憶體裝置告中 至少之一者。 田γ 5·如申凊專利範圍第丨項之電腦系統，其中該記憶體裝置係 包括動態隨機存取記憶體裝置。 μ 6. 如申請專利範圍第丨項之電腦系統其中該排序器可操作 以輸出一位址，該位址係被包含於由該鏈接介面所接收 之每一個所讀取的記憶體請求内，以及其中該列快取記 憶體係可操作以由該排序器接收該位址，以判定該記憶 體請求所要求的資料是否被儲存於該列快取記憶體内， 若該记憶體請求所要求的該資料被儲存於該列快取記憶 體内時，則s玄列快取記憶體輸出所讀取之該資料以及產 生一命中讯號，若該記憶體請求所要求的該資料未被儲 存於該列快取記憶體内時’則該列快取記憶體產生一列 遺漏訊號。 7. 如申請專利範圍第6項之電腦系統，更包括一多工器，其 具有多個資料輸入’其耦合至該列快取記憶體及耦合至 該記憶體裝置介面’一資料輸出’其耦合至該鏈接介面， 以及一控制輸入’其係被躺合以由該列快取記憶體接收 該命中訊號及該列遺漏訊號，該多工器係回應該列遺漏 訊號，以輛合來自該s己憶體裝置介面之所讀取之資料， 以及回應該命中訊號’以搞合來自該列快取記憶體之所 讀取之資料。 87196-990125.doc 1325110
    8.如甲請專 作以產生及麵合記憶體請求至該記憶體裝置介=係可知 被存取之列的記憶體單元内之⑽ =從 鏈接介面傳送至該記憶體裝置介面時被求未由該 9.如申請專利範圍第1項之電腦系統，其中… :輸入埠及該輸出埠係包括-組合之制:: 口至5亥通錢接，以及其中該等記憶 Ί 者之該輸入埠及該輸出埠係包括·· _組：态，中母-埠，其耦合至該通信鏈接。 '、D之輸入/輸出 H)·如申請專利範圍第9項之電腦系統，其 -光學通信鏈接，其中該系統控制二：接包括 出埠係包括：一光學之輸入/輸出埠，其：：入埠及該輪 信鏈接’以且其中該等記憶體集線器當中：，亥先學通 入及該輸㈣係包括：―個別之衫=之該輪 合至該光學通信鏈接。 輸出埠，其耦 一種電腦系統，包括： 一中央處理器（“Cpu”）； 二系統控制ϋ，-合至CPU，㈣統 入蟑及一輸出琿； 盗具有一輪 -輸入裝置，經由系統控制器耦合至 -輸出裝置，經由系統控制器耦合至該， -儲存裝置’經由系統控制器輕合至該， 複數個記憶體模組，該等記憶體模組 ， 田肀每一者係包 87196-990125.doc ；— 括： 複數個記憶體裝置；以及 一記憶體集線器，其包括： 一鏈接介面，其接收記憶體請求，以存取該 等記憶體μ當中至少之—者内《-列《記憶體單元以 -記憶體裝置介面，其麵合至該等記憶體裝 置，該記憶體裝置介面可操作以耦合記憶體請求至該記 憶體裝置，以存取該等記憶體裝置當中至少之一者^ ° 一列的記憶體單元，並回應於該等記憶體請求當中至少 若干者以接收所讀取之資料，該等記憶體請求;中至=、 右干者係搞合至該等記憶體裝置’該等記憶體裝置回應 經由該鏈接介面傳送至該記憶體裝置介面之記憶體請 求； -排序器，其耦合至該鏈接介面及該記憶體 裝置介面及該列快取記憶體，該排序器可操作以輸出一 位址，該位址係被包含於由該鏈接介面接收之每一個所 讀取的記憶體請求内； 一列快取記憶體，其耦合至該記憶體裝置介 面，用以接收及儲存從一列的記憶體單元所讀取之資 料，該列的記憶體單元係回應於由該記憶體裝置介面搞 合至該至少一個記憶體裝置之該等記憶體請求當中之一 者而被存取，該列快取記憶體更可操作以由該排序器接 收該等位址’以判定該記憶體請求所要求之資料是否儲 存於該列快取記憶體内，若該記憶體請求所要求之該資 87196-990125.doc 1325110 料被儲存於該列快取記憶體之内時，則該列快取記憶體 可輸出所讀取之該資料及產生一命中訊號，若該記憶體 請求所要求之該資料未被儲存於該列快取記憶體之内 時，則該列快取記憶體產生一列遺漏訊號；以1
    一多工器，其具有多個資料輸入，其耦合至 該列快取記憶體及耦合至該記憶體裝置介面，一資料輸 出，其耦合至該鏈接介面，以及一控制輪入，其係被耦 合以由該列快取記憶體接收該命中訊號及該列遺漏訊 號，該多工器係回應該列遺漏訊號而耦合來自該記憶體 裝置之所讀取的資料，且回應該命中訊號而耦合來自該 列快取記憶體之所讀取的資料， 一通信鏈接，其將該系統控制器之該輪出埠耦合至 該等記憶體模組當中每一者之該記憶體集線器内之=入 埠，且將該系統控制器之該輸入埠耦合至該等記憶體模 組當中每一者内之該記憶體集線器之該輪出蜂。
    12.如申請專利範圍第u項之電腦系統，其中該記憶體裝置 介面更包括：一先進先出緩衝器，其可操作以接收^儲 存自該鏈接介面及自該排序器所接收之記憶體請求，以 及將所儲存之記憶體請求依其被接收的順序傳送至該該 等記憶體裝置當中至少之一者。 13.如申請專利範圍第n項之電腦系統，—先進先出緩衝 器其可操作以接收及儲存記憶體請求，且將所儲存之 記憶體請求依其被接收之順序傳送至該記憶體裝置介 面。 87196-990125.doc
    14=申請專利範圍第13項之電腦系統，其中該記憶體裝置 更c括 先進先出缓衝器’其可操作以接收及儲 存自該鏈接介面及自該排序器所接收之㈣體請求，以 及將所儲存之記憶體請求依其被接收之順序傳送至該等 記憶體裝置當中至少之一者。 以 其中該鍵接介面係 15.如申請專利範圍第1〗項之電腦系統 包括一光學輸入/輪出埠。 六丫孩等記憶 16. 如申清專利範圍第u項之電腦系統 置係包括動態隨機存取記憶體裝置 17. 如申請專利範圍第u項之 λ it » ^ ^ 罨細系，·克，其中該系統控制器 μ輸入埠及s亥輸出埠包括— 合至該通信鏈接，以及輸出埠’其麵 一者H ^ /、中該專記憶體集線器當中之每 者之5亥輸入埠及該輸出埠 母 埠，其耗合至該通信鏈接。、 &之輸入/輸出 18. 如申請專利範圍第17項之電 包括一光學通信鏈接，其 、，，，其中該通信鏈接係 該輸出埠係包括一光學之〜系統控制器之該輸入埠及 通信鏈接，以及其中該等/入/輸出埠，其耦合至該光學 輸入埠及該輸出埠係包括：憶體集線器當中每-者之該 耦合至該光學通信鏈接。個別之光學輸入/輸出埠，其 87196-990125.doc 1325110 柒、指定代表圖= (一) 本案指定代表圖為：第（1 )圖。 (二) 本代表圖之元件代表符號簡單說明：
    100 電腦糸統 104 處理器 106 處理器匯流排 108 快取記憶體 110 系統控制器 112 圖形控制器 114 視訊終端 118 輸入裝置 120 輸出裝置 124 儲存裝置 130a,b...r 1 記憶體模組 134 高速鏈接 140 記憶體匯流排 148 記憶體裝置 150 匯流排糸統 捌、本案若有化學式時，請揭示最能顯示發明特徵的化學式： 87196-980921.doc
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