I d 經濟部中央標準局員工消費合作社印製 高 之 修正: 補W. --- 1~ 五、發明説明（3 時間為已知。如果▲流排受 . # if yi μ ^ ^ 夂則知道在某一數目之 處】器：31供該請求使用。何時資料可轉移 在匯<到限制’因為處理器必須遠在資料轉移可 4排上開始之前即請求料匯㈣進行存取。 流排受到㈣，職流㈣後不可科其他用途。 因此，需要一種用以提供資料給多個處理器之系統及方 ^ ’且㈣系統及方法提供低等待時間之第—資料存私及 网度彈性。本發明滿足此種需求。 發明概要 本奋明提供一種用以在一電腦系統中提供資料給一匯流 排之方法及系統。該電腦系統包含—記憶體。該匯流排跟 務多個處理器。該種方法及系統決定在已自記憶體存取資 料以後是否旨流排可用以轉移資料ϋ匯流排可供使 用’則該方法接著轉移資料至匯流排。 根據本文所揭示之系統及方法，本發明提供、—具有低等I d The amendment printed high by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs: Supplement W. --- 1 ~ V. Description of the invention (3 time is known. If ▲ is accepted. # If yi μ ^ ^ 夂 then know At a certain number of devices: 31 for this request. When data can be transferred in the sink < to the limit 'because the processor must request the sink to access it long before the data transfer can start on 4 rows. It is not possible to use it for other purposes after the job stream. Therefore, there is a need for a system and method for providing data to multiple processors ^ and a system and method that provides low latency—data storage and privacy Flexibility. The present invention meets this need. SUMMARY OF THE INVENTION The present invention provides a method and system for providing data to a bus in a computer system. The computer system includes-memory. The bus handles multiple processes This method and system decides whether the bus can be used to transfer data after the data has been accessed from memory. The bus is available for use. Then the method then transfers the data to the bus. According to the system disclosed herein And methods, the present invention provides,
待時Ρ之第一資料存取友高度彈性的資料轉移，因而提 整體系統效能V 附圖簡短說明 圖1是一服務多個處理器之系統之概圖的方塊圖。 圖2¾—提供資料給多個處理器之|統系統的方塊圖。 圖3 ·;疋一根據該種方法及系統來提供資料給多個處理器 系統A方塊圖。。 圖式无件符號說明_ & 1，110,200系統 2-1至2-n處理器jin 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)The first data access user of P will be highly flexible in data transfer, and thus improve the overall system performance. V Brief description of the drawings Figure 1 is a block diagram of an overview of a system serving multiple processors. Figure 2¾—Block diagram of a system that provides information to multiple processors. Figure 3. A block diagram of system A providing data to multiple processors according to the method and system. . Schematic description of symbolless parts _ & 1,110,200 system 2-1 to 2-n processor jin 6 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before (Fill in this page)
五、發明説明 A7 B7 經濟部中央標準，局員工消費合作社印製 發明領域 本發明係關於一種用於記'憶體控制器之資料存取的方法 及系統，且更明確地説係關於一種用以提供一緩衝型記憶 體控制器之低等待時間資料存取的方法及系統，且該記憶 體控制器更明確地説是一服務多個處理器之控制器，例如 S Μ P記憶體控制器。 發明背景 目前服務多個處理器之記憶體控制器，例如S ΜΡ記憶體 控制器，一般運用單一資料匯流排來服務所有處理器。在 任何時間當一處理器試圖自記憶體讀取資料時，記憶體控 制器必須決定如何指配資料匯流排之存取給該處理器。當 如此做時，控制器必須將其他處理器對於匯流排之使用列 入考慮。 雖然一旦一特定處理器之讀取指令開始受到執行則資料 匯流排可受到預留，但是如此會阻止任何其他處理器使用 匯流排，直到該讀取指令結束爲止。此種系統會使系J充大 幅變慢。相對地，該等處理器一般可爲匯流排進行仲裁， 且使用多個路徑線緩衝器來儲存資料，直到匯流排可供使 用爲止。 在一資料請求之開端，通常無法決定何時服務多個處理 器之資料匯流排可供用以服務該請求。匯流排可因爲多種 原因而變爲忙碌。可能存在未決之讀取請求。一般而言， 位址匯流排及資料匯流排是獨立的。當發出一位址時，該 位址具有一標籤。自記憶體讀取之資料具有一相關於其之 4- 本紙張尺度適用中國國家標準（CNS ) A4規格（2I0X·297公釐） 請 先 随- 讀· 背 面-- 冬 i 事 項 妾 裝 訂 I Μ Β7 經濟部中央標準局員工消費合作社印製 五、發明説明（2 ) 對 應 標籤。如此 允許 系 統 發 出多 重位 址 ，而 無需 等候 一 特 定 請求之資料返 回0 除 此 之 外， 資料無 需依 照發 出該 等 請 求之 相同順序來 返回 0 因 此 ，在 任何 時 間可 能存在極 多 未 決 之 讀取請求。 處理 器 也可 發出 寫入 請 求並 置放 寫入 資料 於 -- 匯流排。 因 此，當一處 理器 發 出 一 特定 讀取 請 求時 ，並 不知 道 何 時 匯 流排可用以 轉移 白 記 憶 體讀 取之 資 料至 該處 理器 〇 因 爲 不 知道何時匯 流排 可 供 使 用， 傳統 系 統一 般暫 時儲 存 該 資料於一缓衝器 0 雖 然儲存於一 缓衝 器 使得 記憶 體控 制 器可 服務 多個 處 理 器 但是如此做 需付 出 代 價 0 --- 處理 器 自記 憶體 控制 器 所 接 收 之第一資料 受到 等 待 時 間， 因爲 來 自記 憶體 之資料 必 須 進 入記憶體控 制器 並 載 入 路徑 線緩 衝 器。 此資料維持在 路 徑 線缓衝器， 直到 控 制 器 可爲 匯流排 進行仲裁 爲止 〇 無 論 匯 流排是否立 刻可 供 使 用 ，資料會 儲 存於 緩衝 器許 多 循 環 〇 在 一服務單一 處理 器 之 典型記 憶體 控 制器 中， 資料未 受 到 緩 衝。’如果在 一運 用 多 個 處理 器之典型系 統中 資料未受 到 緩 衝，則一處 理器 可 根 據 對於讀取 資料之接收 的預 期 來 預 留 匯流排。接著可 爲 該 處 理器 預留 匯 流排 。在 該"1買 取 運 作 所 需之全部時間以内無其他處理- 器 可存. 耳又匯 流排 0 因 此 ， 此種無缓衝型建 構 不 適 用於 多處理器系統。 同 樣地，如果 一多 Ml 理 器 系統 未運 用 缓衝 ，則 資料 匯 流 排 可 分割成爲許 多時 窗 如 果自 記憶 體 之轉 移之確切 等待 -5- 讀、 背_ s*-- 意 事 項 再、、 頁 訂 )線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 裝 I d 經濟部中央標準局員工消費合作社印製 高 之 修正: 補W. --- 1~ 五、發明説明（3 時間為已知。如果▲流排受 . # if yi μ ^ ^ 夂則知道在某一數目之 處】器：31供該請求使用。何時資料可轉移 在匯<到限制’因為處理器必須遠在資料轉移可 4排上開始之前即請求料匯㈣進行存取。 流排受到㈣，職流㈣後不可科其他用途。 因此，需要一種用以提供資料給多個處理器之系統及方 ^ ’且㈣系統及方法提供低等待時間之第—資料存私及 网度彈性。本發明滿足此種需求。 發明概要 本奋明提供一種用以在一電腦系統中提供資料給一匯流 排之方法及系統。該電腦系統包含—記憶體。該匯流排跟 務多個處理器。該種方法及系統決定在已自記憶體存取資 料以後是否旨流排可用以轉移資料ϋ匯流排可供使 用’則該方法接著轉移資料至匯流排。 根據本文所揭示之系統及方法，本發明提供、—具有低等V. Description of the invention A7 B7 Central Standard of the Ministry of Economic Affairs, printed by the Bureau ’s Consumer Cooperative Cooperative Field of the Invention The present invention relates to a method and system for recording and accessing data of a memory controller, and more specifically to a method A method and system for providing low-latency data access of a buffered memory controller, and more specifically, the memory controller is a controller serving multiple processors, such as a SM memory controller . BACKGROUND OF THE INVENTION Currently, memory controllers that serve multiple processors, such as SMP memory controllers, generally use a single data bus to serve all processors. At any time when a processor attempts to read data from memory, the memory controller must decide how to assign data bus access to the processor. When doing so, the controller must take into account the use of the bus by other processors. Although the data bus can be reserved once a particular processor's read instruction begins to execute, this prevents any other processor from using the bus until the read instruction ends. Such a system would make Department J significantly slower. In contrast, these processors can generally arbitrate the bus and use multiple path line buffers to store data until the bus is ready for use. At the beginning of a data request, it is often not possible to decide when a data bus serving multiple processors is available to serve the request. The bus can become busy for a number of reasons. There may be pending read requests. Generally speaking, the address bus and the data bus are independent. When an address is issued, the address has a label. The data read from the memory has a related 4--paper size applicable to the Chinese National Standard (CNS) A4 specification (2I0X · 297 mm) Please follow-Read · Back-Winter i Matter 妾 Binding I Μ Β7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Corresponding label. This allows the system to issue multiple addresses without waiting for the data of a particular request to return 0. In addition, the data need not return 0 in the same order as the requests were issued. Therefore, there may be a large number of pending read requests at any time . The processor can also issue a write request and place the write data on the-bus. Therefore, when a processor issues a specific read request, it is not known when the bus can be used to transfer the data read by the white memory to the processor. Because it is not known when the bus is available, traditional systems generally temporarily store This data is stored in a buffer 0. Although it is stored in a buffer so that the memory controller can serve multiple processors, there is a price to do so. 0 --- The first data received by the processor from the memory controller is subject to Wait time, because the data from the memory must enter the memory controller and be loaded into the path line buffer. This data is maintained in the path buffer until the controller can arbitrate the bus. Regardless of whether the bus is immediately available, the data will be stored in the buffer for many cycles. A typical memory control on a single processor Device, the data is not buffered. ’If the data is not buffered in a typical system that uses multiple processors, a processor can retain the bus based on the expectations for receiving the read data. A bus can then be reserved for the processor. No other processors can be stored within the entire time required for the " 1 to purchase and operate. Ear and bus 0 Therefore, this unbuffered architecture is not suitable for multiprocessor systems. Similarly, if a multiple Ml processor system does not use buffering, the data bus can be divided into many time windows. If the exact transfer from memory is waited for -5- read, memorize _ s * ---- (Page order) The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). I d. The amendment printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs: Supplement W. --- 1 ~ V. Description of the invention (3 time is known. If ▲ stream is subject. # If yi μ ^ ^ 夂 then know in a certain number of places] device: 31 for the request. When data can be transferred in the sink < to the limit 'because of processing The device must request the data bank to access it long before the data transfer can start on the 4th row. The stream is affected, and the job stream cannot be used for other purposes. Therefore, a system for providing data to multiple processors is needed. And the system and method provide low latency—data storage and privacy and network flexibility. The present invention meets this need. SUMMARY OF THE INVENTION The present invention provides a method for use in a computer system. Method and system for providing data to a bus. The computer system includes—memory. The bus handles multiple processors. The method and system determine whether the intended bus can be used after the data has been accessed from memory. Transfer data: The bus is ready for use 'Then the method then transfers the data to the bus. According to the system and method disclosed herein, the present invention provides,-has a low level
待時Ρ之第一資料存取友高度彈性的資料轉移，因而提 整體系統效能V 附圖簡短說明 圖1是一服務多個處理器之系統之概圖的方塊圖。 圖2¾—提供資料給多個處理器之|統系統的方塊圖。 圖3 ·;疋一根據該種方法及系統來提供資料給多個處理器 系統A方塊圖。。 圖式无件符號說明_ & 1，110,200系統 2-1至2-n處理器jin 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)The first data access user of P will be highly flexible in data transfer, and thus improve the overall system performance. V Brief description of the drawings Figure 1 is a block diagram of an overview of a system serving multiple processors. Figure 2¾—Block diagram of a system that provides information to multiple processors. Figure 3. A block diagram of system A providing data to multiple processors according to the method and system. . Schematic description of symbolless parts _ & 1,110,200 system 2-1 to 2-n processor jin 6 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before (Fill in this page)
五、發明説明（ 3a A7 B7 10, 10'位址控制晶片 20, 20'資料流晶片 30, 30'記憶體 40位址匯流排 50仲裁匯流排 60, 60'資料匯流排 21，2Γ鎖存器 22,22' ECC檢查/更正邏輯 發明詳細說明 本發明係關於多處理器系統之改良 24, 第二鎖存器： 26, 26'緩衝器 28, 28'控制邏輯 91, 91'; 92, 92'; 93, 93' 202 旁路裝置1 204 旁路裝置2 206 多工器 線 下列說明是用以使 (請先閲讀背面之注意事頊再填寫本頁) 經濟部中央標準局員工消費合作社印製 -6a - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） A7 Β7 五、發明説明（4 ) 得普通熟悉本技術領域者可製_造及使用本發明，且是以專 利申請之格式及其之需求來提供。熟悉本技術領域者應呀 輕易想出較佳實例之各種修改，且本文之通屬原理可應用 於其他實例。因此，並未意謂本發明之局限於所展示之實 例，而是應涵蓋符合本文所揭示之原理及特點的最廣範 圖1是服務多個處理器2之系統}之概圖的方塊圖，而系 統1例如可爲s Μ P系統。一共有n處理器，處理器i，2 _ 1，至處理器η，2-n。每一處理器是由一位址匯流排4〇 , 一仲裁匯流排50，.及一資料匯流排6〇來服務。在圖丨所描 述之系統1中，位址控制晶片1 〇控制位址。位址控制晶片 1 0與資料流晶片2 〇 —起控制對於記憶體3 〇之存取。 經濟部中央標準局員工消費合作衽印製 資料流晶片2 0使用匯流排6 〇來提供資料给處理器2 _丨至 2-η，且經由匯流排70接收來自記憶體3〇之資料。在任何 時間當該等處理器2之一，例如處理器！，24，試圖自記 憶體讀取資料時，記憶體控制器2 〇必須獲得對於資料匯流 排60進行存取之許可。當決定何時記憶體控制器2〇可對於 貧料匯流排6 0進行存取時，系統i必須將剩餘之處理器2對 於資料匯流排6 0之使用列入考慮。 在一資料請求之開端，通常無法決定何時資料匯流排6〇 可用以服務該請求。匯流排可因爲多種原因而變爲忙碌。 了 存在未決之項取请求。一般而言，位址匯流排4 〇及資 料匯流排6 0是獨立的。如此允許系統丨發出多重位址，而 播需等候一特定請求之資料返回。除此之外，該資料無需 7- 本紙張尺度適用中國國定炫進f CNS ) A4规抵i 710Y9Q7八权 B7 五、發明説明(5 ) ~~~~ 依照發出該等請求之相同順序來返回。因此，在任何時間 可能存在極多未決之讀取請求。該處理器2之—也可發出 寫入請求並置放寫入資料於一匯流排。 圖2是一傳統之資料流晶片20，位址控制晶片1〇，及記 憶體3 0之更詳細方塊圖。當該等處理器2之一發出—特定 碩取請求時，並不知道何時資料匯流排6 〇可用以轉移自記 憶體3 0讀取之資料。因爲.不知道何時資料匯流排6〇可供使 用，資料一般暫時儲存於緩衝器2 6。 —般而T自1己憶體3 0讀取之資料經由匯流排7 〇轉移至資 料流晶片20之鎖存器21。接-著ECC檢查/更正邏輯22檢 查資料是否有錯誤。ECC檢查/更正邏輯22接著轉移資料 主第二鎖存器2 4。在下一時脈循環中，資料轉移至緩衝器 2 6。緩衝器2 6儲存資料，直到控制邏輯2 8決定資料匯流 排6 0可用以轉移資料至該等處理器2之一適當處理器爲 止。 ' 一般而言，位址控制晶片1 〇通知控制邏輯2 8何時資料匯 流排0 0可接收來自資料流晶片2 〇之資料。在一傳統系統 中，位址控制晶片1 〇主要是藉由三指令來控制資料流晶片 經濟部中央標準局員工消費合作社印製 20 : MEM — CMD，SYS一CMD，與SYS — GRANT指令。 經由線9 1來提供之Μ E Μ — C M D通知資料流晶片2 0資料 將經由匯流排7 0自記憶體3 0抵達。經由線9 2來提供之 S Y S _ C M D通知資料流晶片2 0其必須提供資料至資料匯流 排6.0。經油線9 3來提供之S Y S._ GRANT指令通知資料流晶 片2 0已取得資料匯流排6 0且指定應提供至資料匯流排6 0 -8- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 -—, 五、發明説明（6 ) : : --- 之資料的數量。在值社s； 士 . 仕得統系統中’位址控制晶片1 〇爲資料匯 .排6 0進仃仲裁。—旦可對於資料匯流排6 〇進行存取，位 址t制晶片1 〇發出—s Y S - GRANT。S Y s _ GRANT指令通 丟k料"丨u日日片2 o貧料匯流排6 〇可用以接收資料。 t意雖然一多處理器系統可未具有緩衝器，但是此並 非系〜、在典型I無緩衝型系統中，一記憶體控制器可 根據，於讀取資料之接收的預期來請求匯流排。但是.，在 整個項取運作期間，匯流排皆將預留給該轉移。同樣地， 如果自元fe體（轉移之等待時間爲已知，則資料匯流排 可分到成爲許多時窗。如果二讀取受到請求，則在_預先 決疋I數目之循環以後匯流排必須供該請求使用。如此會 限制系4之H因此’無緩衝型建構通常不適用於多處 理斋系統。 經濟部中央標準局員工消費合作社印製 雖然圖1所展示之系統丨允許處理器2相當快速及具有足 ‘夠彈性地存取記憶體30 ,但是普通熟悉本技術領域者應可 理解由於緩衝器2 6必須付出代價。該等處理器2之—所接 收之第一資料受到等待時間，因爲來自記憶體3〇之資料必 須首先進入資料流晶片2 〇並且载入緩衝器2 6。此資料維持 在緩衝器2 6 ,直到位址控制晶片} 〇可爲匯流排i 〇進行仲 裁爲止。無論資料匯流排60是否立刻可供使用，資料會儲 存於缓衝器2 6許多循環。此可對於自記憶體3 〇至該等處理 器2之一處理器之資料之第一部份的傳輸造成等待時間。 本發明提供一種方法及系統，且該種方法及系統是用以 提供r*第一資料存取具有低等待時間的彈性多處理器系 -9- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公U '~~~~ A 7 二—〜---—_____ B7 五、發明説明（7 )—~~ " -：-- 统。本發明踩技, 月兩猎由—記憶體控制器來加以説明，且該記 體控制器白本 # 心 一 刊命匕。一資料流晶片及一位址晶片。但是，普通熟 悉本技術領域者應可輕易認知此種方法及系统可高效率地 運作於其他型式之記憶體控制器。 ，馬更明確展示根據本發明之方法及系統，現在請參看圖 6而圖·3指）續此種系統之一實例2 〇 〇的方塊圖。本發明之 貫例200包含一些類似於傳統系統之元件。因此該等元件 之編號類似於圖2所展示之該等傳統元件。 現在請夺看圖3，來自記憶體3 〇 ’之資料是由資料流晶片 Μ'接收。在—較佳實例中，〜位址控制晶片1〇,控制資料流 晶片2〇’。在—實例中，資料提供至鎖存器21.及ECC檢查 /更正邏輯22,。系統200接收決定是否資料匯流排6〇,可 用以接收資料。在—較佳實例中，這是藉由控制邏輯28，決 定是否經由線9 3 ’收到一 s Y S _GRANT指令來達成。 旁路装置1，202，提供資料自ECC檢查/更正邏輯222, 直接至多工器2 1。如果發現資料匯流排6 〇，可供使用，則 自旁路裝置1，202，輸入至多工器206之資料提供至資科 匯流排6 0 。如果資料匯流排6 〇 ’不是立刻可供使用，則資 經濟部中央標準局員工消費合作社印製 料提供至鎖存器2 4，。系統200接著決定是否資料匯流排 6 0 ' 彳寸可以接收資料。在一較佳實例中，控制邏輯2 8，再 一次決定是否經由線9 3，收到S Y S — GRANT指令i 來自旁路裝置2 ’ 204之資料提供至多工器206。如果資 料匯流排60’變爲可供使用，則自旁路裝置2,2〇4,輸入 至多工器2 0 6之資料提供至資料匯流排6 〇 I。在一較佳實例 -10- 本紙張尺度適用中國國家標準（CNS ) M規格（210X297公釐） ΑΊ -------- Β7 五、發明説明（8 ) 中’此發生於資料已輸入至資料流晶片2〇,以後之一循環。 如果資料匯流排6 0，不可供使用，則資料提供至緩衝器 2 6 ’。當資料匯流排6 0，變爲可供使用時，自缓衝器2 6 ’提供 至多工器206之資料轉移至資料匯流排6 〇 •。在一較佳實例 中’此發生於貧料成晶片2 〇 _已收到資料以後之二或更多循 立衣0 系統200免除藉由圖2所示之傳統緩衝型系統來提供给相 關處理器之第一資料轉移所導致的不必要代價。因爲旁路 裝置1，202，該等處理器2之一處理器可極快速收回第— 貝'料’如同其處於一無緩衝型系統。系統2〇〇也適用於匯 流排未立刻指配給特定讀取運作之情形。 如果資料匯流排6 0 '未立刻指配給讀取運作，則系統2〇〇 向d移動資料一循環，並重新檢查以決定是否資料匯流排 601可供使用。如果資料匯流排6〇,可供使用，則資料轉移 至貧料匯流排6 0 ’。如果資料匯流排6 〇，不可供使用，則系 統200可保存資料於緩衝器2 6 ’，直到資料匯流排6 〇，準備 好爲止。因此，資料可儘早傳送至該等處理器2之—適當 處理器。 ^ 經濟部中央標準局員工消費合作社印製 R 于' 此之外，系統2 0 0具有大於典型無緩衝型系統之彈性。 資料匯流排6 0 1無需在資料可自記憶體3 0 ’轉移至資料匯流 排60'以前很久即受到仲裁。在一較佳實例中，，當系統2卯 藉由位址控制晶片1 〇 '來爲資料匯流排6 進行仲裁時，在 一些循環之後在該運作所需之時間以内該匯流排皆指配给 該運作。因此，系統200當使用匯流排6 0 ’時未分割成爲_ ___ -11 - 本紙張尺度適财關家辟（CNS ) A视格y2H)X297公楚) ~~--~~~-~~ A7 _ B7 五、發明説明（9 ) 些預先決定之長度之時窗。 本文揭示一種用以提供資料給多個處理器之方法及系 統，且該種方法及系統提供低等待時間之第一資料存取及 高度彈性。 雖然一直根據所展示之實例來説明本發明，普通熟悉本 技術領域者應可輕易認知該等實例存在許多變型，且該等 變型可屬於本發明之精神及範疇。因此，普通熟悉本技術 领域者在不脱離附加之申請專利範園之精神及範疇之下可 進行許多修改。 經濟部中央標準局員工消費合作社印製 準 標 家 國 一國 I中 用 適 尺 張 紙 I本V. Description of the invention (3a A7 B7 10, 10 'address control chip 20, 20' data stream chip 30, 30 'memory 40 address bus 50 arbitration bus 60, 60' data bus 21, 2Γ latch 22, 22 'ECC check / correction logic invention Detailed description The present invention relates to the improvement of a multiprocessor system 24, the second latch: 26, 26' buffer 28, 28 'control logic 91, 91'; 92, 92 '; 93, 93' 202 Bypass device 1 204 Bypass device 2 206 Multiplexer line The following instructions are for use (please read the precautions on the reverse side before filling out this page) Staff Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Printing-6a-This paper size applies to Chinese National Standard (CNS) A4 specification (210X 297 mm) A7 B7 V. Description of the invention (4) Those skilled in the art can make and use the present invention, and it is It is provided in the form of a patent application and its requirements. Those familiar with the technical field should easily come up with various modifications of the preferred examples, and the general principles of this article can be applied to other examples. Therefore, it does not mean that the present invention Limited to the examples shown, but should cover The broadest principle and characteristics Figure 1 is a block diagram of an overview of a system that serves multiple processors 2. System 1 can be, for example, a sMP system. There are n processors in total, processors i, 2 _ 1 To processors η, 2-n. Each processor is served by an address bus 40, an arbitration bus 50, and a data bus 60. In the system 1 described in Figure 丨The address control chip 10 controls the address. The address control chip 10 and the data stream chip 2 — together control the access to the memory 3 0. The consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs prints the data stream chip 2 0 uses the bus 6 to provide data to the processors 2 _ 丨 to 2-η, and receives data from the memory 3 0 via the bus 70. At any time, one of these processors 2 such as a processor! 24. When trying to read data from the memory, the memory controller 20 must obtain permission to access the data bus 60. When deciding when the memory controller 20 can store the lean material bus 60 When taking time, system i must use the remaining processor 2 for data bus 60. Take into account. At the beginning of a data request, it is usually not possible to decide when a data bus 60 can be used to service the request. The bus can become busy for a variety of reasons. There are outstanding item fetch requests. In general, bits The address bus 40 and the data bus 60 are independent. This allows the system to issue multiple addresses, and the broadcast needs to wait for the return of a specific requested data. In addition, the data does not need to be 7- This paper standard applies to China Guoding Hyunjin f CNS) A4 regulations i 710Y9Q7 eight rights B7 V. Description of the invention (5) ~~~~ Return in the same order as these requests. Therefore, there may be very many pending read requests at any time. The processor 2 can also issue a write request and place the write data on a bus. Fig. 2 is a more detailed block diagram of a conventional data stream chip 20, an address control chip 10, and a memory 30. When one of these processors 2 issues a specific master request, it is not known when the data bus 600 can be used to transfer data read from the memory 30. Because it is not known when the data bus 60 is available, the data is generally temporarily stored in the buffer 26. -In general, the data read by T from 1 memory 30 is transferred to the latch 21 of the data stream chip 20 via the bus 70. Then-ECC check / correction logic 22 checks the data for errors. The ECC check / correction logic 22 then transfers the data to the main second latch 24. In the next clock cycle, data is transferred to the buffer 26. The buffer 26 stores the data until the control logic 28 decides that the data bus 60 can be used to transfer the data to an appropriate processor of these processors 2. 'Generally speaking, the address control chip 10 notifies the control logic 28 when the data bus 0 0 can receive data from the data stream chip 2 0. In a traditional system, the address control chip 10 is mainly controlled by three instructions. The chip is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 20: MEM — CMD, SYS — CMD, and SYS — GRANT instructions. M E M — C M D provided via line 91 notifies the data stream chip 20 that the data will arrive via the bus 70 from the memory 30. The S Y S _ C M D provided via line 9 2 informs the data stream chip 20 that it must provide data to the data bus 6.0. The SY S._ GRANT instruction provided via the oil line 9 3 notifies the data stream chip 2 0 that the data bus 60 has been obtained and specifies that it should be provided to the data bus 6 0 -8- This paper size applies to the Chinese National Standard (CNS) A4 specifications (210X297 mm) A7 B7 ---, V. Description of the invention (6):: --- The amount of data. In the value agency, the official control system's address control chip 10 is the data sink. Arrange 60 for arbitration. -Once the data bus 60 can be accessed, the chip made at address t10 issues -s Y S-GRANT. The S Y s _ GRANT instruction can be used to discard k materials " 丨 u daily film 2 o lean material bus 6 〇 can be used to receive data. It means that although a multi-processor system may not have a buffer, this is not a matter. In a typical I unbuffered system, a memory controller may request a bus based on the expectation of receipt of read data. However, the buses will be reserved for this transfer throughout the operation of the project. Similarly, if the auto-fe (the waiting time for the transfer is known, the data bus can be divided into many time windows. If the second read is requested, the bus must be determined after the number of cycles in advance. For this request. This will limit the H of Series 4 and therefore 'unbuffered construction' is generally not suitable for multi-processing systems. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs although the system shown in Figure 1 allows the processor 2 to be equivalent The memory 30 is fast and flexible enough to access the memory 30, but those skilled in the art will understand that the buffer 26 must pay a price. The processors 2—the first data received are subject to waiting time, Because the data from the memory 30 must first enter the data stream chip 20 and load it into the buffer 26. This data remains in the buffer 26 until the address control chip} 〇 can be arbitrated for the bus i 〇. Regardless of whether the data bus 60 is immediately available, the data will be stored in the buffer 26 for many cycles. This can be used to process data from the memory 30 to one of the processors 2 The transmission of the first part causes waiting time. The present invention provides a method and system, and the method and system are used to provide r * first data access to a flexible multiprocessor system with low waiting time. Paper size applies to China National Standard (CNS) A4 specifications (210X297 male U '~~~~ A 7 II — ~ --- — _____ B7 V. Description of the invention (7) — ~~ "-:- The invention of stepping technique is explained by a memory controller, and the memory controller Baiben # heart is published. A data stream chip and an address chip. However, those who are familiar with the technical field generally It should be easy to recognize that this method and system can operate efficiently with other types of memory controllers. Ma has clearly shown the method and system according to the present invention, please refer to Fig. 6 and Fig. 3. Refer to this) A block diagram of an example of the system 2000. The present invention 200 includes some elements similar to conventional systems. Therefore, the numbering of these elements is similar to the conventional elements shown in FIG. 2. Now please see FIG. 3. , The data from the memory 3 0 ' The stream chip M 'receives. In the preferred example, ~ the address control chip 10 and the data stream chip 20' are controlled. In the example, the data is provided to the latch 21. and the ECC check / correction logic 22 The system 200 receives and decides whether the data bus 60 can be used to receive the data. In a preferred example, this is achieved by the control logic 28 by deciding whether to receive a s YS_GRANT instruction via the line 9 3 ′. Bypass device 1, 202, providing data from ECC check / correction logic 222, directly to multiplexer 2. 1. If data bus 6 is found to be available, then from bypass device 1, 202, input to multiplexer 206 The information is provided to the asset bus 60. If the data bus 60 ′ is not immediately available, the printed materials of the consumer cooperative of the staff of the Central Standards Bureau of the Ministry of Economic Affairs will be provided to the latch 24. The system 200 then decides whether the data bus 60 'can receive data. In a preferred example, the control logic 28 decides once again whether to receive the S Y GRANT instruction i via the line 9 3 to provide the data from the bypass device 2 '204 to the multiplexer 206. If the data bus 60 'becomes available, the data input from the bypass device 2, 204, to the multiplexer 206 is provided to the data bus 60. In a better example-10- This paper size applies the Chinese National Standard (CNS) M specification (210X297 mm) ΑΊ -------- B7 5. In the description of the invention (8) 'This happened when the data has been entered To the data stream chip 20, the next cycle. If the data bus 60 is unavailable, the data is provided to the buffer 2 6 ′. When the data bus 60 becomes available, the data provided from the buffer 2 6 ′ to the multiplexer 206 is transferred to the data bus 6 〇 •. In a preferred example, 'this occurs when the raw material is turned into a wafer 2 0_two or more after the data has been received. The system 200 is exempted from being provided to the relevant processing by the traditional buffering system shown in FIG. 2 Unnecessary cost caused by the first data transfer of the device. Because of the bypass device 1, 202, one of the processors 2 can very quickly retrieve the first material as if it were in an unbuffered system. System 200 is also applicable when the bus is not immediately assigned to a specific read operation. If the data bus 60 'is not immediately assigned to the read operation, the system 200 moves the data to d for a cycle and re-checks to determine whether the data bus 601 is available for use. If the data bus 60 is available, the data is transferred to the lean bus 60 '. If the data bus 60 is not available, the system 200 can store the data in the buffer 26 'until the data bus 60 is ready. Therefore, the data can be transferred to these processors 2 as soon as possible-the appropriate processor. ^ Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Besides, the system 2000 has greater flexibility than a typical unbuffered system. The data bus 6 0 1 does not need to be arbitrated long before data can be transferred from the memory 3 0 ′ to the data bus 60 '. In a preferred example, when the system 2 卯 uses the address control chip 10 ′ to arbitrate the data bus 6, the bus is assigned to the bus within a period of time required for the operation after some cycles. Operation. Therefore, the system 200 is not divided into _ ___ -11 when using the bus 60 0 '-this paper size is suitable for financial affairs (CNS) A as a grid y2H) X297 male Chu) ~~-~~~~~~ A7 _ B7 V. Description of the invention (9) Some predetermined time windows. This article discloses a method and system for providing data to multiple processors, and the method and system provide first data access with low latency and high flexibility. Although the present invention has been explained based on the examples shown, those skilled in the art should readily recognize that there are many variations of these examples, and that these variations may belong to the spirit and scope of the present invention. Therefore, those skilled in the art can make many modifications without departing from the spirit and scope of the attached patent application park. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs
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