TWI311353B - Stacked chip package structure - Google Patents

Stacked chip package structure Download PDF

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Publication number
TWI311353B
TWI311353B TW092109019A TW92109019A TWI311353B TW I311353 B TWI311353 B TW I311353B TW 092109019 A TW092109019 A TW 092109019A TW 92109019 A TW92109019 A TW 92109019A TW I311353 B TWI311353 B TW I311353B
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TW
Taiwan
Prior art keywords
contacts
wafer
chip package
substrate
external
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TW092109019A
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English (en)
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TW200423322A (en
Inventor
Yu-Fang Tsai
Juang-Kun Kang
Tsung-Yueh Tsai
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Advanced Semiconductor Eng
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Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092109019A priority Critical patent/TWI311353B/zh
Priority to US10/711,575 priority patent/US7026709B2/en
Publication of TW200423322A publication Critical patent/TW200423322A/zh
Application granted granted Critical
Publication of TWI311353B publication Critical patent/TWI311353B/zh

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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1311353 -------_ 五、發明說明（1) 【發明所屬之技術領域】 本發.明是有關於— 一種堆疊式晶片封裝結構二封裝結構，且特別是有關於 【先前技術】 隨著積體電路（Int . 的高度發展，1C晶片之内部1JCU1 J，Ic)製程技術 )不斷地向上攀升，使得！的積 '度（integration 目因而大幅地增加，並將IC曰曰^内邛電路的電晶體數 逐漸地縮小。目前，隨荖射=^之内部電路的導線截面積 = 出新，例如球格陣列封襄(B⑷、多 ' 荨曰曰片封裝結構，其中，球格陣列封裝 裝則且具有有更高：數二及高可靠度的優勢，而多晶片模組封 =^更快、更短的傳輸路徑以及更佳的電氣特性，並 並、蟲2小晶片封裝結構的面積，因而使得該些技術已經 、曰遍應用於各種電子產品之中，並成為未來的主流產品。 ，參考第1圖，其繪示習知一種晶片封裝結構的示意 f。就4見之打線接合（Wire b〇nd i ng)之晶片封裝結構而 言，晶片封裝結構1〇〇主要係由一基板11()、一晶片12〇、 多個導線130 ' —封膠140以及多個銲球15〇所構成。其 中’基板110例如為一陶瓷基板、玻璃基板或塑膠基板， 基板1 1 0内部具有多層導線層（未繪示）以及多層絕緣層（未 繪示）交替堆疊’而相鄰二導線層之間係以一絕緣層相 隔，且導線層之間係以導電孔（c 〇 n d u c t i v e v i a )或鍵通孔 (Plating Through Hole，PTH)而彼此電性連接。此外，
I 10792twf.ptd 第6頁 1311353 五、發明說明（2) 基板110之頂面ll〇a以及底面110b分別具有一上接點112以 及一下接點11 4，而上接點11 2係藉由基板11 〇内部之導線 層而電性連接於下接點114。另外，晶片12〇配置於基板 110之頂面ll〇a ’晶片120具有一主動表面（actiVe surface)122，而主動表面122之周緣配置多個銲墊 (bonding pad) 124，一般為鋁墊，且導線丨3〇係以打線接 合的方式連接於晶片12〇之銲墊124以及基板11〇之上接點 11 2 ’其中導線1 3 0例如為一.金線。 承上所述，封膠140係包覆導線丨3〇、晶片12〇以及基 板1 1 〇之上接點1 1 2，用以保護晶片1 2 〇以及導線1 3 〇。銲球 150係配置於基板110之下接點114，且銲球15〇之材質例如 為錫鉛合金等焊接材料。其中，晶片封裝結構丨〇〇係以銲 球1 50作為連接外部電子裝置（例如印刷電路板或主機板） 之接點，且銲球150係以面陣列的型態分佈於基板11〇之底 面ll〇b，以使此晶片封裝結構100成為具有高腳數之格 陣列封裝結構。 請參考第2圖，其繪示習知一種多晶片封裝模組的示 圖。習知多晶片封裝技術係將數個晶片封裝單元 200(a)、（b)(僅繪示其二）配置在同一承載器 (ΓΓΓΓ)210上/其中晶片封裝單元20 0例如為一球格陣 ^封裝（BGA)型態，且依序組裝於承載器21〇上。因此_ =封裝單元200U)及⑻之間可藉由承載器21。之内部； :(未綠示)而彼此電性連接，以構成—多晶片模組之：： ~構，例如動態隨機記憶體（DRAM)模組。 裝
五、發明說明（3) 值得注意的是，當晶片封 地承載器所需的承載面積也必須：：之數目越多時’相對 成之後的多晶片封裝模組，、=寬，使得組裝完 之四方體結構，且其承載面積長條狀或扁平狀 了符合現今高腳數之晶片封裳結槿相對小。因此，為 構的潮流，如何利 2及夕晶片模組封裝結 Κι::”結構，將= =裝並集合更多 封裝-種堆疊式晶片 一晶IK::之上，以=::;:::於單 構，係利用球格陣列之銲球來接;堆疊式晶片封裝結 以達到高卿數之晶片封裝=相疊之晶片封襄單元， 封裝結構，片提出-種堆疊式晶片 片封裝翠元主要係由早，而成，每—晶 以及多個薛球所構成。其個導線、-封膠 上而上接點係分別電接r及多 置於基板上，而晶片具有多 j點。晶片係配 内接點係分別電性連接於外接點。此夕;及ί個外接點’且 上接點，且封膠L覆;;出 另外，銲球分別連接下接點，且電性連外接點。 、相豐之這也曰 封裝單7C之一的外接點。 俊照本發明的較佳訾： 片之中央表面區域上，1==於=之外接點位於晶 :外接點例如以面陣列的型態:a :=二：二蜮 ;域上且下接點亦呈面陣列議分佈於 列封：ϊί上：：：施例中，晶片封裝單元係呈-球格陣 外，晶片還具有璃或塑膠。此 面，且銲墊係藉A 重佈線層，位於晶片之表 接點之一。’、佈線層而分別連接内接點之一以及外 :發明因採用球格陣列封裝( 其具有鬲腳數之優點曰片封裴結構， 彼此電性連接，以縮短曰曰片封裝早元係以銲球而 小型：於結構上的改變，使得堆疊完成之後的 顯易士的:，、和優點能更明 細說明如下： 列並配合所附圖式，作詳 【實施方式】 片封的圖分ν本!： ^ 圖，堆疊式曰片忍圖以及組裝示意圖。請參考第3A 且式日日片封裳結構3〇〇主要係由多個晶片 1311353 五、發明說明（5) 302 '304、306堆疊而成’每一晶片封裝單元3〇2、304、 306主要係由一基板310、一晶片320、多個導線330、一封 膠340以及多個銲球350所構成。其中，基板31〇例如為一 陶瓷基板、玻璃基板或塑膠基板，基板31〇内部具有多層 導線層（未繪示）以及多層絕緣層（未繪示）交替堆疊，而相 鄰二導線層之間係以一絕緣層相隔，且導線層之間係以導 電孔或錄通孔而彼此電性連接。此外，每一基板3 1 〇 ( a )、 (b)或（c)之頂面31〇a以及底，面310b分別具有一上接點312 以及一下接點314，而上接點312係藉由基板31〇内部之導 線層而電性連接於下接點31 4。 晶片320配置於基板310之頂面31〇a，晶片32〇具有一 主動表面322，而主動表面322上配置多個内接點328a以及 多個外接點328b，其中内接點328a例如分佈於主動表面 322之周緣區域上，而外接點328b例如分佈於主動表面π? =中央區域上’且内接點328a之一與外接點32化之一例如 藉由晶片320之内部線路（未繪示）而彼此電性 :意的是’以打線接合之晶片封裝為例1方便打線作于 業，一般晶片320之銲墊324係配置於主動表面322之 緣。在本實施例中，銲墊324可藉由一重佈線層 ΰ (re-distribution layer)326 之繞線設計 日 324分Λ電/連接於内接— 二’且内接點328a與外接點328b可分別配置於重 326之周緣表面區域上以及中央 、、、 料以打線接合的方式連接Μ綱之内接^28a導以線及
1311353 五、發明說明（6) 基板310之上接點312，其中導線33 0例如為一金線，而内 接點3 2 8 a對應於上接點31 2，且内接點3 2 8 a與上接點3 1 2例 如呈線形型態或矩形型態分佈。然而本發明中的晶片電路 设计上’亦可以將銲墊直接設計成具有内接點族群及外接 點族群’直接透過導線3 3〇電性連接基板31()，而無須透過 重佈線層3 2 6。 此外’封膠340包覆導線330、晶片320以及基板31〇之 上接點312 ’用以保護晶片3,20以及導線330，且封膠340之 中央區域具有一開口 342，而開口 342對應暴露出晶片32〇 之外接點+328b。另外，銲球35〇例如配置於基板31〇之下接 點314，藉由銲球35〇對應連接於晶片32〇之外接點， 以使相疊之晶片封裝單元3 〇 2彼此電性連接。其中，銲球 列，如#為錫鉛合金等焊接材料，而外接點328b例如呈面 ^列分佈’且外接點328b對應於下接點314，以使下 點3 1 4亦呈面睁列型態分佈於基板31 〇之中央表面區域 # i 考第3β圖堆疊完成之後的晶片封裝結構300， 晶片封步~之*1片封裝單元3〇2上依序堆疊第2層〜第1^層之 Γ曰η二I疋3〇4、3〇6 ’ 可為2, 3, 4 ...等，其中第2層 單：之銲球350繼 之鲜球35G係a接點3m ’ 層之晶片封裝單元306 點328b，以此類推連接於第2層之晶片封裝單元謝之外接 於堆疊完成之德的曰以達到多晶片堆疊封裝的目的。由 灸的曰曰片封裝結構30 0不須藉由習知之承載
1311353__ 五、發明說明d · ' --------— 積之承載面’而是由第1層之晶片封裝單元… 直接k供承載之作用，因此相對於習知長條形或扁平形之 四方體結構，本發明之堆疊式晶片封裝結構3〇〇，其外觀 大致上為柱狀體，且其承載面積可大幅地縮小，以達到小 型化晶片封裝之目的。 此外，本發明之堆疊式晶片封裴結構3〇〇係以球格陣 列封裝（BGA)之結構作為每一晶片封裝單元、304、 306，其具有高腳數之優點，且相疊之晶片封裝單元3〇2、 3 0 4、3 0 6係直接以銲球3 5 0而彼此電性連接，以縮短晶片 封裝單元302、304、306之間電氣連接的長度，因此可降 低晶片320之間因訊號傳遞路徑太長而導致延遲的現象。 再者’最頂層之晶片封裝單元306還可配置一散熱塊350於 封膠340之開口342中，而散熱塊350可快速傳遞晶片320之 主動表面322的熱能’有助於提高此晶片封裝結構300的散 熱效果。然而最頂層的晶片封裝單元3〇6亦可以封膠340密 封開口 3 4 2，以保護未使用之外接點。 雖然本發明以一較佳實施例說明，但非限定利用相同 封裝尺寸之晶片封裝單元，亦可採用不同尺寸或不同型態 的晶片封裝單元，且個別晶片封裝單元亦可具有不同之功 能’例如利用本發明之堆疊結構，將多個動態隨機記憶體 (DRAM)模組配置於最底層之邏輯電路模組或中央處理器模 組之上，以達到多工運算或多功能之堆疊式晶片封裝結 構。 綜上所述，本發明之堆疊式晶片封裝結構具有下列優
10792twf.ptd 第12頁 1311353 五、發明說明（8) 1、本發明之他 *、 堆叠式晶片封裝結構’乃换田+ ^裝（B⑷之晶片封裝 ^球格陣列 疊之晶片封裴單亓後 巧门唧數之優點，且相 封裝單元之間電】：銲球：彼此電性連#，以縮短晶片 』电礼連接的長度，並符人客曰 门 潮流趨勢。 σ多日日片模組封裝的 良與突破，使^寻w疊式晶片封裝結構’由於結構上的改 雖然本發=完ί:.;?封裝面積能更小型化。 以限定本發明，：乂―較佳貝靶例揭露如i，然其並非用 神和範圍Θ，當可：：：此技藝者’在不脫離本發明之精 護範圍當視後附之Φ =更動與潤飾，11此本發明之保 附之申請專利範圍所界定者為準。 1311353 圖式簡單說明 第1圖繪示習知一種晶片封裝結構的示意圖。 第2圖繪示習知一種多晶片模組封裝結構的示意圖。 第3A〜3B圖繪示本發明一較佳實施例之一種堆疊式晶 片封裝結構的分解示意圖以及組裝示意圖。 【圖式標示說明】 1 0 0 :晶片封裝結構 I 1 0 :基板 ， 110a :頂面 110b :底面 II 2 :上接點 11 4 :下接點 1 2 0 .晶片 122 :主動表面 124 :銲墊 1 3 0 :導線 140 :封膠 1 5 0 :銲球 200 (a)、（b):晶片封裝單元 2 1 0 :承載器 3 0 0 :堆疊式晶片封裝結構 302、304、306 :晶片封裝單元 3 1 0 (a)、（ b)、（ c):基板 3 1.0 a :頂面
10792twf.ptd 第14頁 1311353 圖式簡單說明
310b :底面 312 上接點 314 下接點 320 晶片 322 主動表面 324 銲墊 326 重佈線層 328a :内接點 328b :外接點 330 導線 340 封膠 342 開口 350 銲球 352 散熱塊 10792twf.ptd 第15頁

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1311353 六、申請專利範圍 1. 一種堆疊式晶片封裝結構，至少包括： 複數個晶片封裝單元，適於彼此相互堆疊， 該些晶片封裝單元分別包括： 、 且右滿齡：基板，具有一頂面及對應之一底面，該基板還 ς 上接點配置於該頂面以及複數個下接點配置於 该底面，而該些上接點係分別電性連接於該些下接點； 晶片’配置於該基板之該頂面上 * — ’ - - _…—— 该晶片具有 w、查j内接點以及複數個外'接點，而該些内接點係分別電 性連接於該些外接點； 接點； 複數個導線’分別連接於該些上接點以及該些内 此 一封膠，包覆該些導線、該晶片以及該基板之該 二上接點，且該封膠具有一開口，對應暴露出該些外接 點；以及 — 複數個銲球，分別連接該些下接點以及對應之另 以二日日片封裝單元之該些外接點，以使相疊之該些晶片 封裝單元彼此電性連接。 2. 如申請專利範圍第1項所述之堆疊式晶片封裝結 構，其中該些外接點位於該晶片之中央表面區域上，而該 二内接點位於該晶片之周緣表面區域上。 3. 如申請專利範圍第2項所述之堆疊式晶片封裝結 構’其中該些外接點係呈面陣列的型態分佈。 4. 如申請專利範圍第3項所述之堆疊式晶片封裝結 構’其中該些外接點對應於該些下接點，且該些下接點係
J311353 ______ ;、申請專利 ί® · ----~ 呈面陣列的型態分佈於該底面之中央表面 5.如申請專利範圍第J項所述之堆。 該晶片之 …上汗I 該些内接點以及該些外接點。 6. 如申請專利範圍第丨項所述之堆疊 構，其中該晶片還具有複數個銲墊，其曰曰、波結 成該些内接點，其他該些銲，塾構成該些外接鐸塾構 7. 如申請專利範圍第丨項所述之堆’ 其中該此晶片刼姑_ a σ ^ 式阳片封裝結 --係呈一球格陣列封裝型態 才丨J靶圍第：t音所诚夕论蟲二、α U 構，其中該晶片還具有複數個銲墊以及—曰曰、于裝結 『曰片之表面’且該些銲墊係藉 ：：層’位於 …點以及該些外接點。 师、，泉層而分別連接 構 …如申列封裝型態。 、其中該基板之材質係為陶£、玻璃以及塑膠其裝中： 構 上 9更ΐ ί請專利範圍第1項所述之堆疊式晶片封穿社 ^括-散熱塊，配置於最頂層之該些晶片封裝裝。 是蓋於最頂層之該封膠的該開口中。 疋 —’—種晶片封坡堆疊結構，至少包括： 基板：工：晶片封裝單元’具有-基板及-第-晶片，兮 置於該頂：：二ϊ應之一底面，並具有複數個上接點配 與該些下: 下接點配置於該底面，該些上接點 ~接點y刀別電性連接，該第一晶片配置於該n s # …亥些上接點電性連# ; 忑頂面並 該第二晶片封裝單元，具有一承載器及—第二晶片， 一曰曰片配置於該承載器上，其中該第二晶片具有複數
1〇792twf.ptd 第17頁 六、申請專利範園 個内接點以及複數個外接點，該些内接點分別與該承 電性連接；以及 Μ盗 複數個銲球，分別連接該些下接點以及該些外接點， 以使相璺之該第一晶片封裝單元及該第二晶片封裝 此電性連接。 攸 11.如申請專利範圍第】〇項所述之晶片封裝堆疊結 構，其中該些外接點位於該第二晶；ί之中央表面區域上， 而該些内接點位於該第二晶，片之周緣表面區域上。 1 2.如申清專利範圍第11項所述之晶片封裝堆疊結 構’其中該些外接點係呈面陣列的型態分佈。 1 3.如申請專利範圍第丨2項所述之晶片封裝堆疊結 構，其中該些外接點對應於該些下接點，且該些下& σ 呈面陣列的型態分佈於該底面之中央表面區域上。 ’、 1 4 一種晶片封裝單元，至少包括： 上接：ίΪ於頂面及對應之一底面，並具有複數個 上接點配置於邊頂面以及複數個下接點配置於該底面，而 該些上接點係分別電性連接於該些下接點； 一晶片，配置於該基板之該頂面 内接點以及複數個外接點； ’該晶片具有複數個 複數個導線， 點，以及 分別連接於該些上接點以及該些内接 3 44 :覆5亥些導線、該晶片以及該基板之該些上 Λ具有一開口，對應暴露出該些外接點。 15·如中晴專利範圍第14項所迷之晶片封裂單元，其 J311353 ________ 六、申請專利範圍 中更包括複數個銲球，分別配置於該些下接點。 16.如申請專利範圍第14項所述之晶片封裝單元，其 中該晶片還具有複數個銲墊以及〆重佈線層位於該曰日片 之表面，且該些銲墊係藉由該重佈線層而/刀別連接該些内 接點以及該些外接點。 α 1 7.如申請專利範圍第丨4項所述之晶片封裝單元’其 中該晶片還具有複數個銲墊，其中部分該些銲墊構成該些 内接點，其他該些銲墊構成，該些外换點。 时 1 8·如申請專利範圍第丨4項所述之晶片封裝單元，其 中該基板之材質係為陶竟、玻璃以及塑膠其中之
10792twf.ptd 第19貢
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