TW587317B - Construction and manufacturing of a chip package - Google Patents

Abstract

Construction and manufacturing of a chip package which is composed of a glass substrate, at least one chip, an adhesive layer, a stiff layer and an interconnection layer. The glass substrate with a first surface on which the chip is located is opposite to an active surface of the chip. In addition, the adhesive layer covers the first surface and the chip fully. The stiff layer is located on the adhesive layer, moreover, first conductive vias pass through the glass substrate to be electrically coupled to the chip pad of the chip. The interconnection layer with several bonding pads which are located on the second surface of the glass substrate and electrically coupled to those first conductive vias.

Description

587317

The invention belongs to a technology leader. The present invention relates to a chip packaging structure and a manufacturing process thereof, and particularly to a chip packaging structure and a process using a glass substrate as a dielectric layer. Previously, Flip Chip Interconnect Technology (FC) was a method of using an area array to 'position multiple die pads on the active surface of a die. And bumps are formed on the wafer pad, and after the wafer is overturned (nip), these bumps are used to electrically and mechanically connect the wafer pad of the wafer to the contacts on the carrier ( contact), so that the chip can be electrically connected to the carrier through the bump, and electrically connected to the external electronic device through the internal circuit of the carrier. It is worth noting that, because the flip-chip bonding technology (FC) is applicable to chip packages with high pin counts, it has many advantages such as reducing chip package area and shortening signal transmission paths. Bonding technology has been widely used in the field of chip packaging. Common chip packaging structures that use flip-chip bonding technology include Flip Chip Ball Grid Array (FC / BGA) and FHp. Chip Pin Grid

Affay ’FX / PGA) and other types of chip packaging structure. Refer to FIG. 1, which is a schematic cross-sectional view of a conventional flip chip lattice array type chip package structure. The chip package structure 100 includes a substrate 11, a plurality of bumps 120, a wafer 13, and a plurality of solder balls.

587317 V. Description of the invention (2) 140. The substrate 110 has a top surface 112 and a corresponding bottom surface 114, and the substrate 110 further includes a plurality of bump pads 116a and a plurality of bal 1 pads 11 6b. In addition, the chip 130 has an active surface 132 and a corresponding back surface 134. The active surface 132 of the chip 130 refers to the side of the chip 130 with an active device (not shown), and The wafer 130 further has a plurality of wafer pads 136, which are arranged on the active surface 132 of the wafer 130 and serve as a medium for the signal input and output of the wafer 130. The positions of the bump pads 116a correspond to the wafer pads, respectively. 36 position. In addition, the bumps 120 are electrically and mechanically connected to one of the wafer pads 36 to one of the corresponding bump pads 116a, respectively. In addition, these recording balls 14 are respectively arranged on the solder ball pads 11 6 b for electrically and mechanically connecting to external electronic devices.

Please refer to FIG. 1 as well. Underfill 150 can fill the space surrounded by the top surface 112 of the substrate 110 and the active surface 132 of the wafer 130 to protect the bump pad 116a, the wafer pad 136, and the bump. The exposed part of 120 and at the same time buffer the thermal strain mismatch between the substrate 11 and the wafer 13 when heated. Therefore, the wafer pad 136 of the wafer 130 will be electrically and mechanically connected to the bump pad 116a of the substrate 110 through the bump 120, and then routed down to the inner wiring 118 of the substrate 110 to The solder ball pad 116b on the bottom surface 114 of the substrate 110 is finally electrically and mechanically connected to the external electronic device through the solder ball 14o on the solder ball pad 116b. It is worth noting that the material of the conventional wafer 130 is different from that of the substrate 110, so its thermal expansion coefficient (coefficient)

587317 V. Description of the invention (3) of Thermal Expansion (CTE) is also different, and the bump 120 is subject to repeated effects of thermal strain between the wafer 130 and the substrate 110 for a long time. The bump 120 itself is extremely easy Fatigue occurs and lateral fracture occurs. In addition, the conventional chip packaging process is to complete the internal circuit 118 of the substrate 110, the bump pad 116a, and the solder ball pad 116b, and then assemble the wafer 130 on the surface of the substrate 110. Since the wafer 130 is exposed on the surface of the substrate 110, the wafer 130 is easily damaged by external forces, and the wafer 130 is easily affected by external humidity and dust pollution. Furthermore, common materials currently used as substrates for flip-chip ball grid array (FC / BGA) or flip-chip pin grid array (FC / PGA) include ceramics and organic materiai. Among them, Organic substrates using organic materials as materials are the most common. Due to the limitation of the organic substrate in the process yield, the wire width and the pitch of the wires of the organic substrate, which can be mass-produced at present, can only reach 25 microns. It is worth noting that, as the density of the wafer pads of the wafers gradually increases, and the contact density of existing organic substrates cannot be relatively increased upwards, how to use substrates with higher density contacts and fine lines to Replacing the existing organic substrates is a major issue urgently to be solved in the field of chip packaging. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to propose a chip packaging structure and a manufacturing process thereof, which mainly uses a glass substrate instead of a conventional organic substrate, and can provide a high-density contact and a fine circuit for packaging with high density. Wafer wafers and improve the performance of chip packaging. between

587317 Description of the invention (4) Another object of the present invention is to propose a chip packaging structure and its process, "the surface of the glass substrate and the wafer has an adhesive layer and a support layer" to prevent the surface of the wafer from being damaged by external forces. , So that the chip is best protected. In order to achieve the above object of the present invention, the present invention proposes a chip packaging process including the following steps: (a) providing a glass substrate, wherein the glass substrate has a first surface and a corresponding second surface; (b) providing a plurality of Wafer 'wherein the wafer has an active surface and a corresponding back surface, and the wafer further has a plurality of wafer pads, and the wafer pads are respectively disposed on the active surface of one of these wafers and pass through the active surface of the wafer. These wafers are arranged on the first surface of the glass substrate; (c) a glue layer is comprehensively formed on the first surface of the glass substrate, and the glue layer covers the back of the wafer; (d) a support layer is arranged on the glue (E) forming a plurality of first conductive plugs on a glass substrate, wherein the first conductive plugs are respectively connected to a wafer pad of a wafer; (f) forming an interconnecting layer on a glass-based 77 board A second surface, wherein the interconnect layer further has a plurality of bonding pads, which are located on a side of the interconnect layer that is away from the second surface, and the internal wiring of the interconnect layer is electrically connected to the conductive plugs; And (g) singulate these sealed wafers. In order to achieve the above object of the present invention, the present invention provides a chip packaging structure, which includes a glass substrate, at least one wafer, an adhesive material layer, a building, and an interconnect layer. Among them, the glass substrate has a first surface and a second surface, and the wafer has an active surface and a corresponding back surface, and the wafer further has a plurality of wafer pads, which are respectively arranged on the active surface of the wafer.

587317

5. Description of the invention (5), and the wafer is arranged on the first surface of the glass substrate with an active surface. In addition, the adhesive layer covers the first surface of the glass substrate and covers the back of the wafer. The supporting layer is disposed on the adhesive material layer, and the first conductive plug ^ penetrates the glass substrate and is electrically connected to the wafer 塾 of the wafer. In addition = the interconnect layer is disposed on the second surface of the glass substrate and has a plurality of access pads, which are located on the side of the interconnect layer that is away from the second surface of the substrate, and the internal wiring of the interconnect layer is electrically To the first conductive plugs. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: ^ Embodiments

Figures 2A to 2F sequentially show a cross-sectional flowchart of a chip packaging process according to a preferred embodiment of the present invention. Please refer to FIG. 2A first, a glass substrate 210 is provided, a certain surface has a first surface 212 and a corresponding second surface 214, and then a plurality of wafers 220 are provided, and each wafer 220 has an active surface 222 and a corresponding surface. A back surface 224, and each wafer 220 also has a plurality of wafer pads 226, which are arranged on the active surface 222 of the wafer 220, and the wafer 220 is bonded to the active surface 222 of the wafer 220 by means of flip-chip (FC) bonding It is attached to the first surface 212 of the glass substrate 210. Wherein, the wafer 220 and the glass substrate 21 0 are bonded by, for example, an adhesive layer 2 3 0 a, and the adhesive layer 230 a can be formed on the glass substrate 21 0 by a thin film, and then the wafer 220 is passed through the adhesive layer 230 a. It is attached to the glass substrate 210. It ’s worth noting that because the materials of the glass substrate 21 and the wafer 220 are silicides, the thermal expansion coefficients of the two are similar, so that the glass substrate 21 and the crystal

587317

The thermal strain of the plates 2 2 0 can be matched with each other. ^, " 〇 ^ Λ ^ 22βΓ2, "::: ί 2: Γ Γ 230 & ^ 220, Α exhibition: J material layer 230 completely covers the thickness of wafer 220 S can be greater than or equal to the thickness of wafer 22G, so glue The material sound can form a protective film on the surface of the wafer 220, so that the second wafer and the second wafer: i = force /; the surface 212 will not be exposed, so the wafer 220 is damaged by external force. In addition, the material of the absurd material layer 230 is, for example, an organic material such as a ring louse, epoxy resin, and the like: and the supporting platform, and the material on the supporting side may be strong = also used to improve the chip packaging structure. Hardness, and the support layer 240 can also be a high heat-dissipating heat conductive plate, which includes a material such as metal or graphite, which is used to quickly conduct the heat generated by the stomach 220's stomach to the surface of the chip packaging structure, thereby The heat dissipation performance of the chip package structure is improved. Then, referring to FIG. 2C, the glass substrate 210 is thinned from the second surface 214 of the glass substrate 210. Since the above-mentioned optional layer 24 () has sufficient strength and hardness, the branch floor 240 can be used as a supporting structure for the bottom sheet 22 and the bottom of the glass substrate 210. Therefore, when the glass substrate 21 is thinned from the second surface 214 of the glass substrate 21o, the wafer 220 and the adhesive material layer 230 are less likely to be damaged or broken by the force of the polishing machine. Next, referring to FIG. 2D, a plurality of first conductive plugs 21a are formed on the glass substrate 210. For example, a method such as laser ablation, etching perforation, or ultrasonic hole formation on the glass substrate 21Q is performed first. So that a plurality of openings 21a are formed on the second surface 214 of the glass substrate 210, and then a conductive material is filled in each opening 21aa separately to form as many as described above.

587317 V. Description of the invention (7) First conductive plugs 2 5 0. The position of the opening 21 〇a also corresponds to the position of the wafer 2 2 0, the position of the sheet 226, and the opening 2 ioa penetrates the glass substrate 210 to expose each wafer pad 226, so the conductive plug 250 can communicate with the wafer. The pads 226 are electrically connected, and each wafer pad 226 of the chip 220 has a first conductive plug 250. In addition, at the same time that the conductive layer 252 is subsequently formed on the glass substrate, a conductive material 250b may be filled into each of the openings 21a to form these first conductive plugs 25 (), so that the first conductive plug The plug 25 can be formed integrally with the patterned wire layer 252. Then, as shown in FIG. 2D, a patterned interconnect layer 260 is formed on the second surface 214 of the glass substrate 21, and the interconnect layer is electrically connected to the first conductive plug 250. In addition, the interconnect layer 26 may be a single-layer wire layer structure or a multilayer wire layer structure. The interconnect layer 260 of the single-layer wire layer structure refers to a patterned pattern formed on the second surface 214 of the glass substrate 21 A wire layer 252, and the material of the wire layer 252 may be copper, aluminum, and alloys thereof, and the wire layer 252 has a plurality of bonding pads 252a and lines 252b, and the bonding pads 252a are electrically connected to the bonding layer 252a through the lines 252b. The first conductive plug 250 can finally form a solder resist layer 258 on the wire layer holder 2 and expose the bonding pad 252a, so as to form the inner wiring layer 260 of the single layer wire layer holder 2, as shown in FIG. 4 The interconnect layer 26 shown, which includes only a single wire layer. ≪ As shown in FIG. 2E, the inner wire layer of the multilayer wire layer structure refers to the second surface 214 of the glass substrate 210, formed Rounded wire layers 252, 256, and n-1 dielectric layer 254, where n can be a natural number queue 2,3,4 ... ## except 1), and two adjacent patterned wire layers 10035twf.ptd page 11 587317 5. Description of the invention (8) 252: 256 and a dielectric layer 254 are alternately superposed In addition, a plurality of second wire plugs 251 through 0 pass through the dielectric layer 2 54 in the manner of laser burning holes, etched holes or ultrasonic holes, and are electrically connected to adjacent two patterned wire layers. Between 252 and ^ wire layer 256. The material of the dielectric layer 254 may be silicon nitride or silicon dioxide, which has a thermal expansion coefficient similar to that of the wafer 22 and the glass substrate 21, so it can be similar to the wafer 2 2 〇 The thermal strains of the glass substrate 21 〇 match each other.: Please refer to Figure 2E again. The top layer of the inner conductor layer 26 0 far from the glass substrate 21 〇 also has a plurality of bonding pads 2 5 6a and wiring 256b, and the bonding pad 2 5 6a is electrically connected to the first and second conductive plugs 2 5 0, 251 through the line 256b. Finally, a solder resist layer 258 is formed on the topmost wire layer 256, and the bonding pad 2 5 6a is exposed. . Among them, a plurality of contacts 270 ′ can also be arranged on the surface of the bonding pad 2 5 6a to connect external electronic devices, and The point 270 may be a solder ball or a pin, which is used to form a flip chip array (FC / BGA) or flip chip array (FC / PGA) chip package structure. As shown in FIG. 2F, the glass substrate 210 having a plurality of wafers 220 is singulated using a cutting machine to obtain a singulated wafer packaging structure 200. The number of wafers 220 is not limited to a single piece. Because of the wiring of the glass substrate The density is high, and the line width and line pitch (pi tch) of the lead layer can reach 1 · 5 microns', which is much smaller than the line width and line pitch of the lead layer of the organic substrate (about 25 microns). Therefore, multiple wafers 22 () can be arranged in a glass substrate 21, so they can be applied to wafer packages such as Multiple-Chip Modules (MCM) or systems in a single package (System In Package, SIP).

10035twf.ptd Page 12 587317 V. Description of the invention (9) Installation structure. FIG. 3 is a schematic cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention, in which the interconnect layer has a single wire layer. After the singulation, the chip packaging structure 202 mainly includes a glass substrate 210, at least one wafer 220, an adhesive material layer 230, a support layer 240, a plurality of first conductive plugs 250, and an interconnect layer 260. The glass substrate 210 has a first surface 212 and a corresponding second surface 214, and the wafer 220 has an active surface 222 and a corresponding back surface 224, and the wafer 220 further has a plurality of wafer pads 226, which are respectively disposed on The active surface 222 of the wafer 220 is arranged on the first surface 212 of the glass substrate 210 with the active surface 222, and the g glue layer 230 comprehensively covers the first surface 212 of the glass substrate 210 and covers the first surface 212 of the glass substrate 210. The back surface 224, the support layer 240 is disposed on the adhesive material layer 230, and the first conductive plug 250 penetrates the glass substrate 210, and is electrically connected to the wafer pad 226 of the wafer 220, respectively. The interconnect layer 260 is disposed on the second surface 214 of the glass substrate 210, and the interconnect layer 26 has a wire layer 252, which is electrically connected to the first conductive plugs 25, and the interconnect layer 26 There is a plurality of bonding pads on one side of the surface away from the glass substrate 210. . In addition, the anti-tin layer 258 is disposed on the wire layer 252 and the glass substrate 21 and exposes the bonding pads 252a, and the contacts 270 (such as solder balls or pins) are respectively disposed on each bonding pad 252a. · A schematic cross-sectional view of a chip package junction in which the interconnecting layer has a plurality of wire layers in a preferred embodiment of the present invention. After singulation, the chip package structure 2G4 mainly includes—a glass substrate 21 (), at least one clear sheet 220, an adhesive material layer 230, a support layer 240, and a plurality of first conductive plugs.

587317 V. Description of the invention (plug) 250 and an interconnecting layer 260. The glass substrate 210 has a first surface 212 and a corresponding second surface 214, and the wafer 220 has an active surface 222 and a corresponding back surface 224, and the wafer 220 further has a plurality of wafer pads 226, which are respectively disposed on The active surface 222 of the wafer 220 is arranged on the first surface 212 of the glass substrate 210 with the active surface 222, and the adhesive layer 230 comprehensively covers the first surface 212 of the glass substrate 21 and covers the back surface of the wafer 220. 224, the support layer 240 is disposed on the adhesive material layer 230, and the first conductive plug 250 is penetrated through the glass substrate 210, and is electrically connected to the wafer pad 226 of the wafer 220, respectively. The interconnect layer 260 is disposed on the second surface 214 of the glass substrate 2 10, and the interconnect layer 260 has a plurality of conductive layers 252, 256, at least one dielectric layer 254, and a plurality of second conductive plugs 251. The layers 252 and 256 are sequentially disposed on the second surface 212 of the glass substrate 21o, and the conductive wire layer 252 closest to the glass substrate 21o is electrically connected to the first conductive plug 250, and is farthest from the glass substrate 21o. The wire layer 256 forms a bonding pad 256a, and the dielectric layer 254 is arranged between two adjacent wire layers 252 and 256. The second wire plug 251 penetrates the dielectric layer 254 and electrically connects the adjacent wires. Layers 252, 256. In addition, the solder resist layer 258 is disposed on the wire layer 256 and the dielectric layer 254 farthest from the glass substrate 210, and the bonding pad 256a is exposed, and the contact 270 (solder ball or pin) is disposed on each bonding pad separately. 256a. To sum up, the chip packaging structure and the manufacturing process of the present invention have at least the following advantages: 1 · The chip packaging structure and the manufacturing process of the present invention, wherein the wafer packaging structure and the manufacturing process are covered in a plastic layer, so the wafer can be optimally protected. M7317 V. Description of the invention (11) The wafer is affected by moisture or dust. 2 · The chip packaging structure and manufacturing process of the present invention, wherein the back surface of the chip has a support layer such as reinforced glass or a thermally conductive plate, and the material thereof can be metal or graphite ', thereby improving the destructive resistance of the overall chip packaging structure. 3 · The chip packaging structure and manufacturing process of the present invention use glass substrates and circuit layers to provide high-density contacts and fine wire layers for packaging wafers with a high-density wafer pad to improve the performance of chip packaging. . 2. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the essence of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. μ

10035twf.ptd Page 15 587317 Brief Description of Drawings Figure 1 shows a cross-sectional schematic diagram of a conventional flip-chip ball grid array chip package structure; Figures 2 A to 2F sequentially show the preferred embodiment of the present invention A cross-sectional flow chart of a chip packaging process; FIG. 3 shows a cross-sectional view of a preferred embodiment of the present invention. D The cross-sectional view of the interconnect layer having a single wire layer. FIG. 4 shows a preferred implementation of the present invention. An example of a type d is a schematic diagram of a cross-section diagram of a multilayer wiring layer in an interconnecting layer 100: chip package structure 110: substrate 112: top surface 114: bottom surface 116a: bump pad 116b: fresh ball 塾 118 wire Layer 120 bump 130 chip 132 active surface 134 back 136 chip 塾 140 fresh ball 150 primer 200, 202, 204: chip package structure 210 glass substrate 210a: opening 212 first surface 214 second surface 220 wafer 222 active surface 224 back 226 Wafer 塾 230 Adhesive material layer 230a: Adhesive layer 240 Support layer 250, _251: No. -252 '• 256: Wire layer 252a, 256a: Go.

10035twf.ptd page 16 587317 Brief description of the drawings 258: Solder resist 270: Solder balls 252b, 256b: Wire 2 6 0: Interconnect layer 10035twf.ptd Page 17

Claims (1)

587317 VI. Application for Patent Scope 1. A chip packaging process (a) providing a glass substrate surface and a corresponding second surface; (b) providing a plurality of wafers including at least the following steps ... wherein the glass substrate has a first These chips each have two * / 1 7j / j ^ \ L L a-Fortunately, the moving surface and the corresponding one of the back, and it should also be W # π θ, Η. ^ ^ Au ^. A plurality of wafer pads', and the wafer pads are respectively disposed on the active watch of the corresponding wafers-and the wafers are disposed on the glass substrate via the active surfaces of the wafers. The first surface; (C) forming an adhesive layer on the first surface of the glass substrate, and the adhesive layer covering the back surface of the wafer; (d) configuring a support layer on the adhesive layer (E) forming a plurality of first conductive plugs on the glass substrate, wherein the first conductive plugs are respectively connected to the wafer pads of the wafers; (f) forming an interconnect layer on the glass substrate; The second surface of the glass substrate, wherein the interconnect It further has a plurality of bonding pads, which are located on a side of the interconnect layer that is far from the glass substrate, and the internal circuits of the interconnect layer are electrically connected to the conductive plugs; and (g) the particles are formed early. These chips. 2. The chip packaging process according to item 1 of the scope of patent application, wherein the material of the adhesive layer includes epoxy resin. 3. The chip packaging process described in item 1 of the patent application scope, wherein the material of the supporting layer includes one of glass, metal and graphite. 4 · The chip packaging process as described in the first patent application scope in the first step 10035twf.ptd Page 18 587317 It also includes the step of thinning the glass substrate from the second surface of the glass substrate (e) before the step (e). The wafer packaging process described in item 1 of the scope is included. In step (e), After forming a plurality of them, a conductive material f & μ μ σ $ Λ; and a first conductive plug on the substrate are respectively filled. The quality is within these openings, and the chip packaging processes are formed. Among them, the last name is perforation and supersonic. 6. The method of forming delta openings as described in item 5 of the scope of patent application is to use laser burning hole waves. One of the holes " One. 7. The chip packaging process as described in item 1 of the scope of the patent application, wherein the interconnect layer includes at least a patterned _conductor layer, which is disposed on the second surface of the glass substrate, and is electrically connected to the The first conductor and the wire layer form the bonding pads. 8. The chip packaging process according to item 7 of the scope of patent application, wherein the wire layer is formed simultaneously with the first conductive plugs. 9. The chip packaging process as described in item 7 of the scope of the patent application, wherein the interconnect layer further has a solder resist layer disposed on a surface of the interconnect layer away from the glass substrate and exposing the Some bonding pads. 10. The chip packaging process described in item 7 of the scope of the patent application, wherein the material of the wire layer is a material selected from the group consisting of steel, aluminum, the alloys, and combinations thereof. 11. The chip packaging process according to item 1 of the scope of the patent application, wherein the interconnect layer includes at least a patterned plurality of wire layers, at least one dielectric layer, and a plurality of second conductive plugs, wherein the wires Hierarchical configuration 587317 6. The scope of the patent application is on the second surface of the glass substrate, and the conductor layers closest to the glass substrate are electrically connected to the first conductive plugs, and the conductor layers are farthest away from the Those glass substrates form the bonding pads, and the dielectric layer is disposed between two adjacent wire layers, and the second wire plugs penetrate the dielectric layer and are electrically connected to adjacent ones. The wire layers. 12. The chip packaging process as described in item 11 of the scope of patent application, wherein the conductor layers closest to the glass substrate are formed simultaneously with the first conductive plugs. 13. The chip packaging process as described in item 11 of the scope of patent application, wherein the interconnect layer further has a solder resist layer, which is disposed on the wire layer farthest from the glass substrate and the dielectric layer, and is exposed Remove the bonding pads. 14. The chip packaging process as described in item 11 of the scope of patent application, wherein the material of the wire layer is a material selected from the group consisting of copper, aluminum, these alloys, and combinations thereof. 15. The chip packaging process according to item 11 of the scope of the patent application, wherein the material of the dielectric layer is a material selected from the group consisting of silicon oxide and silicon nitride. 16. The chip packaging process described in item 1 of the scope of patent application, after step (f) and before step (g), it further includes forming a plurality of contacts on the bonding pads, respectively. 17. The chip packaging process according to item 16 of the scope of patent application, wherein the contacts are one of solder balls or pins. 18. A chip packaging structure, comprising at least: a glass substrate having a first surface and a corresponding second surface; 587317 VI. Patent application scope At least one wafer 'has an active surface and a corresponding back surface, and the wafer further has a plurality of wafer pads, which are respectively arranged on the active surface of the wafer' and the wafer is configured with the active surface On the first surface of the glass substrate; an adhesive material layer 'comprehensively covers the first surface of the glass substrate and covers the back surface of the wafer; a support layer disposed on the adhesive material layer; a plurality of A first conductive plug penetrates the glass substrate and is electrically connected to the wafer pads of the wafer, respectively; and an interconnect line layer is disposed on the second surface of the glass substrate and has a plurality of bonding pads. The side of the interconnecting layer that is far from the glass substrate and the internal wiring of the interconnecting layer are electrically connected to the first conductive plugs. 19 · The chip packaging structure described in item 18 of the scope of patent application, wherein the material of the adhesive layer includes epoxy resin. 20. The chip packaging structure as described in item 18 of the scope of patent application, wherein the material of the branch floor includes one of glass, metal and graphite. 21. The chip package structure according to item 18 of the scope of the patent application, wherein the interconnect layer includes at least one patterned wire layer, which is disposed on the second surface of the glass substrate and is electrically connected to the The first conductive plug is 0, and the wire layer forms the bonding pads. 22. The chip package structure according to item 21 of the scope of patent application, wherein the wire layer is formed simultaneously with the first conductive plugs. 23. The wafer sealing structure described in item 1 of the scope of patent application, which Page 21 587317 6. In the scope of the patent application, the interconnecting layer further has a solder resist layer, which is arranged on the surface of the interconnecting layer farthest from the glass substrate, and exposes the bonding pads. 24. The chip package structure described in item 21 of the scope of the patent application, wherein the material of the wire layer is a material selected from the group consisting of copper, aluminum, these alloys, and combinations thereof. 25. The chip package structure described in item 18 of the scope of the patent application, wherein the interconnect layer includes at least a plurality of patterned wire layers, at least one dielectric layer, and a plurality of second conductive plugs, wherein The wire layers are sequentially arranged on the second surface of the glass substrate, and the closest to the glass substrate of the 呰 wire layer is electrically connected to the first conductive plugs, and the wire layers are farthest away The glass substrates form the junctions, and the dielectric layer is disposed between two adjacent wire layers, and the second wire plugs penetrate the dielectric layer, and electrically connect the phases. Adjacent to these wire layers. 26. The chip package structure according to item 25 of the scope of the patent application, wherein the conductor layers closest to the glass substrate are formed simultaneously with the first conductive plugs. 27. The chip package structure described in item 25 of the scope of patent application, further comprising a solder resist layer disposed on the surface of the interconnect layer that is furthest from the glass substrate 'and exposing the bonding pads. 2 8 · The chip package structure described in item 25 of the scope of patent application, wherein the material of the wire layer is a material selected from the group consisting of copper, aluminum, these alloys, and combinations thereof. 2 · The chip package structure described in item 25 of the scope of the patent application, in which the 50 Ohm; 1 The material of the electrical layer is selected from the group consisting of silicon oxide and silicon nitride Page 22 587317 VI. A material for patent application. 30. The chip package structure described in item 18 of the scope of patent application, further includes a plurality of contacts, which are respectively disposed on the bonding pads. 31. The chip package structure described in item 18 of the scope of the patent application, wherein the contacts are one of solder balls or pins. I 4 10035twf.ptd Page 23