TWI309962B - Circuit device and menufacturing method thereof - Google Patents

Circuit device and menufacturing method thereof Download PDF

Info

Publication number
TWI309962B
TWI309962B TW94104161A TW94104161A TWI309962B TW I309962 B TWI309962 B TW I309962B TW 94104161 A TW94104161 A TW 94104161A TW 94104161 A TW94104161 A TW 94104161A TW I309962 B TWI309962 B TW I309962B
Authority
TW
Taiwan
Prior art keywords
conductive pattern
circuit
conductive
convex portion
pattern
Prior art date
Application number
TW94104161A
Other languages
English (en)
Other versions
TW200539758A (en
Inventor
Yusuke Igarashi
Sadamichi Takakusaki
Motoichi Nezu
Takaya Kusabe
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200539758A publication Critical patent/TW200539758A/zh
Application granted granted Critical
Publication of TWI309962B publication Critical patent/TWI309962B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

1309962 九、發明說明： [發明所屬之技術領域】 造方法，特別是 路裝置及其製造 本發明係關於一種電路裝置及其穿j 關於一種具有厚度相異之導電圖案的電 方法。 【先前技術】 參照第1G圖說明習知混合積體電路裝置之構成（炎昭
例如專利文獻1)。第10A圖係混合積體電路袭置⑽Z 視圖。第10B圖係第10A圖之χ-χ，線剖視圖。 ’、 習知混合積體電路裝置100具有以 電路裝置100係具有：矩形之基板1〇6. #在^合積體 Φ ^ , 攸1UD，叹置在基板106 之表面的絕緣層107 ;形成在絕緣層1〇7上之導電圖突 108’固著在|電圖t 1〇8上之電路元件1〇4;與電：元 件104及導電圖帛108電性連接之金屬細線服及 電圖案m電性連接之導和ead)1G1i合積體電路裝 置100整體係由密封樹脂102所封裝。㈣封樹脂1〇2封 裝之方法有使用熱可塑性樹脂之射出模塑法，及使用執硬 化性樹脂之移轉模塑法。 … (專利文獻1)日本特開平6_1 77295號公報（第4頁第1圖 【發明内容】 (發明所欲解決之課題） 然而，在前述混合積體電路裝置1 00中，安裝大電流 用之功率系元件之混合積體電路基板（以下稱基板）與安裝 信號系元件之基板，其導電圖案之膜厚會不同。例如安裝 316740 1309962 =率糸元件之基板，其導電圖案之厚度為例如⑽"。安 j號系元件之基板，其導電圖案之厚度為35㈣。因此， ::要安農之元件的不同而準備導電圖案之厚度不同的基 板的话’會有成本上升之問題。 具有厚度程度之厚導電圖案的基板，由 方；無法以厚的導電圖案形成細微之圄安m 士 子I夕+ TCHT 倣之圖案，因而有不能將端 數夕之 LSI (Large Scale 安裝於安裝基板的問題。又H 體電路） 薄導恭Fi安mu 在具有尽度僅35# m程度之 〜圖案的基板安裝功率系元件時 斷面積小，故有益、丰左仅 ，导的等电圖案之 士 有…/去確保充分之電流容量的問題。 备明係鑑於上述課題而研創， 種可在確伴带、、*〇ν_^όΑη ± 者其目的在於提供一 C…的同時形成細微圖案之電路裳置及其 (解決課題之手段） 本發明之電路裝置係具備 電圖案，及與前述導電圖案電性連接板的表面之導 :::由第1導電圖案及形成得比前⑵ 之弟2導電圖案所構成，前述 ：〜圖案厚 電圖案之表面係配置於實質相同的水;木與前述第2導 圖案之背面，設置有相較於前述第二：前述第2導電 於厚度方向的凸部。 黾圖案之背面突出 本發明之電路裝置俦且 電圖荦，及盘二、十.，旨 成在電路基板的#而夕、曾 ⑶木’及與刖述導電圖案電性 ㈣表面之導 電圖案係由第！導電圖电路元件；前述導 秦比河述第1導電圖案厚 1309962 :之第2導電圖案所構成，前 -電圖案之背面係配置於每彳 电圖案與前述第2導 F1安 只貝相同的水平，少乂丄 圖案之表面’設置有相較於前述第丄在則述第2導電 於厚度方向的凸部。 電圖案之表面突出 本發明之電路裝置係 電圖案，及與前述導電圖案電路基板的表面之導 電圖案係由第！導電圖案 ：电路元件；前述導 鲁之第2導電圖案所構成二侍t别逑第1導電圖案厚 面，設置有突出於厚度方向的凸部。^电圖案之表面與背 又’本發明之電路梦署也& 質上與第1導電圖宰相凸部之周圍形成有實 电回茱相问艇厚的緣部。 又，本發明之電路裝置係使 1導電圖案之厚度寬。 袭邙之寬度比前述第 又’本發明之電路裝置中， 述電路基板的表面之絕緣層。a领埋入形成於前 陶瓷^本發明之電路裝置中，前述電路基板係全屬A板、 陶，、印刷基板或換性薄糊
有第1電之:：裂置中，在前述第1導電圖案連接 、, 件’在鈾述第2導電圖案連接右3 A Μ述第1電路元件大之第2電路元件 有“L合置比 於厚度方向之电：裝置之製造方法係準備表面設置有突出 又°之凸部的導電箔，以使前述凸部埋 電路基板的表面之¥ M w _v U;刖遠 述電路基拓 ㈣方式’使前述導電绪密接在前 土反’亚將未設有前述凸部之區域的前述導電结予
316740 1309962 以部分去除，藉此形成第 比前述第1導電圖案厚的 又，本發明之電路裝 犬出於厚度方向之凸部的 接在設於電路基板的表面 之區域的前述導電箔予以 案，及包含前述凸部且比 圖案。 又，本發明之電路裳 設置有突出於厚度方向之 入設於前述電路基板的表 箔密接在前述電路基板， 述導電箔予以部分去除， 前述凸部且比前述第1導 又’本發明之電路裝 面係為曲面。 又’本發明之電路裝 第1導電圖案相同厚度的 式’將前述導電箔予以圖 又，本發明之電路裝 之寬度比前述第1導電圖 又，本發明之電路裝 理，形成前述第丨導電圖 (發明之效果） 1導電圖案，及包含前述凸部且 第2導電圖案。 置之製造方法係準備表面設置有 導電箱，使前述導電落之背面密 之絕緣層’並將未設有前述凸部 部分去除，藉此形成第1導電圖 前述第1導電圖案厚的第2導電 置之製造方法係準備表面及背面 凸。卩的‘電箔，以使前述凸部埋 面之絕緣層的方式，使前述導電 並將未設有前述凸部之區域的前 藉此形成第1導電圖案，及包含 %圖案厚的第2導電圖案。 置之製造方法中，前述凸部的側 置之製造方法中’係以使與前述 緣部殘存在前述凸部之周圍的方 案化。 置之製造方法中，係使前述緣部 案之厚度寬。 置之製造方法中，係藉由蝕刻處 案及前述第2導電圖案。 316740 !309962 根據本發明，可在丨個電路 同之導雷岡安mL 土板之表面，形成厚度不 較;^，π: 使要求電流容量之導電圖荦形成 專乂尽，可使較小電流通過之部分 ^^成 且，可刹田，叫、话 ]导屯圖案形成幸父溥。而 了利用細彳政之導電圖案使 所要求之+— θ的 、展在度交南。因此，可依 晋欠之谷I將圖案規則（ 圖案形成在Η固電路基板上。P tternrule)不同之導電 較厚將大電流通過之第2電路元件固著在形成 子乂y子之弟2導電圖幸，田从可v±外 ^ y ρχ, 積極地散出至外部:、特別是=電路元件所產生之熱 示，導電圖案背面之—部八埋入广弟6圖及第7圖所 - 刀里入 '、，巴緣層的導電圖幸，苴北 面之凸部係由絕緣樹脂所覆甚， 其月 導提升。 因而使透過絕緣層之熱傳 【實施方式】 ^照第1圖說明本發明之混合積體 成。弟1圖（A)係混合積體電 置10之構 •⑻係第i圖⑴之x x :: 4置10之斜視圖。第1圖 布丄口 之x-x剖面的剖視圖。 本發明之混合積體電路裝 板16表面的導雷鬥宏1Q 備形成在電路基 表面的，圖t ίδ，及與導電圖案⑺電 路兀件14，月；I述導電圖宰J 8 兒 成得比第】導電圖宰厚之第?:幻導電圖請及形 h圓請係形成電流 弟2 構成。以下說明上述各構成要素/ W圖案⑻大之 電路基板16在散埶之觀奸 構成之基板。亦可為由^ 金屬或陶竞所 為心性潯片或樹脂所構成的印刷基板 1309962 I 只要是至少基板表面接受過絕緣處理者h 板Μ之村料可採用Ai、c_F 者即可。電路基 A1N。亦可以其他機械強度及散敎性採用键、 之材料。舉—例而言，採用心，構；;者 =為電路基㈣ 16時，電路基㈣之表面係由嗯C作為電路基扳 層17之表面形成有導電圖幸18二層17所覆蓋。在絕緣 路基板16與導電圓㈣予以絕斧亦即以絕緣層17將電 基板1 6的表面、隹—+允 巴承 對由A1構成之電路 的表面進仃耐酸鋁⑴umite)處理。 路 多照第1圖（B)，為使從載置於带 路元件14所產生之熱適當地散出至:土板Μ表面的電 5面係從密封樹脂12露出在外部’電广基板16之 濕性，亦可以密封樹脂12封裝 路：裝置整體之耐 體。再者，亦可以外殼（case):路基板16背面之整 電路元件“係固著在:)^ 14與導電圖荦18構成子 " 上，且以電路7L件 赢田兩 8構成預定之電氣電路。雷踗开杜14焱4 •用電晶體或二極體等主動 —$路兀件14係採 件。又，功率系之半導===或電阻等被動元 亦可將樹脂封= = 基㈣。又， 以面朝上之方式安裝的主# =圖案18。在此， 與導電圖案18電性連接。H透過金屬細線15 在本形態中，電路 電路元件14A ; 匕含：流通較小電流之第j 呈卿’二、父大電流之第2電路元件⑽。 ^例中’弟1電路元件14A可列舉LSI晶片、電容 3】6740 10 1309962 电阻等。为面與接地電位等電性連接的LSI θ #透 ==電性膏(_與導電= 薄之例如：：小之第1電路元件陶固著在形成較 !如數十㈣度的第1導電圖請。 弟2電路元件14β係連接 程度的第2導電圖請。第2 =如數百^ 制大雷、、六夕a φ / 弟Ζ电路兀件14β係可採用控
Se . 7…系電晶體例如功率M〇S(Metal 〇xlde
Semiconductor，金屬氧化物束道 .ate h· nl Μ 化物切體）、iGBT(⑽ulated blPQlar加㈣咖，絕 體（thyristor)等。又 又载子“脰）、間流 元件之晶U寸小且Hi之/亦可。該等第2電路 量。 A尘且问功能，故會大量產生熱 ‘電圖案18係由銅等金屬 緣而形成。在導出導腳成’並與電路基板16絕 成之銲墊（pad)。導腳i，形成有由導電圖案18構 至少-邊:導;出進行說明，但只有從 著劑接著在電路基716之=圖。=係簡緣層㈣接 电圖案18Α及形成得比第i導電 案1δβ所構成。且依照第1導電圖案^:二：電圖 18Β窄的圖案規則。 Α比弟2 ν電圖案 弟1導電圖案18Α係形成較 圓案。第1導電圖安•与度數十//m程度的 。： ⑽之厚度係選擇在9赠如 私度之間。適合於量產水準 Am 平之弟1導電圖案18A的厚度為 316740 1309962 =如3〇❹。如為該厚度，可利兩濕式餘刻使圖 同接近於50 g m程度。在此，圖案間 、 $ ^ ,Β1 Ί %係指從相鄰圖 /、内側的端部至端部的距離。如為該厚 :度,8至一度，可形成細::圖:= 號二1的ISΑ #用作為使例如數mΑ程度之電氣信 圖案18A SI元件之控制信號通過第1導電 圖宰第】！=請係形成得比第1導電圖㈣厚之 選;在=案18B之厚度可依據所要求之電流容量
之厚产作2至500㈣私度之間。將第2導電圖案18B 度心為程度時，可將圖案間的間隔及圖案寬 下:度。在如此之第2導電圖案ΐ8β之情況 』導通50Α程度之電流。 導電形成在電路絲16之表面全域，具有使 I緣声面與電路基板16之表面接著之功能。絕
而D吏乳化心1Umina)等無機填料高度充填在樹脂 成者’且形成熱傳導㈣者。導電_ U 壓而變化，但最好為50/ζπ!程度以上。 導腳11係接著在設於電路基板16之周邊部的銲塾， ^具有例如進行與外部之輸出、輪人的功能。在此，在— =有多數個導腳n。導腳與鲜塾之接著係藉由銲錫 (I于料）寺導電性接著劑進行。 密封樹脂12係藉由使用熱硬化性樹脂之移轉模塑 316740 12 1309962 封塑性樹脂之射出模塑法而升〈成， 子羞笔路基板16及形成於A ^ 乂成。在此，以 密封樹脂12,使電路μ 电氣電路的方式形成 再者，模塑封細卜：f 面從密封樹脂。露出。 触供土封衣以外之封裳方法亦適用於〜 ^ :電路裝置’例如樹脂接合㈤恤 ：：合積 裴等其他封裝方法亦適用。 扁、外奴材之封 、麥照第2圖之斜視圖說明形成於電路基 導電圖案18的具體形狀$ , 反16之表面的 的圖示。 遷之—例。在此省略封裝整體之樹脂 如上所述，本形態中’導電圖案丨8可分 弟1導電圖案18A及形成較厚之第2導電圖案⑽。乂第〜 圖中，以實線顯示第i導電圖案18A， 第 導電圖案⑽。亦即，以小信號通過之圖案作為第、員； 圖案18A來設計，以大信號通過之圖案作為第2導電圖< 18B來設計。在此，大信號可列舉例如進行揚聲器或$馬°岛 之驅動的信號。小信號可列舉輸出入於例如本身為) 件之第1電路元件14A的信號，及出入於例如本身為開j (switching)元件之第2電路元件14β之控制端子的電氣^ 號。 在此’連接在本身為LSI元件之第1電路元件的圖案 係由第1導電圖案18 A構成。使用在LSI元件之信號處理 的電氣信號係數m A程度，因此利用厚度數十# m程度之第 1導電圖案18A，電流容量即十分充足。又，第1導電圖案 18A係形成得很細微，因此可採用端子數多之LSI元件作 316740 13 !309962 為第1電路元件14A。 第2導電圖案18B係連接在功率電晶體等之第2電路 元件14B的流出、流入電極。亦即，根據透過第工導電圖 案18 A輻入之小k號，進行流通於第2導電圖案}仙之二 電流的開關（swi tching)。 參照第3圖說明第2導電圖案18β之詳細。第3圖 至第3圖（C)係顯示第2導電圖案18β之形狀。 參照第3圖⑴，在此，係藉由局部地設置凸 形成較厚之第2導電圖案18B。又，設置在第2 末 18B之背面且一體突出於展碎 ' 固木 月且大出於；度方向的凸部22，係埋入 層17。且第1導電圖案18a 、、·、彖 面與弟2導電圖荦— 上面係實質位在同一平面上。 书回木18B之 將第1導電圖案18A之厚度設定為Ti，將第？ h圖木18B之凸部22埋入絕緣層η之深戶 將第2導電圖幸1抑十田A 又。又疋為T2， /、 之取下σ卩與電路基板16之丰而沾 設定為Τ3。為了將第丨 b之表面的距離 係設定為心，崎度 =、二’η最好 之電流容量’Τ2最好設定為35二广電圖案18B 第2導電圖案18B A m程度。亦即， 丁2之厚度。T3在考/而相較於第1導電圖案⑽增加 程度。考慮耐壓性的情況下’最好為5一至 以下說明第？道+ ^ + 笔圖案18 B部分埋入窄终 之優點。首先，因第2導電圖宰丨、=層”所產生 16之表面’故可透汛货 下面接近電路基板 。2導電圖案18β及絕緣層17使第2
336740 14 1309962 電路元件14崎生之熱散出至外部。在本形能中，# 性之範圍’絕緣層17係以較薄者為佳。因此，= 使弟2導電圖案]δβ部分埋入 錯由 9植a 豕智W的構成，可縮轺结 2 h圖案18B與電路基板16之 '昂 整體散熱性之提升。 由此，有助於裝置 的構：者“藉，使第2導電圖案1δβ部分埋入絕緣層1? >面并、可f第2導電圖案18β之背面與絕緣層1 7接觸之 开二:大」因此，可更加提升散熱性。以凸部22形成：方 ^例，貫f上除了上面以外之各面均與絕緣層17抵接方 =可提升散熱性，而可實現省略散熱片之構成。再：。 電圖木8β部分埋入絕緣層Π，可提升 之您接性。因此，可提升第知升兩者 由於第1導電圖宰丄:: 強度。 保第1導電圖宰不埋入絕緣層17,因此可禮 此，可減低第/導電圖、：二= 路基板16之距離較長。由 生電容。因此，即使路基板16之間產生之寄 、、兄介叮 Ρ使阿頻彳§唬通過第1導電圖案18Α的愔 /亦可P#止ϋ寄生f容所造成之信號延遲等。 ::⑽係形成於第2導電圖案ΐ8β之周緣部的部 ”厚度與第i導電圖案i8a相同。緣部⑽係芦由 刻進行導電圖案18之製造所設的部位。具: 刻使導電圖幸1 S FI安 &由钱 s木18圖案化時，為了防止凸部22被蝕刻 =2广:周圍設置凸緣⑴―)。該凸緣部分即成為緣部 立灰凸部22之周圍。緣部18D之寬度T4最好在第i 316740 15 1309962 導電圖案18A之厚度以上。作為 um ^ ^ „ L 1 j見度T4最好為loo ..又。廷是由於進行導電圖案丨8之圖荦化的蝕y 係以等向性進行之故。Α τL u木化的蝕刻 β 防止以等向性進彳 凸』22,欺好將緣部⑽之寬度 達 —案18A之厚度為寬。 疋為比弟1導電圖 參照第3圖⑻，說明將第2導電圖案18 的其他構成。在此，形成較厚部分具 :乂子 心第2導電圖請。因此，第2導電圖== 積會變大，可確保大的電流容量。再者，藉由使厚度^面 可減小過渡熱電阻。又，第1及第2導電圖案之底面 於同一平面上。 /、-面知位 參照第3圖（〇，第2導電圖案18β之較厚部分係因作 出於上方向及下方向之兩方，故可形成得較厚，： 第2導電圖請之表面及背面形成凸部22。因： 第2導電圖案刚形成得更厚，可更增大電流容量之= 及過渡熱電阻之減低的效果。利用複數次之兹刻可 2導電圖案18Β，因此可使緣部⑽變小並使圖案〜。 如第4圖⑻、第5圖⑹及第6圖⑻所示，薄:子圖。安 與厚的®案-體形成時，在薄的部分進行圖案化而同時= 成厚的圖案’則具有可一次完成圖案化的優點。… 其次，參照第4圖說明上述混合積體電路裝 、皮 方法。 衣每 盲先’麥照第4圖’說明具有第3圖⑴所示之 狀的導電圖案1δ之製造方法。 形 16 316740 ⑧ 1309962 (res.sJia. kresistVl圖案化。導電箔別之 材料的金屬，F e與N,之合金或以：° 用以銅為主 電領20之厚度係依所要 ，，，、材枓的材料。導 笙i首予门也 办成之導電圖案18之厚声而思 弟2導電圖案18B之厚度為 卩度而異。 度以上之導電落20。阻劑21 _、古^/王度日可，係採用該厚 ⑽的部位。 心心被覆要形成第2導電圖案 、參照第4圖⑻，其次以阻劑21作為卿罩… 蝕刻’進行未形成阻劑21之主面的蝕：罩進心 被阻劑21 ;皮覆之區域的導 =刻對未 :修在此’進行微細的圖案化，： = = = 木18Α之區域形成得十分薄。具體 = 程度。藉由本製程使 ^刀係浴成犬出成凸狀的凸部22 ; 劑21剝離。 衣柱、、，=束後，將阻 _之4^二（〇及第4圖（D) ’使表面設有絕緣層17 电路基板16與導電落㈣接。具體而言，以使凸部Μ 二絕=17的方式使導電陶接於電路基板16。該 二二、广麼制機（VaCUU,n ΡΓ_進行時，可防止因導電 、巴、’彖層1 7間之空氣而產生的間隙(Void)。又，以 寻向f生钱刻形成之凸部22的側面係形成平滑之曲面。因 此，將導電辑入絕緣層Π時，樹脂沿著該曲面侵入， 而不會有未充填部。由此，藉由該凸部22之側面形狀可抑 制間以之產生。且因使凸部22埋入絕緣層1 7，故可使導 Π 3)6740 1309962 電箔2 〇盘绰祕爲]7 /、冱、味層17之密接強度提升。 再者’第4圖（〇之導雪咬9η ^ 為下面）係呈平面，故 / 6、上面（在第4圖（β)中 卞囱故可全面與厚-入、、厶目, r 以全面均句的力均等地予以加壓r具之抵接面抵接，可 翏照第4圖（E)，1次谁r姑— 箱2〇的圖案化。具體而、二 電路基们6之導電 及第2導带°在形成對應予定形成之第j 牙z¥电圖案之形狀的阻 弟1 圖案化。在此，被覆對庳 麦^由進行钱刻而進行 電落的阻劑21，#==㈣圖案⑽之區域之導 止因下—制口传比凸部22更寬。這是為了防 , 衣私之蝕刻而侵蝕凸部22之故。再者，^去 成阻劑⑴夺之遮罩的偏移，藉由以 再者:考慮形 進行導電圖案18之分離。 可確貫以蝕刻 2〇進稭由對除了凸部22以外之區域的導電笔 ==刻而將導電$2G予以部分去除，而形成t =圖案18A及較厚之第2導電圖案刚 程度之薄的部分的導彻予U 。併形成厚度不同之導電圖案18。 ” #麥照第4圖（F)說明透過阻劑21進行姓刻後的第 :圖/卞18A及第2導電圖案18B的剖面。形成有凹部饥參 照第4圖⑻)之區域的導電辖2〇，其厚度較薄至： 程度。因此’第！導電圖案1δΑ微細地形成。在此，利用 —次蝕刻，可形成較薄之第i導電圖案m及較厚 導電圖案18B。 緣部18D係以平面地包圍&部22之方式形成。換言 316740 1309962 :，藉由使被覆凸部22的上部 寬，而形成緣部18D。如此，餘 比凸。"2 藉由使阻劑21形成較寬 ？^ 1δβ時， 飿刻係等向性，故對第2導:丁刻。亦即’濕 此，葬由d ? 面形成斜面(_咖)。因 二廣地進行姓刻，可防止因側㈣而酬 2導電圖案18Β。 』丨又鄉乐 八^ 弟2導電圖案Ϊ8Β之剖面箱 冒受小，無法確保大的電流容I 積 包含草種”η 里且散熱性會降低。又因 。3某種私度之…形成阻劑2卜故可藉由 防止因該誤差所造成之凸部22的侵蝕。 蒼肢第5圖說明上述混合積體電路裝置之第2制 ^在此說明形成第3圖⑻所示之第2導電圖案 k方法。在此之導電圖案18 ^ 、 〜珉万法係與乐4圖所說明 之Φ成方法相同，故以不同之部分為中心加以說明。 、、參照第5圖⑴至第5圖（〇,首先使導電箱2〇密接於 塗布於電路基板16表面的絕緣層17。在此，因在導電 2〇較厚之狀態下進行壓接，故可抑制壓接製程中導電二 之「皺紋」的產生。然後，在以阻劑2丨被覆要將形H交厚 之第2導電圖案1δβ的區域後，進行導電箱2〇表面的蝕子 刻。利用該蝕刻，使將形成較薄之第i導電圖案18α的區 域之導電落20變得非常薄。該蝕刻結束後，剝離阻劑 參照第5圖（D)，將新的阻劑21塗布於導電領2〇之表 面後，為了形成第1導電圖案及第2導電圓幸， " ^ 逆订阻劑 316740 ]9 21之圖案化。此時，為了形 2 2之阻劑2 "皮覆的範圍比：部二：⑽，使被覆凸部 22之側面延伸一薄幅邻八& 士 ^見廣。亦即，以從凸部 . Ρ刀的方式塗布阻劑2】。 麥照第5圖⑻，其次透過 相 第1導電圖案及第2導電圖案。^ 1進行㈣，而形成 &不會被㈣，可進行釋& =成緣部⑽，故凸部 離阻劑2〗。 “ 圖木化。該蝕刻結束後，剝 參照第6圖，說明上述混合 方、、土 . 个貝月丑电路裝置之第3制谇 方决。在此說明形成第3圖⑹ ：3 --
的製造方φ。卢仏七首 义弟2導電圖案18B 衣i方法。在此之導電圖案18 圖說明夕郴士士、+ #丄 < $成方法係與茶照第4 允月之形成方法基本上相同，故 以說明。 M J之口p刀為中心加 阓安1ηπ y 牡預疋形成第2導‘ 用^仙的導電㈣表面形成阻劑21，並進行❹Λ
參照第6圖⑴圖及第6圖⑻，在預定形成 =刻:形成凸部22。設有凹部23之區域的導電^ 尿子广’係比預定形成之第1導電圖案m厚。且因利） ::治具抵接其面來進行壓接，故可抑制壓接製程度 书箔20之「皺紋」的產生。 芩照第6圖（C)及第6圖（D)，其次以阻劑21被覆形成 有凸部22之區域的表面。然後進行蝕刻。本製程中蝕刻之 目的係在導電箔20之兩面形成凸部22，及使設有凹部Μ 之區域的導電箔20變薄。本製程結束後，剝離阻劑21。 參知、弟6圖（Ε)及第6圖（F)，將新的阻劑21塗布在導 電泊20之表面後，為了形成第！及第2導電圖案，進行阻 316740 20 1309962 劑21之圖案化。在此，使覆蓋凸部22之阻劑21，以超出 凸部22的方式被霜异邱99 谈凸。卩22。在本製程中，由於在導電箔 20之兩主面形成凸部' 又〇 口丨“，因此可使第2導電圖案18β形 較厚。 蒼”.、第7圖，說明上述混合積體電路裝置之第*夢造 方法。在此說明形成第3圖(c)所示之第2導電圖案‘ 的製造方法。 …f照第7圖(A)及第7圖⑻’首先在對應於預定形成 第2導電圖案18B之區域@9n 匕攻扪¥电’泊20的表面及背面形成 劑21。然後，進行導雷笮川沾主二 ^风丨且 、 疋仃令电泊20的表面及背面之蝕刻，在兩 主面形成凸部22。因此，利用一 _欠 之兩主面形成凸部22。 …刻，可在導⑽ 參照第7圖（C)至第7圖⑻，以使凸部22埋入絕緣声 π的方式使導電箱2G密接於電路基板16後 '^ 案18之圖案化。該方法係與 书θ 略並…弟b圖说明者相同，故省 明二第二？:!於使導電圖案18圖案化之製程的說 二二 方法所形成之混合積體電路基板係 =弟δ圖所不，將電路元件配置在所希望之部位 路兀件與導電圖案18電性連接。 、’.毛 麵，透過銲錫與導電f將電路
者在導電圖案（島部）]8。在此，進 U ^ - Μ , , ^订J电流處理之第1雷 14A係固著在第]導電圖案]8 欹景炙+哲。& 柯遇人％流且發 …、夕之弟2笔路元件14β係固著在第2導 因第】導電圖案m可構成微％圈安 木8β。 Ί、田θ案，故可採用LSZ元件 316740 21 1309962 等端子數多的元件作為第 劃可形成為充分厚故二:件4A。第2導電圖案
電晶體、LSI等作；^第採用進行大電流處理之功率 寺作為罘2電路元件14B。在此 合積體電路裝置之·個單 成H 16,以也、p 早兀Μ可形成在1片電路基板 以—併進行晶粒接合（dle b〇n bonding)。 “久力、，尿接合（wire 參照第8圖（B)，經由金屬細線 與導電圖案18之電性連接。太丑…,— 兀件14 10D 埂接本形恶係错由將第2導恭pi安 ⑽之厚度部分埋入 ：〜圖案 ^ m ^ 向1更弟1導電圖幸18A盥 弟2V電圖案18β之上面形成同一高 逸二 電路元件UB之電性連接時，可使用 進？ 2 以往，载置在散熱片等的上部之電晶體田線_； 低差报大。竽古彻茬古卩士达 〇令电圖案18之高 ,有為例如2咖程度。因此，為了避 丨、，泉因本身重量而下垂且與晶片或散熱片敗 使用彈力較強的粗線。本形態中，因相當於散路二而 導電圖案18Β與第1導電圖案18Α形成之弟2 用彈力較強的粗線。在此，細線係指二故無須使 之金屬細線。 直仏80/^程度 以製程結束後，進行各單元24之分離。各單元％ 之刀離可藉由使用沖壓機之沖壓法、切 一 行。然後，將導腳u固著在各單元之‘路:、：:法等進 芬照第9圖，進行各電路基板16之樹脂封裝 不藉由使用熱硬化性樹脂之移轉模塑法- 〇>7 4+ , 打封。亦即， 知包路基板1 6收納在由上模具30A及下握θ 卜核具3QB所構成之 316740 1309962 模具3◦中後，使兩模具抵接，而將導腳 由將樹脂封入模穴(cavity)31，進行 ：定。： 以上之製程，製造第1圖所示之混合積體電 在習知混合積體電路裝置中，因導 ； 膜厚形成故在需要大電流之部分，形成之導^同一 或另外採用散熱片。然而在本案中，厚的第2 :電圖案， 與薄的第1導電圖案ISA可形成在同—、：圖案18β 置。因此莽由厚的楚9、曾+ 叱合積體電路裝 容量。且案18β’確保散熱性及電流 系:零:…的弟1導電圖案⑽，可安裝小信號 第2 ί :Γ;8βΑ1形成之電路基板16時，藉由使形成於 絕緣乂 ;Γ:二凸部22埋入被覆電路基板16表面的 ，:：層，可使散熱性提升。這是由於從固 2^2良件產生的熱，經由埋入絕緣層I?之凸： 【圖式簡單說明】 第1圖係本發明之混人夢雕#
視圖（β)。 D積肢电路裝置之斜視圖（Α)、咅丨J :2::本發明之混合積體電路裝置之斜視圖。 ⑹。弟”、本％明之混合積體電路裝置之剖視圖(A)至 方“ = ===本發明之現合積體電路裝置之製造 Μ 31674^ 1309962 第5圖係用以說明本發明之混合積體 方法的剖視圖（A)至（E)。 裝置之製造 第6圖係用以說明本發明之混合積體 方法的剖視圖（A)至（F)。 扁置之製造 第7圖係用以說明本發明之混合積體電 方法的剖視圖（A)至（E)。 衣之衣造 第8圖係用以說明本發明之混合積體電路裝置之萝造 方法的剖視圖（A)、剖視圖（B)。 衣& 第9圖係用以說明本發明之混合 方法的剖視圖 足心衣k 路骏置之製造方法的剖視 第10圖係習知混合積體電 圖（A)、剖視圖（B)。 【主要元件符號說明】 14、 104 電路元件 14B 第2電路元件 16、 106 笔路基板 108 導電圖案 18B 第2導電圖案 18D 緣部 20 導電箔 22 凸部 24 ΌΌ 早元 3〇A 上 14A 15、 17、 18A 18c 19 21 23 30 30B 100 31 模穴 第1電路元件 1〇5金屬細線 107絕緣層 第1導電圖案 銲墊 銲料 阻劑 凹部 模具 下模具 混合積雜電略裝置 24 1309962
101 導腳 102 密封樹脂 τι 厚度 Τ2 深度 Τ3 距離 Τ4 寬度
25 316740

Claims (1)

  1. 第 1309962 十、申請專利範圍·· 1:=以備形成在電路基板的表面之導電圖 . ;:二边導電圖案電性連接之電路元件，· 第1導電圖案及形成得比前述 ，案厚之第2導電圖案所構成， 在前述第2導電圖案之表盥詈 厚度方向的凸部。 （、月面δ又置有突出於 之圍第1項之電路裳置，其中，在前述凸部 3如；C質上與第1導電圖案相同膜厚的緣部。 •3 =圍第2項之電路裝置，其中，使前述緣部 見度比則述第1導電圖案之厚度寬。 利範圍第1項之電路裝置’其中，前述凸部係 入形成於前述電路基板的表面之絕緣層。 .2請專·㈣1項之電路裝置，其中，前述電路基 6 =金屬基板、陶£基板、印刷基板或撓性薄片。 .導ΐ =利範圍第1項之電路裝置，其中，在前述第1 ¥电圖案連接有第1電路元件， 在前述第2導電圖案連接有電流容量比前述第1 電路元件大之第2電路元件。 7.—種電路裝置之製造方法，係钱表面及背面設置有突 出於厚度方向之凸部的導電辖， 以使前述凸部埋入設於電路基板的表面之絕緣層 的方式，使前述導電箱密接在前述電路基板， 並將未設有前述凸部之區域的前述導電箱予以部 316740修正本 26 第94104161號專利申請案 (97年12月23曰') 1309962 1去除,藉此形成第1導電圖案，及包含前述凸部且二 .4第1導電圖案厚的第2導電圖案。 8. 利補第7項之電路裝置之製造方法，其中， 前述凸部的侧面係為曲面。 、 9·如申明專利範圍第7項之電路裝置之製造方法，其中， 係以使與.¾•述第丨導電圖案相同厚度的緣部殘存在前 述凸部之周圍的方式’將前述導電箔予以圖案化。 ίο.如=請專利範圍第9項之電路裝置之製造方法，其中， 使剛述緣部之寬度比前述第1導電圖案之厚度寬。 11.如:請專利範圍第7項之電路裝置之製造方法，其中， 係藉由姓刻處理，形成前述第丨導電圖案及前述第2 墓図也 〒电圖莱。
    316740修正本 27
TW94104161A 2004-02-24 2005-02-14 Circuit device and menufacturing method thereof TWI309962B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004048259 2004-02-24

Publications (2)

Publication Number Publication Date
TW200539758A TW200539758A (en) 2005-12-01
TWI309962B true TWI309962B (en) 2009-05-11

Family

ID=34879504

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94104161A TWI309962B (en) 2004-02-24 2005-02-14 Circuit device and menufacturing method thereof

Country Status (5)

Country Link
US (1) US7714232B2 (zh)
JP (1) JP4785139B2 (zh)
CN (1) CN100527393C (zh)
TW (1) TWI309962B (zh)
WO (1) WO2005081311A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4711792B2 (ja) * 2005-09-26 2011-06-29 三洋電機株式会社 回路装置
US8263870B2 (en) * 2005-09-27 2012-09-11 Panasonic Corporation Heat dissipating wiring board, method for manufacturing same, and electric device using heat dissipating wiring board
JP2007250698A (ja) * 2006-03-14 2007-09-27 Furukawa Electric Co Ltd:The メタルコアプリント配線板の製造方法
TWI449137B (zh) * 2006-03-23 2014-08-11 Ceramtec Ag 構件或電路用的攜帶體
JP2013149947A (ja) 2011-12-19 2013-08-01 Shinko Electric Ind Co Ltd 発光素子搭載用パッケージ及び発光素子パッケージ並びにそれらの製造方法
DE102012206973B4 (de) * 2012-04-26 2021-02-18 Ledvance Gmbh Verfahren zum erzeugen von leiterbahnen und substrat
JP2014220304A (ja) * 2013-05-06 2014-11-20 株式会社デンソー 多層基板およびこれを用いた電子装置
CN104717848B (zh) * 2013-12-12 2017-12-12 深南电路有限公司 一种局部厚铜电路板的制作方法和局部厚铜电路板
JP2015159240A (ja) * 2014-02-25 2015-09-03 矢崎総業株式会社 フレキシブルフラット回路体
US9397017B2 (en) 2014-11-06 2016-07-19 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US11437304B2 (en) 2014-11-06 2022-09-06 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US9408301B2 (en) 2014-11-06 2016-08-02 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
CN105208789B (zh) * 2015-09-18 2018-05-11 深圳诚和电子实业有限公司 一种电池电路板的制作方法
CN112435972A (zh) * 2019-08-26 2021-03-02 珠海零边界集成电路有限公司 功率模块及其制备方法、电器设备
CN111148378B (zh) * 2020-01-09 2021-04-06 深圳市景旺电子股份有限公司 一种局部厚铜板的制作方法
WO2022162875A1 (ja) * 2021-01-29 2022-08-04 サンケン電気株式会社 半導体パワーモジュール
JP2024054433A (ja) * 2021-02-16 2024-04-17 株式会社フジクラ 配線板の製造方法、及び、フレキシブルプリント配線板
EP4273928A1 (en) * 2022-05-02 2023-11-08 Infineon Technologies AG A semiconductor package comprising power and logic on a single ceramic plate

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63260198A (ja) * 1987-04-17 1988-10-27 古河電気工業株式会社 多層回路板の製造方法
JP2664408B2 (ja) * 1988-04-18 1997-10-15 三洋電機株式会社 混成集積回路の製造方法
JPH0631734Y2 (ja) * 1988-10-13 1994-08-22 ローム株式会社 印刷配線基板
JP2715576B2 (ja) 1989-07-26 1998-02-18 松下電工株式会社 プリント配線板の製法
JPH07105461B2 (ja) * 1990-08-03 1995-11-13 三菱電機株式会社 半導体装置用絶縁基板の製造方法およびそのための金属パターン板
JP2772184B2 (ja) * 1991-11-07 1998-07-02 株式会社東芝 半導体装置
JP2698278B2 (ja) 1992-01-31 1998-01-19 三洋電機株式会社 混成集積回路装置
JPH06334311A (ja) 1993-05-18 1994-12-02 Yazaki Corp 回路体の製造方法
JP3231982B2 (ja) * 1995-10-30 2001-11-26 京セラ株式会社 配線基板及びその製造方法
US6222136B1 (en) * 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
JP2001177022A (ja) * 1999-12-17 2001-06-29 Matsushita Electric Ind Co Ltd 熱伝導基板とその製造方法
JP4172893B2 (ja) * 2000-01-11 2008-10-29 電気化学工業株式会社 金属ベース回路基板の製造方法
JP4411720B2 (ja) * 2000-02-02 2010-02-10 パナソニック株式会社 熱伝導基板とその製造方法
JP3752949B2 (ja) * 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
JP4459406B2 (ja) 2000-07-27 2010-04-28 ソニーケミカル＆インフォメーションデバイス株式会社 フレキシブル配線板製造方法
JP2002198619A (ja) * 2000-12-25 2002-07-12 Matsushita Electric Ind Co Ltd 回路基板
DE10205592B4 (de) 2002-02-11 2008-01-03 Ksg Leiterplatten Gmbh Verfahren zum Herstellen eines Halbzeugs für Leiterplatten

Also Published As

Publication number Publication date
CN1961422A (zh) 2007-05-09
JPWO2005081311A1 (ja) 2007-08-02
CN100527393C (zh) 2009-08-12
US20080106875A1 (en) 2008-05-08
TW200539758A (en) 2005-12-01
US7714232B2 (en) 2010-05-11
WO2005081311A1 (ja) 2005-09-01
JP4785139B2 (ja) 2011-10-05

Similar Documents

Publication Publication Date Title
TWI309962B (en) Circuit device and menufacturing method thereof
TW535462B (en) Electric circuit device and method for making the same
TWI248140B (en) Semiconductor device containing stacked semiconductor chips and manufacturing method thereof
TW501382B (en) Semiconductor device and process therefor
TW471149B (en) Semiconductor device, process for producing same, carrier substrate and process for producing same
TW567738B (en) Manufacturing method of circuit device and circuit device
TW533754B (en) Semiconductor device and semiconductor module
TW486920B (en) Electric circuit device and method for making the same
TW511422B (en) Method for manufacturing circuit device
TWI276211B (en) Board member and method for making semiconductor device
TW200541126A (en) Circuit device and manufacturing method of the same
TW200941688A (en) Semiconductor device and manufacturing method thereof
JP5115573B2 (ja) 接続用パッドの製造方法
JP4722836B2 (ja) 回路装置およびその製造方法
KR920001689A (ko) 반도체장치 및 그 제조방법
TW546715B (en) Hybrid integrated circuit device and manufacturing method therefor
TW511399B (en) Semiconductor device and its manufacture method
TW200828472A (en) Method for fabricating a circuit
KR100738134B1 (ko) 회로 장치의 제조 방법
TW200532750A (en) Circuit device and method for making same
TWI334182B (en) Method of fabricating chip package structure
TW200421947A (en) Circuit device and manufacturing method thereof
KR101582548B1 (ko) 인터포져 제조 방법 및 이를 이용한 반도체 패키지 제조 방법
JP3863816B2 (ja) 回路装置
JP3676197B2 (ja) 半導体装置および混成集積回路装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees