TWI303463B - Lead-free bump and formation method thereof - Google Patents

Lead-free bump and formation method thereof Download PDF

Info

Publication number
TWI303463B
TWI303463B TW092136995A TW92136995A TWI303463B TW I303463 B TWI303463 B TW I303463B TW 092136995 A TW092136995 A TW 092136995A TW 92136995 A TW92136995 A TW 92136995A TW I303463 B TWI303463 B TW I303463B
Authority
TW
Taiwan
Prior art keywords
alloy
lead
plating
bump
concentration
Prior art date
Application number
TW092136995A
Other languages
English (en)
Other versions
TW200421507A (en
Inventor
Masashi Shimoyama
Hiroshi Yokota
Rei Kiumi
Fumio Kuriyama
Nobutoshi Saito
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Publication of TW200421507A publication Critical patent/TW200421507A/zh
Application granted granted Critical
Publication of TWI303463B publication Critical patent/TWI303463B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C25D21/12—Process control or regulation
    • C25D21/14—Controlled addition of electrolyte components
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C25D3/60—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of tin
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
    • C25D5/505—After-treatment of electroplated surfaces by heat-treatment of electroplated tin coatings, e.g. by melting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01092—Uranium [U]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

1303463 玖、發明說明 [發明所屬之技術領域] 本發明係關於一種無斜凸塊（lead_free bump)及該凸塊 之形成方法，更詳而言之，係關於將經調整鍍膜Ag濃度 之Sn-Ag系焊錫（solder)合金鍍膜加以迴焊處理（refl〇w)所 製得之空隙（void)發生經抑制之無鉛凸塊及其形成方法， 以及形成該無鉛凸塊所用之電鍍裝置。 [先前技術] 半導體70件之表面封袈技術中，以優異信賴性進行銲 接乃非g重要。至目岫為止，由於廣泛使用含鉛之共晶銲 料（sn:Pb=63:37)作為銲料，而發生環境污染或由鉛所引起 α線之問題’ gj而目前正進行無錯輝料之開發。 例如目前正進行之印刷法或電鑛法之無麟料的研 :中，印刷法由於對應於金屬遮罩之細間距(fi—h)而 有其界限，因此例如晶圓 鍍法逐漸成為主流。鬼⑽〜^P)之形成使用電 為玫成晶圓凸塊時’—般會為了使形成之鑛膜成 ==而進行加熱處理(迴焊)。而為了避免對基板中 為佳 他機件造成熱損傷，該迴桿溫度以儘可能低溫 “人今Γ ’很多焊錫合金的開發’係從利用共晶點，不 限疋合金組成比只求接近共晶组成來考量。 =而’將電鍍法形成之凸塊進行 發生空隙的問題。特別是―系合全丄；凸=有 毛生革-，而使作為凸塊之信賴性降低。 315370 5 1303463 [發明内容] 由此，需要開發一種依據電鍍法而在迴焊後無空隙發 生之Sn-Ag系無鉛凸塊之形成方法，而本發明之目的即係 提供上述方法。 本發明人等以所得無空隙發生之無鉛凸塊進行檢 討，結果得知，由Sn_Ag系焊錫合金形成凸塊時，該鍍膜 中所έ之Ag〉辰度對空隙的發生有重大影響。更詳而言之， Sn_Ag系之無鉛&塊中所含之Ag濃度為接近Sn_Ag之共 晶組成比或更高時，在迴焊後之凸塊内會有空隙發生。因 此，更進一步進行研究，結果發現，凸塊中使用Sn-Ag系 焊錫合金膜時，為了確實防止凸塊内空隙之發生，凸塊形 成時必需使用較Sn-Ag之共晶組成比（重量比，
Sn:Ag = 96.5:3.5/Ag含量，3·5質量％)更低Ag濃度之合金 鍍膜。 此外’ Ag濃度較Sn-Ag之共晶組成比更低時，雖預 期迴焊溫度會上昇，然而發現即使降低Ag含有濃度也未 見熔點之大幅提昇，因此並無須大幅提高迴焊溫度。 本發明基於上述發現而完成，係藉由電鍍形成Ag含 量低於Sn-Ag共晶形成濃度之sn_Ag系合金膜，再將該合 金鍍膜迴焊而製得無鉛凸塊。 又本發明係提供無鉛凸塊之形成方法，其特徵係在要 形成凸塊之部份，於控制形成Ag含量低於Sn-Ag共晶形 成漢度之Sn-Ag系合金鍍膜的鍍浴組成及電沉積 (electrodeposition)條件而進行Sn_Ag系合金電鍍，其次將 6 315370 1303463 所得之該合金鍍膜迴焊。 此外本發明提供無鉛凸塊形成用電鍍裝置，其係具有 置入含有Ag離子及811離子之電鍍液之電鍍槽、陽極電 極、保持待處理物並供電至待處理物之支架、分別供電至 前述陽極電極及前述支架所保持之待處理物之電沉積用電 源、補充Ag離子及“離子之補充機構，偵測Ag離子及 Sn離子之分析裝置，以及根據前述分析裝置所得之分析資 料，而將前述待處理物之表面所形成之Sn_Ag系合金鍍膜 中之Ag含量控制為低於Sn-Ag共晶形成濃度用之控制機 構。 [實施方式] 本發明之無鉛凸塊係藉由控制Ag濃度使低於sn_Ag 共晶形成濃度含量（3.5質量％以下）之電沉積條件之Sn_Ag 系合金電鍍（下文中僅以「合金電鍍」稱之），而析出Sn_
Ag系合金鍍膜，再將該鍍膜進行迴焊而製得。 由防止空隙發生的觀點而言，雖僅將合金鍍膜中Ag 2之上限控制於上述濃度亦可，惟Ag濃度為2.6至3.5 質ΐ %之間時，可能會發生空隙，而亦可能不發生空隙， 因而意味若欲完全避免空隙則合金鍍膜中之α §濃度較佳 為2 · 6質量％以下。 由貫用性方面而言，希望無須提高迴焊溫度（例如，最 高迴焊溫度為24rc以下)。因此，合金鍍膜中Ag濃度之 下限較佳為u質量％。亦即，為形成實用性較佳的凸塊， 合金鍍膜中Ag濃度較佳為丨6至26質量％。 315370 7 1303463 由此，本發明之合金鍍膜中Ag濃度必須控制在3·5 質量°/。以下，較佳為1 6至2 6質量％以進行電鍍。 又，根據前述操作，將合金鍍膜迴焊所得之無鉛凸塊 自其表面所放出之“線放射量較佳為〇〇2cph/cm2以下。 鉛為多種含天然放射性元素之同位素。鉛之同位素系 為鈾及銼衰變系列中之中間生成物或最終生成物，而在衰 變過程中會放射出α線。α線會與半導體積體電路之半導 體元件作用而引起軟錯誤（softerr〇r)之問題。§11或其他元 素也含有些許該等天然放射性元素，為此’在Sn_Ag系無 鉛凸塊中也放射出^線，而降低其放射量甚為重要。因此， 將無鉛凸塊表面所放射出之α線放射量降低至〇 〇2 cph/cm以下，就能抑制半導體積體電路元件因“線之影響 所引起之軟錯誤。 一般而言合金電鍍中所析出之成分組成係依電鍍液 中各成分濃度或電沉積條件而決定。由此，本發明之合金 電鍍中可由調整合金電鍍液中Ag離子及Sn離子之濃度比 及控制電/儿積條件’而使合金鍍膜中Ag濃度成為上述範 圍。具體而言為（a)固定錢浴中Ag離子及Sn離子之濃度 比，改變電沉積條件而控制合金鍍膜中入§濃度之方法或， (b)固定電沉積條件，藉改變鍍浴中Ag離子及“離子之濃 度比即可控制合金鍍膜中之Ag濃度。 亦即口金鍍液中除配合有形成合金之金屬離子以 外，亦可配合安定金屬離子之配位劑《，在鍵膜形成美麗 表面之光澤劑’或其他添加劑。然而，合金錢膜中Μ濃 315370 8 1303463 Ϊ主要係由合金鑛浴中之Ag離子及Sn離子之濃度比而決 疋’由/驗找出較佳的範圍，且維持該濃度比而進行電鑛， :製付Ag ,辰度經控制之合金鍍膜。實際上，固定電沉積 =狀態下，進行合金電鏟時，合金鍍膜中之^濃度係 ° f 1圖杈式所示，與電鍍液中存在之Ag離子及Sn離子 之丨辰度比為比例關係。 由此’將待處理物浸潰於Ag離子及^離子為規定濃 度比之合金鍍液中，在固定的電沉積條件下，即可製得Ag 離子遭度經控制之合金㈣，將此鑛膜迴焊而得i 生之凸塊。 ....... 本月中所使用之合金鍍液之一例可列舉如下述之 鍵液。 組成：
Sn H^(Sn ) · 10 ^ 100 g/L ^ 35 ^ 5〇 g/L)
Ag離子（Ag + ): 〇.3至8g/L(較佳為以至 甲烷磺酸：1〇〇 g/L 金電鍍中，已知析出組成成分會隨電沉積條件 而異，本發明之合金電鍍亦可藉由改變電沉積條件，而改 變合金鍵膜中之Ag離子濃度。 本發明之合金電鍍可以多種電流形式進行，可連續地 施加直流電流電鍍而進行直流電鍍，亦可間歇地施加直流 電流電鍍*進行有週期性停歇期存在的間歇電鍍。 連、-貝地知加直流電流電鑛而進行直流電錄時，如第2 圖所示之模式’由於電流密度變高時合金鍍膜中之^含 315370 9 1303463 有濃度會降低，因而由實驗決定較佳的電流條件，於維持 該條件而電鍍亦可。該直流電鍍時之較佳電流密度為i〇、 至 100 mA/cm2 範圍。 ▲再者’間歇性地施加直流電流錢而進行存在有週期 性停歇期之間歇性電鍍時，如第3圖所示之模式，連續地 乜力直/’IL電之Jf况與間歇性地施加相同電流的情況下，、其 Ag含有濃度不相同’因而在該情況下’藉由實驗測定好 之施加電壓及停歇時間之比例等，且維持該條件而電錢亦 可。該間歇電鍍時’較佳之施加電流密度$ ι〇至 mA/Cm2範圍，停歇時間（零電流）為施加時間之"μ至 之範圍。 珂述兩種電鑛之施加電壓可依電流強度、基礎材料、 厚度、鍍液、陽極等條件而改變，較佳為4 Μ範圍。 作為實施前述合金電鍍之裝置，並無特別限制，一妒 ，浸潰_電鑛裝置等皆可使用。然而，實際作業時； 較佳係使用慮及待處理物夕她# k Μ 〜物之機械條件之治具構件、能將金 構r將子的迅速供給至晶圓等待處理物全面用之攪拌機 冓（木式構造）、使電場分布均—用之遮罩之形狀及大小、 取出異物、防止鑛液轡皙& 及欠貝旎均一且迅速的將金屬離子提 供給待處理物全面収㈣循環“等之裝置。 再者，根據前述，由於必須調整鑛液中之Ag離子戍 η離子Μ度或㈣t沉積條件而進行電鍍，較好使用具 ^ Ag料及Sn離子之補充機構離子及^ 離子之分析裝置及以得自前述分析裝置之分析資料，而調 315370 10 1303463 整合金錢液A ~ 之Ag離子或Sll離子之、、f 積條件用之控制機構之钱裝置。之展度及/或控制電沉 第4圖中’1為電錢裝置 # 4為支架、5為待處理物^'錄槽、3為陽極電極、
^至㈣補充機構、9為分Hi電源、7為導線、 為自動取樣器、12 10為控制機構、U 為排液口。 〜為送液幫浦、13為開關閥、14 八中作為電鍍控制指針之分权壯里〇〆 的運轉中定期i?、4钵ΛΛ Υ 刀析衣置9係在電鍍裝 思锝Τ疋期或連績的分析
AgM早》q月耗及才貝失而伴隨之 g離子及Sn離子之濃度變化 光分析裝置等。 妁如』使用原子 再者控制機構10，例如為 裝置9所尸夕八… 巧㈣用電腦，係根據由分; I罝y所付之分析貧料，炎 液）等之/ 出Ag離子（溶液）、Sn離子（; 促J寺之取適補充^，而運轉 液幫，、者17 5ι 連轉與補充機構83至8c連結之^ 繁浦12a至12c，對鐘液A 子(溶液)等。 [液中添加、離子(溶液)或_ 充Ag離子溶液或Sn 成也可追加水或添加 此外，補充機構8a至8c除了補 離子溶液之部份外，為了調整鍍液組 劑之補充部份。 /述陽極電極3、支架4及制2係使由電鍍裝置i 所形成之Sn-Ag合金㈣表面所放出之“線放射量低於 〇.〇2 cphW，而由降低α線放射量之材料所構成。由此， 降低由電鍍形成之合金鍍膜而得之凸塊中所摻人之前述天 然放射性元素，而降低由凸塊所放出之α線放射量而能 315370 11 1303463 抑制=半導體積體電路元件之α線影響所產生之軟錯誤。 陽柽電極3可為不溶解性陽極或溶解性陽極。使陽極 υ為不溶解性陽極時，不進行交換而能持續使用該電 又，陽極電極3使用溶解性電極時，使用錫陽極則陽 二可^給Sn離子至電鑛運轉之鑛液中，由此而能減少鑛 /文之官理或金屬離子補給作業。
”刖述匕制機構！ 〇 ’係希望針對鍍液組成控制最適合之 冰積條件（上述施加電壓密度及電壓施加方法），至少需 要持有控制前述Ag離子及Sn離子之補充量之任一者。 實際的電鍍析出動作不僅受前述合金鍍液中Ag離子 及Sn離子之濃度比或電沉積條件影響’也受多種重要因 素影響。例如，鍍液中所添加之多種添加劑，纟會改變合 …、中之Ag /辰度。然而多數情況下，該等添加劑之名 稱或添加量為添加劑製造商之技術知識(―)而未揭 由此，本發明之凸塊形成時，在固定的合金鍍液中， 必須預先在電鍍之電流密纟，電壓施加方；去，鑛〉夜中之Μ =子及Sn離子之濃度比進行實驗’測定形成之凸塊中所 含A g之重量濃度，據此而求出最適條件以進行合金電鍍。 若依此而行則除了可安定鍍液之組成，更能安定：形 成含有所欲Ag濃度之凸塊。 上述所形成之合金鍍膜接著進行迴焊處理而形成凸 塊。此迴焊處理可使用例如第5圖所示之裝置（紅外線加熱 爐）’在惰性氣體環境（例如氮氣或氬氣環境）中加熱進行。 315370 1303463 第5圖中，20表紅外線加熱爐、21表加熱室（心_叫、 22表平台（Stage)、23表石英玻璃窗、24表紅外線燈、25 表待處理物。 ^以此農置迴焊時，例如，在加熱室2 1中置入經合金 電，之待處理物25，以8至3〇 L/min範圍將氮氣流入加 …、至2 1中，軋體取代完全後，通過石英玻璃窗23，以紅 外線燈24進行加熱。 本發明之凸塊形成中，迴焊溫度甚重要。凸塊係在印 刷電路板等之卜$ # ^ 上 。、 上&成，而一般電子零件之耐熱溫度為240 c。為此，合金電鍍所形成之合金鍍膜之迴焊步驟之最高 溫度必需控制於2，c以下。再者，一般之^系焊料 熔點為22rC，而一般迴焊之可能最低溫度為熔點+1〇它， 且必需保持15秒至45秒。考慮該等條件時，迴焊之溫度 條件之示例可例舉有23rc保持3G秒，而最高到達溫度為 2 3 8 C之溫度條件。 以上所說明之本發明之無鉛凸塊，例如可利用作為封 衣基板中配線塾片（pad)上之球狀凸塊。 4^狀凸塊之形成係、，首先，形成金屬接合墊（bondPad) : 阻劑並保留凸塊之形狀，而形成阻劑圖案。接著， 法形成Ag濃度經控制之sn-Ag係合金鑛膜。之 上^阻劑，以設定之迴焊溫度進行處理。 阻叫ϋ:法中，金屬接合墊之形成，阻劑圖案之形成及 " 示可以該技術領域中所使用之-般方法進行。 再者，本發明之無錯凸塊，可使用於形成各種半導體 315370 13 1303463 基板上配線墊片。具體而言，能依據下列⑴至（ιν)之步驟， 而在半導體元件之半導體基板上形成無鉛凸塊。 (I) 半導體元件之半導體基板上形成配線墊片之步 驟。 (II) 所形成之配線墊片上形成阻障金屬（barrier metal) 之步驟。 (III) 阻障金屬上形成Sn-Ag鍍膜之步驟。 (IV) 將Sn-Ag系鍍膜迴焊之步驟。 上述（I)之半導體元件包含積體電路（IC)等。再者，配 線塾片中所形成（II)之阻障金屬，可使用習知之阻障金屬。 接著，將列舉實施例及比較例更詳細說明本發明，而 本發明並不因該等實施例而有所侷限。 實施例1 (l)Sn-Ag系之凸塊之製備·· 在晶圓上，將阻劑以12〇μιη的厚度塗布於多數個開口 徑為0 ΙΟΟμΓΠ的小孔作為試樣。該試樣之電鍍面積為汗口 149.63cm2。將該試樣依下列步驟及條件進行電鍍'。” (電鍍步驟） 脫氣（10分鐘卜卩10%硫酸前清洗（1分鐘）_銅電鑛 —水洗—Ni電鍍—水洗—Sn_Ag系合金電鍍 (電鍍條件） (a)Cu電鍍 鍍液組成：
Cu2+ 220 g/L 315370 14 1303463
H2so4 200 g/L HC1 5 mL/L 添加劑 5 mL/L
電鍍溫度：25°C 稅掉·機械稅样（槳式搜掉速度1〇 m/m in) 鍍液循環：流量2.5 L/min 電極：銅陽極，電極間距離約7.5mm，陽極遮罩φ 25 0mm 陰極電流密度（總電流）：5 A/dm2 (7·48Α) 電錢厚度：2 μιη (b)Ni電鍍 鑛液組成·
Ni(NH2S04).4H20 450 g/L
H3BO3 30 g/L
NiCl2-6H2〇 10 g/L 添加劑 2 mL/L 電鍍溫度：50t： 攪拌：機械攪拌（槳式攪拌速度10m/min) 鍍液循環：流量2.5 L/min 電極：鎳陽極，電極間距離約7.5mm，陽極遮罩0 25 0mm 陰極電流密度（總電流）：3 A/dm2 (4·49Α) 電鍍厚度：3 μιη (c)Sn-Ag 電鑛
鍍液組成： Sn2 + 40 g/L 315370 15 1303463
Ag2+ 甲烧續酸 添加劑 (聚氧乙烯系界 2 : 2 : 1 者）
1·5 g/L 100 g/L 10 g/L 面活性劑：硫尿素：鄰苯二酚之重量比為 電鍍溫度：2 5。(： 攪拌：機械攪拌（槳式攪拌速度lOm/min) 鍍液循環：流量2 5 L/min 電極·鈦陽極，電極間距離約7.5mm，陽極遮罩必25〇历爪 陰極電流役度（總電流p 1〇 A/dm2 (14·9Α)、直流電鍍 電錢厚度·· 140 μηι (2)迴焊處理 上述（1)之電鍍後，去除阻劑而露出電鍍部份。將此電 KM”使用第5圖所不之紅外線加熱爐進行迴焊處理。紅 外線加熱爐之溫度控制係藉由署 ^ ^ ^ _ ^丨尔稽由置放將中心最表層設有熱電 偶(thermocouple)之 2 英口+ 功曰冋 / a 士 , p ; 央才石夕晶圓（感應器（Sensor)公司所 製之晶圓溫度計）置於紅外绩力劫哈 r琛加熱爐之平台上而進行。再 者，迴焊試樣係置放於接近續欲曰m ^ ^ 、 受迎4矽日日圓上之熱電偶之位置。 迴焊溫度條件為，在1 5 〇至]7 〇。广猫 υ C預備加熱9〇秒後，以3〇 秒昇溫至最高溫度，最高溫度設為 厌叹马238 C，於迴焊可能最 低溫度之23 1°C以上保持3〇秒後冷卻者。 再者，該加熱爐之氣體環境係 衣兄係經虱氣取代，加熱時氮 氣也以8L/min流入而進杆。&从a ·
、、外線加熱爐因呈有容县I 加熱、急速冷卻的特徵而利用之。 /、 h 315370 16 1303463 (3 )凸塊之組成分析
Sn_Ag合金之元素組成比以下列方法加以評估。將該 凸塊埋入樹脂中，削成剖面加以研磨後，以電子探測微分 析法（Electron Probe Microanalysis·· ΕΡΜΑ)進行元素比對 (mapping)，對如第6Α圖及第6Β圖所示之剖面内約1〇μιη X ΙΟμπι之微小領域之3定點（i、c、r)進行Ag之定量分析， 而以其平均值作為Ag之含量。 再者，使用微螢光X設線分析裝置時，即使不削出剖 面，亦能測定大略之組成比，或者以酸溶解凸塊，而以感 應偶合電漿發攝光譜儀（Inductively Coupled Plasma Mass Spectrometer·· ICP_MS)進行晶圓内組成分布之分析。 (4) 凸塊形狀之確認 進行Sn-Ag合金電鍍後，將去除阻劑之電鍍部份及以 各種溫度迴焊後之凸塊形狀以掃描式電子顯微鏡（sem)觀 察。第7A圖為迴焊前凸塊之SEM照相圖，第7B圖為225 °C迴焊後之SEM照相圖，第7C圖為230。(：迴焊後之SEM 照相圖，第7D圖為23 8X：迴焊後之照相圖。 (5) 空隙之確認 以SEM觀察於迴焊溫度238t：迴焊後之凸塊之剖面形 狀。觀察係連同晶圓埋入樹脂中，削出剖面後加以研磨後 進行。其結果顯示，本實施例之Ag濃度為2·6質量％之入 金鍍膜（凸塊），係如第8圖所示之無空隙者，相對於此， Ag濃度為3.4質量％之合金鍍膜所形成之凸塊係如第9圖 所示有空隙發生'。 315370 17 1303463 實施例2 改k合金鑛液對總金屬之Ag比例，電鑛時之電流密 度，電流施加法而進行合金電鍍，再以2 3 8 °C迴焊。將所 製得之凸塊，與實施例1相同操作進行凸塊之Ag濃度、 形狀及空隙有無的檢視。其結果示於表1。 (表1) 鍍液 Ag/Sn(%) 4.3 4.4 4.4 4.3 4-3 1.3 1.31.3 2.2 2.2 4.1 3.1 3·1 3.1 3.2 3.2 2.3,?.3 電鍍條件 _ ^ t 電流畚4 電壓施加法 (A/dm1) 33203203820320320103320320
DC DC CHOP DC CHOP DC DC CHOP DC CHOP DC CHOP CHOP DC DC CHOP DC CHOP 凸塊含有知濃度 (重量％) 5.2 6·4 4.0 7.7 5.1 1.8 0.91.4 3.42.14.9 2.9 3.6 5.0 5.8 2.7 3.52.6 空隙 有(Χ)ίί(Ο) 238¾ 之球狀化
XXXXXOOOXOXOXXXXXO ooooooXXoooooooooo 由該結果可明白，凸塊（合金鍍膜）中之Ag含有量為 2·9%以下時，不會發生空隙，特別是Ag含量為1.8至2.6% 時’在最尚迴焊溫度238下球狀化且不會發生空隙，而 顯示製得實用性高之無鉛凸塊。 本發明之無鉛凸塊不會發生空隙，且即使不提高溫度 也會形成甚佳形狀之凸塊。再者，該凸塊不含鉛，所以不 會因放出α線而引起積體電路之錯誤動作或影響環境。 315370 18 1303463 因此本發明之無錯凸塊能廣泛的使用於半導體元件等 之表面封裝技術（SMT)，且由於無鉛，能進行具信賴性優 異之銲料。 [圖式簡單說明] 第1圖顯示合金鑛液中Ag離子及Sn離子之濃度比及 鍍膜中Ag含有濃度之關係圖。 第2圖顯示進行連續施加直流電鍍時，電流密度及艘 膜中Ag含有濃度之關係圖。 第3圖顯示進行連續施加直流電鍍時（連續直流電鑛） 及進行施加直流電鍍時（間歇電鍍），鍍膜中Ag含有濃度之 差異圖。 第4圖顯示本發明之電鑛裝置之一例。 第5圖顯示用於迴焊處理之紅外線加熱爐之一例。 第όA圖顯示實施例1進行Ag之定量分析時，其試料 迴焊前取樣部份之圖，第6B圖顯示實施例1進行Ag之定 量分析時，其試料迴焊後取樣部份之圖。 第7A圖顯示實施例1中迴焊前凸塊之SEM照相圖， 第7B圖顯示第7A圖所示凸塊於225^迴焊後之SEM照相 圖，第7C圖顯示第7A圖所示凸塊於23(rc迴焊後之§ΕΜ 照相圖，第7D圖顯示第7A圖所示凸塊於238。(：迴焊後之 SEM照相圖。 第8圖顯示Ag濃度為2·6質量％之Sn_Ag系合金鍍膜 於238°C迴焊後所形成凸塊之剖面之SEM照相圖。 第9圖顯示Ag濃度為3·4質量％之Sn_Ag系合金鍍膜 315370 19 1303463 於23 8°C迴焊後所形成凸塊之剖面之SEM照相圖。 1 電鍍裝置 2 電鍍槽 3 陽極電極 4 支架 5 待處理物 6 電沉積用電源 7 導線 8a 、 8b 、 8c 補充機構 9 分析裝置 10 控制機構 11 自動取樣器 12a、 12b、 12c 送液幫浦 13 開關閥 14 排液口 20 紅外線加熱爐 21 加熱室 22 平台 23 石英玻璃窗 24 紅外線燈 25 待處理物 20 315370

Claims (1)

1303463
第92136995號專利申請案 申請專利範圍修正本 (95年8月2曰） 1 · 一種無鉛凸塊，其係藉由電鍍形成Ag含量低於Ag 共晶形成濃度之Sn-Ag系合金膜，再將該合金鍍膜迴焊 而製得者。 2·如申請專利範圍第1項之無鉛凸塊，其中，Sn-Ag系合 金鍍膜中之Ag濃度為ι·6至2.6質量0/〇。 3·如申請專利範圍第1項之無錯凸塊，其中，前述合金錢 膜迴焊時之最高溫度係240°C以下。 士申明專利範圍帛1項之無鉛凸塊，&中，藉由電鍍形 成該Sn-Ag系合金膜時，係控制鍍浴組成及電沉積條 件，而調整該合金鍍膜所含之Ag濃度使之低於 共晶形成濃度。 5. 如申請專利範圍帛i項之無鉛凸塊，其中，由表面放出 之《線放射量低於〇·02 cpix/cm2。 6. ^種無錯凸塊之形成方法，其特徵為：在要形成凸塊之 部份’控制鍍浴組成及電沉積條件而形成Ag含量低於 Sn-Ag共晶形成濃度之Sn_Ag系合金鍍膜之下，進行 = :Ag系合金電鍍，然後將所得之該合金鍍膜加以： 7’如申請專利範圍第6項之無鉛凸塊之形成方法，其中， $ Sn_Ag系合金鑛膜中之Ag濃度為16至26質量％。， •如申請專利範圍第7項之無鉛凸塊之形成方法，其中， 315370修正版 1
3修捷)正替換頁 耵述合金鍍膜迴焊時之最高溫度為24(rc以下 9.二申:"利範圍第6項之無錯凸塊之形: 组成及電沉積條件的控制係藉由固定鍍浴中其A中， 離子之濃度比，改變電沉積條件而、離 申請專利範圍第6項之無錯凸塊之形成方法，龙 ，成及電沉積條件之控制係藉由 ：中， u二改變鑛浴中Ag離…離子之濃度比而二積條 種無鉛凸塊形成用電鍍襞置，其係具有· 丁 置入含有Ag離子及Sn離子之電鍍液 陽極電極， 电戮槽’ 保持待處理物及供電至待處理物之支架， 分別供電至前述陽極電極及前述支架所 處理物之電沉積用電源， 、待 補充Ag離子及Sn離子之補充機構， 偵測Ag離子及Sn離子之分析裝置，以及 根據來自前述分析裝置之分析資料，而將 理物之表面所形成之Sn_Ag系合金鑛膜中之^含量二 制在低於Sn-Ag之共晶形成濃度之控制機構。 ' U·如申請專利範圍第U項之無鉛凸塊形成用電鍍裝置， 其中，控制Sn-Ag系合金鍍膜中Ag含量使之為丄6 2.6質量％。 …·至 13·如申請專利範圍第u項之無鉛凸塊形成用電鍍裝置， 其中Sn-Ag系合金鍍膜中Ag含量之控制，係藉由調餐 前述鍍液中Ag離子及Sn離子之濃度及改變電沉積伯 315370修正版 2 件而進行。 如申明專利|(!圍第1 i項之無鉛凸塊形成用電鍍裝置， 其中，由Sn-Ag系合金鍍膜表面所放出之α線放射量為 〇·〇2 cph/em以下，且前述陽極電極、支架及電鍍槽係 由降低α線放射量之材料所構成者。 15·如申清專利範圍第u項之無鉛凸塊形成用電鍍裝置， 其中，前述陽極電極為不溶解性陽極。 16. 如申清專利範圍第u項之無鉛凸塊形成用電鍍裝置， 其中’前述陽極電極為溶解性陽極。 17. 如申請專利範圍第16項之無鉛凸塊形成用電鍍裝置， 其中’前述陽極電極為Sn陽極。 3 315370修正版
TW092136995A 2002-12-26 2003-12-26 Lead-free bump and formation method thereof TWI303463B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002378010 2002-12-26

Publications (2)

Publication Number Publication Date
TW200421507A TW200421507A (en) 2004-10-16
TWI303463B true TWI303463B (en) 2008-11-21

Family

ID=32677413

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092136995A TWI303463B (en) 2002-12-26 2003-12-26 Lead-free bump and formation method thereof

Country Status (7)

Country Link
US (2) US7012333B2 (zh)
EP (1) EP1598448A4 (zh)
JP (1) JP4425799B2 (zh)
KR (1) KR101076819B1 (zh)
CN (1) CN1732291B (zh)
TW (1) TWI303463B (zh)
WO (1) WO2004059042A1 (zh)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7012333B2 (en) * 2002-12-26 2006-03-14 Ebara Corporation Lead free bump and method of forming the same
ES2422455T3 (es) 2005-08-12 2013-09-11 Modumetal Llc Materiales compuestos modulados de manera composicional y métodos para fabricar los mismos
US7713859B2 (en) * 2005-08-15 2010-05-11 Enthone Inc. Tin-silver solder bumping in electronics manufacture
TW200804629A (en) * 2006-07-05 2008-01-16 Idx Corp Power supply for anodizing
US8177945B2 (en) * 2007-01-26 2012-05-15 International Business Machines Corporation Multi-anode system for uniform plating of alloys
EP2310557A2 (en) 2008-07-07 2011-04-20 Modumetal, LLC Property modulated materials and methods of making the same
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
JP5311656B2 (ja) * 2008-12-27 2013-10-09 京セラＳｌｃテクノロジー株式会社 配線基板
EA201792049A1 (ru) 2009-06-08 2018-05-31 Модьюметал, Инк. Электроосажденные наноламинатные покрытия и оболочки для защиты от коррозии
US8377816B2 (en) * 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
EP2596150B1 (en) 2010-07-22 2020-06-17 Modumetal, Inc. Material and process for electrochemical deposition of nanolaminated brass alloys
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
US20120325671A2 (en) * 2010-12-17 2012-12-27 Tel Nexx, Inc. Electroplated lead-free bump deposition
US9005409B2 (en) 2011-04-14 2015-04-14 Tel Nexx, Inc. Electro chemical deposition and replenishment apparatus
US9017528B2 (en) 2011-04-14 2015-04-28 Tel Nexx, Inc. Electro chemical deposition and replenishment apparatus
JP5876767B2 (ja) * 2012-05-15 2016-03-02 株式会社荏原製作所 めっき装置及びめっき液管理方法
WO2014146114A1 (en) 2013-03-15 2014-09-18 Modumetal, Inc. Nanolaminate coatings
CN110273167A (zh) 2013-03-15 2019-09-24 莫杜美拓有限公司 通过添加制造工艺制备的制品的电沉积的组合物和纳米层压合金
EA201500949A1 (ru) 2013-03-15 2016-02-29 Модьюметл, Инк. Способ формирования многослойного покрытия, покрытие, сформированное вышеуказанным способом, и многослойное покрытие
WO2014146117A2 (en) 2013-03-15 2014-09-18 Modumetal, Inc. A method and apparatus for continuously applying nanolaminate metal coatings
US9303329B2 (en) 2013-11-11 2016-04-05 Tel Nexx, Inc. Electrochemical deposition apparatus with remote catholyte fluid management
US8877630B1 (en) * 2013-11-12 2014-11-04 Chipmos Technologies Inc. Semiconductor structure having a silver alloy bump body and manufacturing method thereof
US9368340B2 (en) * 2014-06-02 2016-06-14 Lam Research Corporation Metallization of the wafer edge for optimized electroplating performance on resistive substrates
AR102068A1 (es) 2014-09-18 2017-02-01 Modumetal Inc Métodos de preparación de artículos por electrodeposición y procesos de fabricación aditiva
CN106795645B (zh) 2014-09-18 2020-03-27 莫杜美拓有限公司 用于连续施加纳米层压金属涂层的方法和装置
CN105256347B (zh) * 2015-11-17 2018-01-16 通富微电子股份有限公司 锡银凸块含银量控制方法
JP6713809B2 (ja) * 2016-03-31 2020-06-24 株式会社荏原製作所 基板の製造方法及び基板
EA201990655A1 (ru) 2016-09-08 2019-09-30 Модьюметал, Инк. Способы получения многослойных покрытий на заготовках и выполненные ими изделия
JP7051823B2 (ja) 2016-09-14 2022-04-11 モジュメタル インコーポレイテッド 高信頼性、高スループットの複素電界生成のためのシステム、およびそれにより皮膜を生成するための方法
EP3535118A1 (en) 2016-11-02 2019-09-11 Modumetal, Inc. Topology optimized high interface packing structures
EP3601641A1 (en) 2017-03-24 2020-02-05 Modumetal, Inc. Lift plungers with electrodeposited coatings, and systems and methods for producing the same
CN110770372B (zh) 2017-04-21 2022-10-11 莫杜美拓有限公司 具有电沉积涂层的管状制品及其生产系统和方法
US20200303748A1 (en) * 2017-04-24 2020-09-24 University Of North Texas Nanomanufacturing of metallic glasses for energy conversion and storage
WO2019210264A1 (en) 2018-04-27 2019-10-31 Modumetal, Inc. Apparatuses, systems, and methods for producing a plurality of articles with nanolaminated coatings using rotation
JP2020111796A (ja) * 2019-01-11 2020-07-27 Ｊｘ金属株式会社 表面処理金属材料、表面処理金属材料の製造方法、及び、電子部品
JP7484865B2 (ja) * 2021-10-14 2024-05-16 トヨタ自動車株式会社 金属皮膜の成膜装置および金属皮膜の成膜方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3645955B2 (ja) * 1995-12-19 2005-05-11 ディップソール株式会社 錫−銀合金酸性めっき浴
DE69720435T2 (de) * 1996-01-30 2004-01-08 Naganoken Beschichtungslösung für Zinn-Silber-Legierungen und Verfahren zur Beschichtung mit dieser Lösung
JP3545549B2 (ja) * 1996-09-26 2004-07-21 株式会社大和化成研究所 電気・電子回路部品
JPH10102277A (ja) * 1996-10-01 1998-04-21 Daiwa Kasei Kenkyusho:Kk 光沢錫−銀合金電気めっき浴
US6099713A (en) * 1996-11-25 2000-08-08 C. Uyemura & Co., Ltd. Tin-silver alloy electroplating bath and tin-silver alloy electroplating process
JP3301707B2 (ja) * 1997-01-20 2002-07-15 ディップソール株式会社 錫−銀合金酸性電気めっき浴
JP2000094181A (ja) * 1998-09-24 2000-04-04 Sony Corp はんだ合金組成物
JP3632499B2 (ja) 1999-05-19 2005-03-23 ユケン工業株式会社 錫−銀系合金電気めっき浴
JP3753168B2 (ja) * 1999-08-20 2006-03-08 千住金属工業株式会社 微小チップ部品接合用ソルダペースト
JP2001237259A (ja) * 2000-02-22 2001-08-31 Fujitsu Ltd ハンダ合金、回路基板、半導体装置及びその製造方法
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
KR100398716B1 (ko) * 2000-06-12 2003-09-19 가부시키가이샤 히타치세이사쿠쇼 반도체 모듈 및 반도체 장치를 접속한 회로 기판
JP3866503B2 (ja) * 2000-10-18 2007-01-10 株式会社東芝 半導体装置
JP3649116B2 (ja) * 2000-11-22 2005-05-18 松下電器産業株式会社 半田バンプの形成方法
TW471146B (en) * 2000-12-29 2002-01-01 Apack Technologies Inc Bump fabrication method
JP4152596B2 (ja) * 2001-02-09 2008-09-17 新日鉄マテリアルズ株式会社 ハンダ合金、ハンダボール及びハンダバンプを有する電子部材
JP3801893B2 (ja) * 2001-09-26 2006-07-26 株式会社東芝 部材の接合方法
US7012333B2 (en) * 2002-12-26 2006-03-14 Ebara Corporation Lead free bump and method of forming the same

Also Published As

Publication number Publication date
EP1598448A4 (en) 2007-03-07
CN1732291A (zh) 2006-02-08
KR20050084312A (ko) 2005-08-26
US20050279640A1 (en) 2005-12-22
KR101076819B1 (ko) 2011-10-25
US20040219775A1 (en) 2004-11-04
CN1732291B (zh) 2010-10-13
JP4425799B2 (ja) 2010-03-03
US7012333B2 (en) 2006-03-14
WO2004059042A1 (ja) 2004-07-15
EP1598448A1 (en) 2005-11-23
JPWO2004059042A1 (ja) 2006-04-27
TW200421507A (en) 2004-10-16

Similar Documents

Publication Publication Date Title
TWI303463B (en) Lead-free bump and formation method thereof
JP4758614B2 (ja) 電気めっき組成物および方法
TWI579415B (zh) 無鉛錫合金電鍍組成物及方法
EP3004429B1 (en) Electroplating baths of silver and tin alloys
JP6121090B2 (ja) Ｓｎ合金めっき液へのＳｎ成分補給用酸化第一錫粉末の製造方法及び該方法により製造された酸化第一錫粉末
JP4536781B2 (ja) 無電解ニッケルめっき液
JP2006009039A (ja) ウィスカー成長が抑制されたスズ系めっき皮膜及びその形成方法
US5759379A (en) Solder method
Njuki et al. Enhanced voiding in Cu-Sn micro joints
JP2021048391A (ja) Ｓｎ−Ｂｉ−Ｉｎ系低融点接合部材および、その製造方法、ならびに半導体電子回路およびその実装方法
US5783059A (en) Electrodeposition bath
Njuki et al. All-electrochemical synthesis of SnBi/SnAgCu structures for low-temperature formation of high-reliability solder microjoints
JP3895638B2 (ja) すず−銀−銅はんだ合金の形成方法並びに当該合金を使用する鉛フリーバンプおよび半導体素子の製造方法
Njuki A Study of Reliability Issues in Alternative Fine Pitch Solder Joint Interconnect Technology for System-In-Packages (SIPS)
Shang et al. Preparation and soldering performance of SAC305@ Sn-bi Core-shell solder balls based on eutectic co-deposition
Ohtani et al. Non-cyanide electroless gold plating using polyphenols as reducing agents
EP4209607A1 (en) Low melting-point bonding member, method for producing same, semiconductor electronic circuit, and method for mounting said semiconductor electronic circuit
JP2003105581A (ja) スズ合金の電解析出方法及び装置
Pietriková et al. Microstructure of solder joints and isothermal aging
JP2815401B2 (ja) 浸漬はんだめつき浴
JP2000280066A (ja) 非鉛系接合部材の形成方法
Kim et al. The Stability of Plating Solution and the Current Density Characteristics of the Sn-Ag Plating for the Wafer Bumping
JP2008240018A (ja) すずメッキ皮膜およびウィスカー防止方法
JP2022043722A (ja) Ｓｎ－Ｉｎ系低融点接合部材およびその製造方法ならびに半導体電子回路およびその実装方法

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent