TWI297550B - Process for producing doped semiconductor wafers from silicon, and the semiconductor wafers - Google Patents

Process for producing doped semiconductor wafers from silicon, and the semiconductor wafers Download PDF

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TWI297550B
TWI297550B TW094127231A TW94127231A TWI297550B TW I297550 B TWI297550 B TW I297550B TW 094127231 A TW094127231 A TW 094127231A TW 94127231 A TW94127231 A TW 94127231A TW I297550 B TWI297550 B TW I297550B
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mohmcm
dopant
single crystal
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Krautbauer Rupert
Frey Christoph
Zitzelsberger Simon
Lehmann Lothar
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Siltronic Ag
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    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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Description

1297550 九、發明說明: 【發明所屬之技術領域】 本發明係關於-種由石夕製造經摻雜半導體晶圓之方法,其含有 電活性摻質,例如:,若適合另外摻以鍺^有 特定之導熱性。本發明亦關於由㈣成之半導體晶圓,其係推以 濃度高達2*102。個原子/立方公分之鍺及電活性推質,域等半導 體晶圓具有與導熱性(TC)及電阻係雖)有關之特殊性質。 【先前技術】 '
作為電子元件之基材(基片),若半導體晶圓儘量具有特定物 理性質,基本上係有利的。理想的是,基片在—晶圓内之所有主 要參數及具有同樣規範之不同晶圓間應僅具有些微之起伏。基片 導熱性係-關鍵性性質,對電子元件組裝之加工配置及最終成品 之f生貝極為重要。舉例言之,切所製半導體晶圓之導熱性對加 工製造電子元件期間晶圓性f之蚊及成品元件用途之可能範圍 扮演一關鍵㈣色。因此,裝配元件極需要-具有完善界定及均 勻之導熱性的基片。 但:由⑪所製半導體晶圓之導熱性,其量私雜為複雜而』 成本昂貴’因此在標準製程中不量測此參數。導熱性係由一聲名 成/刀及-f子成分所組成。在t溫下該二者對單晶歡貢獻極肩 導,’、、f生之f子成分實質上與基片之導電性成正比,而聲名 成分則與於固態原子質量之分佈有關。如所知者,純同位素石夕之 導熱f特別高’但摻雜元素會降低導執性。 【發明内容】 … 本發明之目的係提供—财法,該方法可㈣製造半導體晶s 5 1297550 ,該等晶圓具有預定之導熱性。 藉一種由矽製造經摻雜半導體晶圓之方法可達到此目的,該等 摻雜半導體晶圓含有電活性摻質,例如:硼、磷、砷或銻,若合 適另外摻以鍺且具有特定之導熱性,其中單晶體係由矽製得旅再 進一步加工形成半導體晶圓,其導熱性係藉選擇電活性摻質之濃 度及(若適合)藉助於鍺之濃度而設定。 【實施方式】
本申請案之諸發明人已發現:對已摻有電活性摻質(例如:确 、磷、砷或銻)之矽而言,導熱性係一固定界定之物理性質真係 由下式說明 k= l/(6.8*10-3+alpha*c(Dot)) (1) 其精確度為數個百分點,於該式中,在22°C溫度下導熱性之單 位為W/mK,c(Dot)係電活性摻質之經選定之濃度且單位為原子/ 立方公分,alpha係一係數,視電活性摻質而定,具有下列諸值: 摻質: 硼 磷 砷 銻 alpha : 9·57*1(Τ23 6·42*1(Γ23 2·11*1(Γ22 1·30*1(Γ21 〇 若希望將導熱性之值設定在不含在式(1)所預定諸值之範園内時 ,可藉另外摻以濃度高達2*1020個原子/立方公分之鍺以擴展諸值 之範圍,尤其可達到目前尚未接近之諸區域内。在此等情況下’ 藉選擇鍺之濃度及電活性摻質之濃度,導熱性係依照下式設定 k=(l-5.6*l〇-21*c(Ge)+l,4*Hr41*c(Ge)2)/(6.8*l(T3+alpha*c(Dot))(2) 其中,k係22。(:溫度下之導熱性且其單位為W/mK,c(Ge)及c(Dot) 係鍺及電活性摻質之經選擇之濃度,其單位為原子/立方公分’及 6 1297550 alpha係一係數,端視電活性摻質而具有下列數值: 摻質:硼 磷 砷 銻 alpha : 9·57*1(Τ23 6·42*1(Γ23 2·11*10·22 1·30*1(Γ21 〇 本發明亦關於一種由石夕製成之半導體晶圓,若適合具有經沉積 之磊晶塗層,該晶圓係摻以濃度高達2*102G個原子/立方公分之鍺 及摻以硼,且具有以下與導熱性(TC)及電阻係數(R)有關之性質組 合中之一種: a) TC< 105 W/mK ; R>5 mOhmcm b) TC= 90 W/mK — 30 W/mK ; R = 5 — 3 mOhmcm c) TC=80 W/mK-20 W/mK ; R=3-2 mOhmcm d) TC=70 W/mK-20 W/mK ; R=2- 1.5 mOhmcm e) TC < 50 W/mK ; R< 1.5 mOhmcm o 此外,本發明亦關於由矽所製半導體晶圓,若適當具有一沉積 之蠢晶層’該晶圓係換以濃度南達2 * 1 〇20個原子/立方公分之鍺及 摻以磷,且具有以下與導熱性(TC)及電阻係數(R)有關之性能組合
a) TC=90 W/mK-50 W/mK; R= 1.5-1.2 mOhmcm b) TC=80 W/mK-40 W/mK ; R= 1.2-0.9 mOhmcm c) TC=75 W/mK—30 W/mK ; ΪΙ<〇·9 m0hmcm 0 若業已使用鍺作為摻質’無論如何由於其可達成其諸效果及在 若干情況下認為導熱性低於依照式(1)選擇電摻質之特定濃度後將 達成之導熱性’摻以鍺及電活性摻質則特別合適。在諸如 US-5,553,556、US-5,744,396、US-4,631,231、P-2003160395 A及 1297550 JP-2003146795 A中均曾述及,作 作為摻質,鍺之其他效果特別可增 高機械強度及加強晶格應力< 早明則m對導熱性僅具有相對低影響之其他摻質 ,例如:與氮及/或碳具有共同_作用之形式者。 、 該電活性摻質可先包含在單體製造期間之雜體内,其中,該 早晶體較佳係用左科拉斯基法抽拉。但,亦可在稍後之步驟内 =擴散作用或離子植入僅將電活性捧質引入已自單晶體分開 半¥體晶圓内。較佳地’鍺係與融溶體—起提供。 此外 之
原則上,由左科拉斯基法抽拉之石夕單晶體内捧質之轴向分佈係 取決於對應摻質之偏折常數。但,亦如眾㈣知者,單體内㈣ 向及軸向分佈亦可被影響。最重要之影響因素包含拉晶期間 早晶體及㈣之轉動方向及轉動速率,以及壓力條件及遮蔽氣體 之流速。藉適當選擇該等參數,可製得摻f含量在徑向及轴向變 化均低之早晶體。舉例言之,藉適當地選擇壓力條件,可透過控 制石申、錄«自㈣熔體蒸發出去之作用,俾使單晶體内電阻係 數之軸向及徑向變化僅為數個百分點。所以,連同本發明之方法 ’:見所選參數歧,亦可製得具有㈣衫之導熱性軸向分佈及 ^刀單晶體係均句之導熱性的單晶體。藉助於精確界定導熱性 ’可減低加工期間及產品性能之不合意變動。 用硼作為電活性摻質,特佳係利用本發明之方法,在該方法中 ,產生與半導體晶圓之導熱性(TC)及電阻係數(11)有關之下列性質 級合中之一種: a) TC< 105 W/mK ; R>5 mOhmcm 1297550 b) TC=90 W/mK-30 W/mK ; R=5-3 mOhmcm c) TC=80 W/mK-20 W/mK ; R=3-2 mOhmcm d) TC=70 W/mK-20 W/mK ; R=2- 1.5 mOhmcm e) TC< 50 W/mK ; R< 1·5 mOhmcm。 在此情況下,電阻係數之徑向變動較佳係低於8%。 用磷作為電活性摻質,特佳係利用本發明之方法,在該方法中 ,產生與半導體晶圓之導熱性(T C)及電阻係數(R)有關之下列性能 組合中之一種:
a) TC=90 W/mK-50 W/mK ; R= 1.5-1.2 mOhmcm b) TC=80 W/mK-40 W/mK ; R= 1.2-0.9 mOhmcm c) TC= 75 W/mK — 30 W/mK ; R<0,9 mOhmcm。 在此情況下,電阻係數之徑向變動較佳係低於10%。 實施例: (磷摻雜) 連續實線所表示者為:摻磷之矽單晶體導熱性分佈係應用式(1) 時所預測之摻質濃度之函數。諸量測點所顯示者為:對利用本發 明式(2)製造之矽單晶體不同樣品所測得之導熱性。 9 1297550
【圖式簡單說明】 (本申請案無圖式)

Claims (1)

1297550 十、申請專利範圍: 1· 一種由矽製造具有導熱性k之經摻雜半導體晶圓之方法,含有 電活性摻質,並進一步摻雜濃度高達2xl02G原子/立方公分之 鍺,該方法包括由矽製造單晶體,及進一步加工該單晶體形成 半導體晶圓,並依下式設定導熱性k
其係藉選擇鍺及電活性摻質之濃度,其中式k為在22°C且單位 為W/mK之導熱性,c(Ge)與c(Dot)分別為鍺及電活性摻質之經 選定濃度且單位為原子/立方公分,且alpha為視電活性摻質而 定且有下述值之係數: 摻質:爛 磷 砷 銻 alpha : 9.57*10'23 6.42*10'23 2.1 1 *1(Τ22 1·30*1(Γ21。 2·如請求項1之方法,其中利用左科拉斯基法將該單晶體自含有 電活性摻質及鍺之矽熔融體拉出,量測該單晶體内電活性摻質 之濃度c(Dop)及鍺之濃度c(Ge)。 3·如請求項1之方法,其中利用左科拉斯基法將該單晶體自含有 鍺之矽熔融體拉出,量測鍺之濃度c(Ge),將該單晶體加工成 批式晶圓,利用擴散作用或雜子植入法將該晶圓推以電活性換 貝用足夠數目之晶圓量測濃度c(D〇p)以證實該批晶圓中電活 性摻質之濃度。 4·如叫求項1之方法,其中蝴為電活性摻質,且侧濃度以產生與 半導體晶圓之導熱率(TC)與電阻係數(R)有關之下列性質組合 1297550 之一種的方式加以選擇: a) TC< 105 W/mK ; R>5 mOhmcm b) TC = 90 W/mK-30 W/mK ; R二 5 —3 mOhmcm c) TC=80 W/mK-20 W/mK ; R=3-2 mOhmcm d) TC = 70 W/mK-20 W/mK ; R=2- 1.5 mOhmcm e) TC< 50 W/mK ; R< 1,5 mOhmcm。 5. 如請求項4之方法,其中該電阻係數之徑向變化量低於8%。
6. 如請求項1之方法,其中該半導體晶圓摻雜磷作為電活性摻 質,磷濃度以產生與半導體晶圓之導熱性(TC)與電阻係數(R) 有關之下列性質組合之一種的方式加以選擇: a) TC=90 W/mK-50 W/mK ; R= 1.5- 1.2 mOhmcm b) TC=80 W/mK-40 W/mK ; R= 1.2-0.9 mOhmcm c) TC = 75 W/mK-30 W/mK ; R< 0.9 mOhmcm。 7, 如請求項6之方法,其中該電阻係數之徑向變化量低於10%。 8. 如請求項1之方法,其中該半導體晶圓係用作電子功率半導體 元件之基板。 9. 如請求項1之方法,其中該半導體晶圓上係沉積一磊晶層。 10. 如請求項1之方法,其中該單晶體另外摻雜至少一種其他摻質。 11. 如請求項1之方法,其中該單晶體另外摻雜氮、碳、或氮與碳 之組合。 12
TW094127231A 2004-08-12 2005-08-10 Process for producing doped semiconductor wafers from silicon, and the semiconductor wafers TWI297550B (en)

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JP4516096B2 (ja) 2007-05-31 2010-08-04 Sumco Techxiv株式会社 シリコン単結晶の製造方法
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