TWI281238B - Thermal enhanced package for block mold assembly - Google Patents

Thermal enhanced package for block mold assembly Download PDF

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Publication number
TWI281238B
TWI281238B TW092127066A TW92127066A TWI281238B TW I281238 B TWI281238 B TW I281238B TW 092127066 A TW092127066 A TW 092127066A TW 92127066 A TW92127066 A TW 92127066A TW I281238 B TWI281238 B TW I281238B
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TW
Taiwan
Prior art keywords
substrate
heat sink
package
die
molding compound
Prior art date
Application number
TW092127066A
Other languages
English (en)
Other versions
TW200416982A (en
Inventor
Daniel K Lau
Edward L T Law
Original Assignee
Advanced Interconnect Tech Ltd
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Publication date
Application filed by Advanced Interconnect Tech Ltd filed Critical Advanced Interconnect Tech Ltd
Publication of TW200416982A publication Critical patent/TW200416982A/zh
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Publication of TWI281238B publication Critical patent/TWI281238B/zh

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

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1281238 玖、發明說明： 【發明所屬之技術領域】 本專利申請案於年9㈣日巾請之美國臨時專利申 請案號6G/415，189之權益，該專利中請案以提及方式完整併 入本文。 本發明係關於半導體裝置封裝。更特定言之，本發明係 關於熱增強模製塑膠半導體裝置封裝。 【先前技術】 模製塑膠封裝為積體電路裝置（晶粒）提供環境保護。該等 封裝-般包括至少-個半導體裝置（晶粒），其輸入/輸出 加_/〇卿ut ; 1/0)焊塾電性連接至錯框架型基板或插入型 基板，而晶粒及基板之至少—部分具有模製化合物塗層。 -般，晶粒上的而焊塾係使用打線焊接、卷帶焊接或覆晶 焊接方法電性焊接至基板上之焊接點。錯框架或插入基板 在I/O焊墊與封裝外之電性電路之間傳輸電性信號。 在具有錯框架型基板的半導體裝置封裝中，電性信號係 在至少-個晶粒與外部電路如印刷電路板之間藉由導電鉛 框架傳輸。鉛框架包括複數個引線，各具有一内引線端及 一相對外引線端。内引線端係電性連接至晶粒上的ι/〇焊 墊，且外引線端為連接至外部電路提供端子。若外引線端 終止於封裝體表面，則該封裝稱為「無引線」或「㈣線而」 封裝。廣為人知之益引績射往 μ 線封裴之粑例包括四方扁平無引線 (quad flat no-lead ; 抖驻，甘曰士 W⑴封裝，其具有四組引線位於方形封 裝主體底部的周邊，以及雙爲平無引線咖心心。如d;
O:\88\88354.DOC 1281238
部的相對側置 在具有插入型基板的半導體裝置
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•置封裝中，電性信號係藉 咖y ; lga)封裝、細球袼栅陣列（fine _㈣阶叮； fbga)封裝、彈性球袼柵陣列（flexiMe㈤丨的d訂叫； ^BGA)封裝及要求封裝上的焊盤以合適電路板附著間距 (「格柵陣列」）排列之任何其他類型的封裝。焊球、焊凸塊 或針腳可位於焊盤上，與BGA及PGA型封裝的情形一樣， 以便於連接至電路板。 在任何類型的模製塑膠封裝中，晶粒運作產生的熱必須 移除以保持其運作完好。雖然封裝之金屬組件如基板與焊 線之部分會散發某些熱量’但其餘熱量會吸收入模製化合 物内。問題在於，模製化合物係不良熱導體。因此，有人 已經試圖改進模製塑膠封裝之散熱性能。 提而模製塑膠封裝散熱性能之一方法為在封裝内安置金 屬散熱器。在一普通設計中，金屬散熱器係置於晶粒之下。 例如’均頒發給Mahulikar等人的美國專利5,367，196與 5,608,267號及頒發給parthasarathi的美國專利5,650,663提 供了該等散熱器設計之範例，二者均經引用完整併入本文。
O:\88\88354.DOC 1281238 在另一普通設計中，金屬散熱器係置於晶粒之上，因而 晶粒係位於散熱器與基板之間。在該設計中，散熱器一般 包括接觸基板、晶粒或二者的向下部分。向下部分可用介 電黏合劑黏附於基板及/或晶粒。該等散熱器一般透過在封 裝材料上大於晶片的一面積散熱。頒發給Guan等人的美國 專利6,432,742號提供了該種散熱器之_範例。頒發給^吨 等人的美國專利5,977,626號提供了該種散熱器之另一範 例。不幸的是，使用該類散熱器之封裝的製造方法尚未達 到組裝低成本模製塑膠封裝所需要的高度自動化水準。 _ 頒發給Libres的美國專利6,432,749號（，749專利）提供了自 動化模製塑膠封裝組裝之嘗試，該專利經引用整體併入本 文。’749專利說明之製造方法以帶形式提供散熱器，從而可 同時組裝複數個封裝。散熱器帶置於晶粒及基板上，模製 化a物沈積於散熱裔、晶粒及基板上，從而封裝材料的邊 緣與連接鄰接散熱器之縮短斷面柱對齊。然後，切斷縮短 _面柱以分離各封裝。若基板為鉛框架，，749專利教導使用 防止電性短路的非導電黏合劑將散熱器黏附在鉛框架上。 雖然該方法用於自動組裝，但組裝要求個別模製封裝（即袋 、 式模製），以露出斷面柱以便切斷。對某些應用各封裝使用 個別模製不可取，因其使模製過程易生製造缺陷，如個別 模製與晶粒及基板不對齊。此外，，749專利說明之方法要求 使用非導電黏合劑固定散熱器於鉛框架上以防止電性短 路。此係可能產生缺陷之另一製造過程。 因此，仍需要無須複雜製造步驟之熱增強模製塑膠封裝
O:\88\88354.DOC 1281238 之自動製造方法。 【發明内容】 包括以下兀件之裝置克服或減輕了先前技術之上述及其 它缺點與缺陷：具有第一及第二之大致相對表面的基板:、 基=第一表面上具有複數個焊接點；具有平行於基板第一 及第—表面之第一與第二大致相對表面之晶粒，晶粒第一 表面上具有電性連接至焊接點之複數個1/〇焊墊；封裝晶粒 及基板之至少第一表面的模製化合物；以及至少部：：入 模製化合物的散熱器。散熱器具有周邊切邊部分與基板與 杈製化合物之關聯周邊切邊部分對齊，並不自後者凹進。 基板可為金屬鉛框架，或可包括其上具有第一電性導體 之介電材料，該等第—電性導體係從至少導電跡線、層、 通迢、針腳及包括上述-項或多項之組合之—中選擇。一 第二電性導體陣列可將基板電性耗合至外部電路，該等第 =性導體係從至少焊球、焊凸塊、焊膏、針聊及包括上 二項或多項之組合之一中選擇。—般，晶粒上的ι/〇焊塾 /用打線焊接、卷帶焊接或覆晶焊接方法電性連接至基 板上之焊接點。 -ΪΓ 貝具體實施例中’散熱器具有平行於晶粒第一及第 二二第一與第二大致相對表面。散熱器第二表面係由 杈衣化合物覆蓋，散熱器第— 散埶哭&面則未由杈製化合物覆蓋。 起：二可包括自散熱器第二表面延伸並與晶粒接觸的突 面的向二項具體實施例中’散熱器包括接觸基板第-表 向下支撐腳。散熱器可電性連接至基板。或者，散執
O:\88\88354 D〇C 1281238 器整個與基板分離。 根據本發明之另一方面，製造封裝半導體裝置的方法包 括：在複數個互連基板上安置複數個晶粒；電性連接複數 個曰曰粒中之各晶粒上的1/0焊墊至複數個互連基板中之關 聯基板上的焊接點；在複數個晶粒上固定複數個互連散熱 器；以模製化合物之連續塗層在面上模製複數個晶粒、焊 接點：複數個互連散熱器，以形成複數個互連封裝先驅； 以及單一化互連封裝先驅以提供複數個封裝。 在-項具體實施例中，複數個互連散熱器包括位於複數 個互連散熱器周邊的向下部分。在複數個晶粒上固定複數 個互連散熱器包括在複數個互連基板上安置向下部分，單 一化包括透過向下部分單—化以提供具有與基板完全分離 之一散熱器的封裝。 附圖及以下說明壹φ接+ 士政n 口 ^ ^ 一 曰中扶出本叙明一或多項具體實施例的 細即。從說明書與附圖及巾請專利範圍將可明白本發明的 其他特徵、目的及優點。 【貫施方式】 一考圖1其在10大致顯不之封裝帶之斷面正視圖，包括 三個互連封裝先驅12，其甲各先驅包括與一基板16電性連 接亚且塗佈有模製化合物18的晶粒14。安置於晶粒"上並 且部：封裝於各封裝先驅12之模製化合物18内的係散熱器 2 〇 基板16係互連以形成其★册 _ 小戚基板^22之部分，散熱器20係互 以:成散熱器先驅24之部分。散熱器先驅24包括隸合至 土板^22之邊緣的向下支撐腳部分26。
O:\88\88354 DOC -10- 1281238 在封裝帶ίο的製造中，散熱器先驅24係在晶粒14電性連 接至基板帶22之後並在模製化合物丨8黏貼於散熱器先耙 24、晶粒14及基板帶22之部分之前置於晶粒14之上。模掣 化合物1 8係使用封閉模製方便地黏貼於帶1 〇 ,其中模掣化 合物18的連續塗佈在封裝帶1〇之各封裝先驅12上模製f在 模製化合物1 8固化後，沿線28切斷封裝帶丨〇，如使用片鋸、 衝床、雷射、喷水等，以將封裝先驅12單一化成個別封裝， 其各如圖2之3 0大致所示。 如圖2所示，各單一化封裝3〇包括一晶粒14，其電性連接 至形成封裝30之基板16的基板帶22(圖1)之部分，並連接至 形成封裝30之散熱器20的散熱器先驅24(圖丨）之部分。散熱 20係至少部分嵌入模製化合物18，並且具有一周邊切邊 部分32分別與·基板16與模製化合物18的關聯周邊切邊部分 3 4及3 6對^，並不從後一者的關聯周邊切邊凹陷。散熱器 20增強了封裝30的熱性能及有利電性性能。此外，散熱器 20為晶粒14遮罩作用於封裝3〇上的電磁力。 再人參考圖1，政熱益先驅24可包括位於封裝先驅之各 側的減薄槽口區域38。減薄槽口區域38透過減少單一化過 程中必須切斷之散熱器先驅24的厚度使封裝先驅丨2的單一 化更谷易。如圖2所不，在單一化後，槽口區域38形成一肩 形部分，保持嵌入模製化合物18。模製化合物18作用於肩 形部分以將散無器20錨定於模製化合物丨8内。 向下支撐腳26支撐各互連散熱器2〇位於基板帶 10之晶粒 14上。封裝先驅12的單一化移除支撐腳％，產生具有與基
0 \88\88354 DOC -11 - 1281238 板1 6完全分離之散熱器？ 勺封衣30 0因為散熱器20係與基 完全分離，所以可確保散熱器與基板16的電性絕緣 而無需使用先前技術散熱器設計使用的非導電黏合劑。 雖然在許多封裝設計中％赦 政…、叩2 0與基板1 6電性絕緣係有 利的，但在其他應用中，裎 徒t、政熱為20與基板16之間的電 性連接係可取的。例如， ^ j此而要猎由將散熱器20電性附 著於與電性接-地關聯之其 土板1 6上的烊接點使散熱器20電性 接地。如圖3所示，對於兮笪旛 、以寻應用中的利用，可使用散熱器 先驅2 4之替代例。 在圖3之一項具體實施例中’除位於散熱器先驅24周邊之 支撐腳26外’散熱器先驅24還包括位於各封裝先驅以之間 的向下支撐腳52。如線28所示，封裝先驅12之單一化發生 於接觸基板帶22之支撐腳52的部分，因而在單一化後支撐 腳52之部分仍附著於各基板16。 圖4說明自圖3之封裝帶1〇單一化的封裝“的斷面圖。如 圖4所示，各支撐腳52係附著於形成於基板16上的焊墊％， 以形成相互間的電性連接。最好使用環氧黏合劑將支撐腳 52附著於焊墊56。 在圖1至4的具體實施例中，晶粒14之各輸入/輸出（1/〇)焊 墊60與基板16上之關聯焊接點62之間的電性連接係藉由打 線焊接或卷帶焊接完成，其中引線64或導電卷帶（未顯示） 的一端係連接至I/O焊墊60，引線64的另一端係連接至焊接 點62。但是，應明白，晶粒14之I/O焊墊60與基板16上之關 聯焊接點62之間的電性連接也可替代性地藉由覆晶型連接
O:\88\88354.DOC 1281238 广成’其中晶粒14係倒覆’從而其1/〇焊墊6〇可直接電性連 焊接點62。「直接」電性連接指藉由覆晶方法實施互連， 吏用插入打線4接或卷帶谭接帶。合適的附著物包 從金、锡與紹組成之群組中選擇的主要成分的焊料。 在圖1至4的具體實施例中，基板16係說明為插入型基 板’其包括多個具有電性導體72(如跡線、針腳、通道及同 寺物)之介電材料層，如圖3所示的薄層“。電性導_ 止：曝露於封裝30或34表面的焊盤⑼。另外的電性導體7〇, 雨于求¥凸塊、焊f、針腳及同類物可附著於焊盤〇 電性信號係透過引線64、電性導體72、焊㈣及電性導體 7〇在晶粒14上之1/〇焊㈣與外部電路如印刷電路板之間 if輸。應明白’雖然本發明適用於具有插人基板的模製塑 膠封裝’但是’本發明同樣適用於具有其他類型基板的模 製塑膠封裝。例如’圖5至8說明了具有錯框架型基板的模 製塑膠封裝。 參考圖5’具有金屬純架型基板帶以封裝㈣之斷面 正視圖包括互連封裝先驅12 ’其中各先驅包括與基板㈣ 性連接亚且塗佈有模製化合物18的晶粒14。基板帶22包括 複數個錯框架形式之互連基板16。錯框架型基板“係從金 屬材料如銅或銅合金形成。各基板16包括晶粒邮著於其 上的晶粒焊塾80及與晶粒焊墊8〇分開之複數個引線28。位 於S日粒14之上亚且部分封裝於各封裝先驅12之模製化合物 18内的係散熱器20，其與鄰接散熱器2〇互連以形成散熱器 先驅24。圖5之具體實施例使用的散熱器先驅24實質上類似
O:\88\88354 DOC -13 - 1281238 〆考圖1至4之具體實施例說明之散熱器先驅24。 山各引線82具有-内引線端與—相對之外料端。内⑽ 端上形成的為焊接點62，係電性連接至晶粒14之1/〇焊墊 外引線知提供焊盤68，用於連接至外部電路。引線们 =有減缚厚度的槽σ區域84，透過減少在單—化中必須切 斷之基板16的厚度使封裝先驅12的測量更容易。 f圖5封裝帶10的製造中，散熱器先驅24係在晶粒“附著 ;粒焊墊80且弘性連接至引線82之後並在黏合模製化合 物ΐδ之則安置於晶粒14上。模製化合物邮使用封閉模製 方便地黏合於帶10。在模製化合物18固化後，沿線28切斷 封裝帶10，如使用片鑛、衝床、雷射、喷水等，以將封裝 先驅12單-化成個別封裝，其各如圖6之86大致所示。 如圖6所示，—各單一化封裝86包括形成封裝86之散熱器20 之散熱器先驅24(圖5)之部分。散熱器2〇係至少部分嵌入模 衣化合物18，亚且具有一周邊切邊部分32分別與基板μ與 模製化合物18的關聯周邊切邊部分34及36對齊，並不從後 二者的關聯周邊切邊凹陷。如前述具體實施例之情形，散 熱器20增強了封裝86的熱性能及有利電性性能。此外，散 熱裔20為晶粒14遮罩作用於封裝86上的電磁力。 07 a與7b各具有金。框架型基板16之封裝帶⑺的斷面正視 圖，其中晶粒14係以覆晶方式電性連接至基板。封裝帶10 實質上類似於圖5顯示的封裝帶，例外之處為，圖以與几的 錯框架基板16不包括晶粒焊塾，而且圖〜與％的引線邮 晶粒14下延伸，用於直接電性連接1/〇焊墊6〇。如前述具體
O:\88\88354 DOC -14- 1281238 實施例之情形，封裝帶 一〃 m線28㈣，如使用片錯、衝 街射 貝水等，以將封妒先靶1 2 I ,, 士门 竹玎衣无驅I2早一化成個別封萝。 在圖7a說明之封裝帶丨〇中，曰 、 Μ ^ σσ 宁日日粒14如错由模製化合物18盥 放…器先驅24分離。圖7b與圖几一樣” 几的封“附，散熱器先驅24係藉由導熱性高卿化 合㈣的-層雜附著於各晶粒。例如，層材料88;為 置於晶粒14上之導熱膏層或金屬材料層。 如圖_8b所示，各單—化封裝90包括直接電性連接至 引線82的晶粒14。各單-化封裝還包括形成封裝90之散埶 器20的散熱器先驅24(圖7_之部分。散熱器2〇係至少部 分嵌入模製化合物18’並且具有一周邊切邊部分32分別與 基板16與模製化合物18的關聯周邊切邊部分“及％對齊， 並不從後二者的Μ周邊切邊凹陷^如前述具體實施例之 情形，散熱器20增強了封裝9〇的熱性能及電性性能。在圖 8b之具體實施例中，置於晶粒14與散熱器川之間的材料層 88透過提高晶粒14與散熱器2〇之間的導熱性進一步增強封 裝90的熱性能。 參考圖9與10，其顯示用於圖i、2、及5至8的具體實施例 的散熱器先驅24。散熱器先驅24包括複數個互連散熱器2〇 其各包括一平坦頂部表面92、一相對之平坦底部表面料及 在頂部表面92之周邊延伸並自其凹陷的肩形表面％。各散 熱器20係透過一對連接桿98互連至鄰接散熱器2〇。如從圖 1 0之正視圖所見’連接桿98與肩形表面96形成減薄厚度之 槽口區域3 8。置於散熱器先驅2 4周邊的係支撐腳2 6。應明 O:\88\88354 DOC •15- 1281238 T ’雖然未顯示，如目3與4所示，圖3與4之具體實施例的 散^器先驅24可藉由將連接桿98形成為支撐腳52而獲得。 一散熱器先驅24可自導熱性高於模製化合物以之任何材料 薄片形成。散熱器先驅24最好為金屬，例如，_、铭或包 銅人紹之4夕項的合金。例如在需要較高導熱性的地 方，銅與銅基合金較好，而在需要較低導熱性的地方，铭 或銘基合金較好。如本文之定義’㈣「合金」指兩或多 種金屬的混合，或—或多種具有某些非金屬元素的金屬的 混及與金屬關聯使用的術語「基」指包括至少50 wt% 元素的δ孟。各散熱益20之部分，尤其是曝露於封裝 頂部之頂部表面92可鍍一金屬如鎳，以防止氧化。也可使 用任何傳統方法對散熱㈣進行防銹處理與/或美化處理， 如在其表面塗佈黑色氧化物塗層。 ^形成散熱器先驅24之導電材料薄片的厚度最好在約〇.2 毫米（millimeter ; mm)至約〇·5 mm之間，在約〇 2 至約 〇.3mm之間更好。可使用任何已知方法如壓印、化學蝕刻、 田射切除或同類方法形成包括連接桿98與支撐腳％之散熱 器先驅24的特徵。支撐腳26最好藉由彎曲形成為向下形。 最好使用控制消減程序如化學蝕刻或雷射切除形成減薄厚 度槽口區域38。最好充分#刻減薄厚度槽口區域38以提供 厚度在散熱器20之厚度（即頂部與底部表面92、94之間的厚 度）的約25%至約60%的肩形表面96與連接桿％，在該厚2 之約50%至約60%之間更好。在該較佳範圍内的厚度在減& 厚度槽口區域38提供足夠的間隙接受模製化合物18，該模
OA88\88354.DOC -16 - 1281238 製化合物鎖定封裝内的散熱器20 便於單一化。 並減少足夠量 之金屬以 麥考圖其顯示散熱器24之一項替代具體實施例，盆 中各散熱器20包括一突起100自底部表面94延伸。當散熱: 2 〇安裝於封裝内後，各突起丨〇 〇接觸關聯晶 $二二: 的熱量直接導至散熱器2〇。散熱器可使用環氧黏” 或同類物附著於晶粒。應明自，具有突起之散熱器可用^ 圖1至8的任何具體實施例。 參考圖12與丨3，其顯示散熱器先驅24之另一項具體實施 例。在圖12之具體實施例中，散熱器先驅24包括複數個互 連散熱器2G，其各包括-平坦頂部表面％相對之平坦 底部表面94及在頂部表面92之周邊延伸並自其凹陷的肩开: 表面96。各散熱器20係透過一凹陷平坦部分1〇2互連至鄰接 散熱器20。如自圖13之正視圖可見的，凹陷平坦部分ι〇2形 成在單一化中切斷之減薄厚度槽口區域38之部分。置於散 熱器先驅24之周邊的係支撐腳26，透過支撐腳％之部分安 置的係複數個穿透孔1 04，其用於使模製化合物丨8進入。 形成圖12與13之散熱器先驅24之導電材料薄片的厚度最 好在約0·2 mm至約0.5 mm之間，在約〇·2 mm至約〇·3 mm之 間更好了使用任何已知方法如壓印、化學钱刻、雷射切 除或同類方法形成散熱器先驅24的特徵，如支撐腳26與穿 透孔104。支撐腳26可彎曲成型。肩形區域26最好蝕刻至厚 度在散熱器20之厚度（即頂部與底部表面92、94之間的厚度） 的約25%至約60%之間，在該厚度之約5〇%至約6〇。/()之間更
O:\88\88354 DOC 17- 1281238 好。在該較佳範圍内的厚度在減薄厚度槽口區域38提供足 夠的間隙接受模製化合物18，該模製化合物鎖定封裝内的 散熱态20，並減少足夠量之金屬以便於單一化。如圖1 4所 示，圖12與13的散熱器先驅24還可包括接觸晶粒14的突起 100 〇 麥考圖15與16，其顯示散熱器先驅24之另一項具體實施 例。在圖1 5之具體實施例中，散熱器先驅24包括複數個互 連散熱裔20，其各包括一平坦頂部表面92、一相對之平坦 底部表面94及在頂部表面92之周邊延伸並自其凹陷的肩形 表面96。各散熱器20係透過一凹陷平坦部分1〇2互連至鄰接 政熱态20。如自圖16之正視圖可見的，圖15與16之具體實 施例對應於圖3之散熱器先驅24，其中除置於散熱器先驅24 周邊之支撐腳26外，散熱器先驅24還包括位於各封裝先驅 12之間的向下支撐腳52。凹陷平坦部分1〇2形成支撐腳^的 底部部分，在單一化中切斷。透過支撐腳26與52之部分安 置的係複數個穿透孔104 ,其使模製化合物18能夠進入。如 同參考圖3及4所述，散熱器2〇係電性連接至基板16，則可 能需要穿透孔104的數目及位置可自圖15與16說明之情形 變化至提供不同的支撐腳26與52圖案。 形成圖15與16之散熱器先驅24之導電材料薄片的厚度最 好在約〇·2 mm至約〇·5 mm之間，在約〇 2 mm至約〇·3 之 間更好。可使用任何已知方法如壓印、化學蝕刻、雷射切 除或同類方法形成散熱器先驅24的特徵，如穿透孔1〇4。支 撐腳26與52可彎曲成型。肩形區域26最好蝕刻至厚度在散
O:\88\88354.DOC -18- 1281238 熱器20之厚度（即頂部與底部表面92、94之間的厚度）的約 2 5%至約60%之間，在該厚度之約50%至約60%之間更好。 如圖1 7所示，圖1 5與1 6的散熱器先驅24還可包括接觸晶粒 14的突起100。 在上述各具體實施例中，封裝帶1 〇及其關聯散熱器先焉區 24及基板帶22係說明為具有三個互連封裝先驅12之陣列或 矩陣。但是，應明白，本發明適用於具有組裝成陣列或矩 陣形式之兩或多個互連封裝先驅12的任何封裝帶1〇。例如， 圖18與19說明配置用於組裝2x2互連封裝先驅矩陣的封裝 帶10 〇 圖1 8係本發明之封裝帶1 〇之範例於各製造階段的平面 圖。圖19係圖18之封裝帶1〇的斷面正視圖，圖2〇係說明製 造模製塑膠封裝之方法118的流程圖，該方法可用於製造本 文說明之任何具體實施例。在方法丨丨8中，各晶粒丨4係使用 傳統方法如焊料、環氧、雙面黏合劑及同類物固定於基板 帶22(方法118之區塊120)。在晶粒14固定至基板帶22後，引 線64係個別連接於晶粒14之1/〇焊墊6〇與基板帶22之焊接 點62之間（區塊122)。或者，若I/O焊墊6〇係使用覆晶方法電 性連接至焊接點62，則步驟120與122同時實施，並且各晶 粒14與基板帶22之間的電性連接也用作將晶粒14機械性地 附著於基板上。 在日日粒14弘性連接至基板帶22之後，若需要，導熱材料 8 8(圖7b)可塗佈於晶粒背面，使各封裝中的散熱器連接至 晶粒14(區塊124)。然後，將散熱器先驅24安置於晶粒14上，
O:\88\88354.DOC -19- 1281238 使散熱器先驅24内的各散熱器20在各自的晶粒14之上方對 準政熱為先驅2 4的支樓腳2 6係使用焊料、環氧、雙面黏 合帶及同類物耦合至基板帶22(區塊丨26)。 政熱先驅24到位後，使用封閉模製方法為封裝先驅i 2 塗佈模製化合物18(區塊128)。即，連續塗佈模製化合物18 在封裝先驅12之矩陣内的各封裝先驅12上進行模製。如圖 18所不，各散熱器20的頂部表面92仍曝露於模製化合物18 之外。在模製化合物18固化後，電性導體7〇(如焊球、焊凸 塊、焊膏、針腳等）的陣列可附著至基板帶（區塊13〇)。然後，_ 可使用傳統方法如鋸子、衝床、雷射或喷水沿線28單一化 封裝先驅12以提供個別封裝（區塊132)。應明白，方法118 可包括各種特定封裝設計需要的檢查步驟、固化步驟、清 潔步驟或其他步驟。 方法118提供熱增強模製塑膠封裝之自動製造，同時省略 了與先前技術之方法關聯之某些複雜製造步驟。例如，方 法11 8允許使用封閉模製技術模製封裝帶内的封裝。因此， 本發明消除了與用於製造先前技術之熱增強模製塑膠封裝· 之個別模製技術關聯的問題。此外，因為本發明之散熱哭 先驅24無需附著於各個別封裝内的基板上，本發明消除了 先前技術方法必須之使用介電黏合劑將散熱器固定於個別 封裝先驅内的基板的需要。 已說明本發明的一些具體實施例。但是，應明白，可進 行各種修改而不背離本發明的精神與範疇。因此，其他具 體實施例都屬於下列申請專利範圍的範疇内。
O:\88\88354.DOC -20- 1281238 【圖式簡單說明】 結合以下附圖將自上述詳細說明更在附圖巾，相同元件編號相同，其中 圖1係具有插入基板之本發明之範 圖； 全面地理解本發 例封裝帶的斷面 明， 正視 圖2係自圖1之帶單一 圖3係具有插入基板 正視圖； ， 化的封裝的斷面正視圖； 之封衣V的替代具體實施例的斷面 圖4係自圖3之帶單一化的 ^ 平化的封裝的斷面正視圖； 圖5係具有錯框架基板之 視圖· ^月之犯例封裝帶的斷面正 係自圖5之帶單—化的封裝的斷面正視圖； 圖7a係具有錯框架基板之封裝帶的替代具體實施例的 面正視圖； 圖7b係在晶粒與散熱器先 心间文置有導熱材料之圖7a 之封裝帶的斷面正視圖； 圖㈣自圖7a之帶單一化的封裝的斷面正視圖； 圖8b係自圖7b之帶單一化的封裝的斷面正視圖,· 圖9係开> 成散熱益先驅之互連散熱器陣列的平面圖； 圖10係沿圖9之八至A部分之互連冑熱器陣列的斷面正視 圖11係包括晶粒接觸突起之沿圖9之八至八部分之互連散 熱器陣列的斷面正視圖； 圖12係形成散熱器先驅之互連散熱器陣列之替代具體實 0 \88\88354 DOC -21- 1281238 施例的平面圖； 圖13係沿圖12之B至B部分之互連散熱器陣列的斷面正 視圖； 圖14係包括晶粒接觸突起之沿圖12之3至6部分之互連 散熱器陣列的斷面正視圖； 圖1 5如形成放熱裔先驅之互連散熱器陣列之替代具體實 施例的平面圖； ' 圖16係沿圖15之（：至c部分之互連散熱器陣列的斷面正 視圖； 圖17係包括晶粒接觸突起之沿圖15之〇至（：部分之互連 散熱器陣列的斷面正視圖； 圖18係本發明之封裝帶於各製造階段的平面圖； 圖19係沿圖18之〇至〇部分的封裝帶的斷面正視圖；以及 圖20係說明製造模製塑膠封裝之方法的流程圖。 【圖式代表符號說明】 10 封裝帶 12 封裝先驅 14 晶粒 16 基板 18 模製化合物 20 散熱器 22 基板帶 24 散熱為先驅 26 向下支撐腳部分
O:\88\88354.DOC -22- 線 封裝 周邊切邊部分 封裝；周邊切邊部分 周邊切邊部分 減薄厚度槽口區域 支撐腳 封裝 焊墊 輸入輸出焊墊 焊接點 引線 介電材料 焊盤 電性導體 電性導體 晶粒焊墊 引線 減薄厚度槽口區域 單一化封裝 材料層 單一化封裝 平坦頂部表面 平坦底部表面 肩形表面 -23 - 1281238 98 連接桿 100 突起 102 凹陷平坦部分 104 穿透孔 118 方法 O:\88\88354 DOC -24

Claims (1)

  1. 产雜月必日修(更)正替換頁 128 ^^27G66號專利申請案 中文申請專利範圍替換本(96年元月) 拾、申請專利範圍： 1 · 一種包裝一半導體晶粒之模製裝置，包括： 一基板（16)，其具有第一與第二大致相對之表面，該基 板（16)第一表面上安置有複數個焊接點（6 2); -安裝於該基板（16)之第—側的晶粒（14)，該晶粒（Μ) 具有與該基板（16)第一與第二表面平行之第一與第二大 致相對之表面，該晶粒（14)第一表面上安置有複數個ι/〇 焊墊（60)，該等I/O焊墊（6〇)係與該等焊接點（62)電性連 接； 一模製化合物（1 8)封裝該晶粒（i4)及至少該基板（i 6)之 該第一表面； 政熱器（20)至少部分欲入該模製化合物（18)，並且具 有一周邊切邊部分（32)分別與基板（16)及模製化合物（1 8) 的關聯周邊切邊部分（34、36)對齊，並不從後二者的關聯 周邊切邊凹陷。 2·如申請專利範圍第1項之裝置，其中該散熱器（2〇)具有平 仃於該晶粒（14)第一與第二表面的第一與第二大致相對 表面w亥政熱器（2 〇)第二表面係由該模製化合物（1 8 )覆 蓋’该散熱器（20)第一表面未由該模製化合物（18)覆蓋。 3·如申請專利範圍第2項之裝置，其中該散熱器（2〇)係透過 導熱性高於該模製化合物（18)之導熱性的材料（88)熱連 接至該晶粒。 4.如申請專利範圍第2項之裝置，其中該散熱器（2〇)包括一 犬起（100)自該散熱器（20)第二表面延伸，該突起接觸該 O:\88\88354-960116.DOC 1281238 5. 6· 晶粒（14)。 如申請專利範圍第1項之萝w 展置’其中該散熱器（20)包括 向下支撐腳（52)接觸該基板〇6)第一表面。 7. 8. 如申請專利範圍第5項之裝置 連接至該基板（16)。 如申請專利範圍第1項之裝置 與該基板（16)分離。 如申請專利範圍第1項之裳置 置於其内的穿透孔（104)，用 之間該模製化合物（18)的進入 ’其中該散熱器（20)係電性 ’其中該散熱器（20)係完全 ’其中該散熱器（20)包括安 於在散熱器（20)與基板（16) 9. 如申請專利範圍第1項之裝置，以該基板⑽係-金屬 鉛框架。 10. 2申請專利範圍第旧之裝置，其中該基板⑽包括其上 安置有第一電性導體（72)之介電材料（66)，該等第一電性 導體（72)係k至少導電跡線、層、通道、針腳及包括上述 一或多項之組合之一中選擇。 11·如申請專利範圍第10項之裝置，進一步包括： 一第二電性導體（70)陣列將該基板（16)電性耦合至一 外部電路，該等第二電性導體（7〇)係從至少焊球、焊凸塊、 焊膏、針腳及包括上述一或多項之組合之一中選擇。 12·如申請專利範圍第1項之裝置，進一步包括·· 複數個引線（64)或導電卷帶，各電性連接於該晶粒（14) 第一表面上的一 I/O焊墊（6〇)與該基板（16)第一表面上的 一焊接點（62)之間。 O:\88\88354.960l I6.DOC -2 - 1281238 13 14 15. 16. 17. •如申請專利範圍第1項之裝置，其中該晶粒（14)上各1/〇桿 墊（60)係以覆晶方法直接電性連接至該基板（16)上的一 焊接點（62)上。 一種用於製造封裝半導體裝置的方法，該方法包括·· 在複數個互連基板（16)上安置複數個晶粒（14); 電性連接该複數個晶粒内之各晶粒（丨4)上的J/0焊塾 (60)至該複數個互連基板内之一關聯基板（16)上的焊接 點（62); 在該複數個晶粒（14)上固定複數個互連散熱器（2〇); 使用一模製化合物（1 8)之連續塗佈在該複數個晶粒 (14)、該等焊接點（62)及該複數個互連散熱器上進行 模製’以形成複數個互連封裝先驅（丨2);以及 單一化該等互連封裝先驅（12)以提供複數個封裝。 如申請專利範圍第14項之方法，其中該散熱器（2〇)具有平 行於該晶粒（14)第一與第二表面的第一與第二大致相對 表面，其中該表面模製使該散熱器（2〇)第二表面由該模製 化合物（18)覆蓋，而該散熱器（20)第一表面未由該模製化 合物（18)覆蓋。 如申请專利範圍第15項之方法，進一步包括： 在電性連接之後但在表面模製之前，向該複數個晶粒 的背面塗佈一導熱材料（88)，該導熱材料（88)之導熱性高 於該模製化合物（18)的導熱性。 如申請專利範圍第15項之方法，其中該散熱器（2〇)包括一 突起（100)自該散熱器（2〇)第二表面延伸，該突起接觸該 O:\88\88354-960116.DOC -3- 1281238 晶粒（14)。 18. 如申請專利範圍第14項之方法，其中該複數個互連散熱 器（20)包括一向下部分安置於該複數個互連散熱器之一 周邊，其中將該複數個互連散熱器固^於該複數個晶粒 上包括在複數個互連基板上安置該向下部分，該單一化 包括透過該向下部分單-化以提供具有完全與該基板⑽ 分離之一散熱器（2〇)的一封裝（3〇)。 19. 如申請專利範圍第14項之方法，進一步包括： 電性連接該複數個散熱器之錄熱器（2G)至該複數個 基板之一關聯基板（1 6 )。 2〇·如申請專利範圍第14項之方法，其中該散熱器（2〇)包括安 置於其内的孔徑，用於在散熱器（2〇)與基板⑽之間該模 製化合物（18)的進入。 A如申請專利範圍第14項之方法，其中該基板（16)係— 錯框絮。 △ Μ請專利_第14項之方法，其中該基板（16)包括其上 安置有第-電性導體（72)之介電材料（％)，該等第一電性 導體⑼係從至少導電跡線、層、通道、針腳及包括上述 一或多項之組合之一中選擇。 23·如申請專利範圍第22項之方法，進一步包括·· 電性麵合—第二電性導體（7G)陣列至基板⑽，該 二電性導體（70)係從至少烊球、谭凸塊、焊膏、針腳及包 括上述一或多項之組合之一中選擇。 申明專利觀圍第14項之方法，其中電性連接該等⑽焊 O:\88\88354-9601J6.doc 1281238 墊（60)至該等焊接點（62)包括·· 打線焊接或卷帶焊接該等1/〇焊墊（6〇)至該等焊接點 (62) 〇 25. ’其中電性連揍該等I/O焊 等1/0焊墊（60)至該等焊接 如申請專利範圍第14項之方法 塾（60)至該等焊接點（62)包括·· 以覆晶方法直接電性連接該 點（62) 〇 O:\88\88354-960116.DOC 5-
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI643297B (zh) * 2016-12-20 2018-12-01 力成科技股份有限公司 具有內置散熱片之半導體封裝構造

Families Citing this family (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI239080B (en) * 2002-12-31 2005-09-01 Advanced Semiconductor Eng Semiconductor chip package and method for the same
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US8211753B2 (en) * 2003-08-26 2012-07-03 Stats Chippac Ltd. Leadframe-based mold array package heat spreader and fabrication method therefor
TWI233170B (en) * 2004-02-05 2005-05-21 United Microelectronics Corp Ultra-thin wafer level stack packaging method and structure using thereof
TWI374525B (en) * 2004-05-11 2012-10-11 Taiwan Semiconductor Mfg Cut-out heat slug for integrated circuit device packaging
US7084494B2 (en) * 2004-06-18 2006-08-01 Texas Instruments Incorporated Semiconductor package having integrated metal parts for thermal enhancement
KR100631403B1 (ko) * 2004-09-23 2006-10-09 삼성전자주식회사 방열판을 장착한 반도체 패키지 및 그 제조 방법
CN101053079A (zh) 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
US7851268B2 (en) * 2005-04-09 2010-12-14 Stats Chippac Ltd. Integrated circuit package system using heat slug
KR20080013865A (ko) 2005-06-06 2008-02-13 로무 가부시키가이샤 반도체 장치, 기판 및 반도체 장치의 제조 방법
CN100466210C (zh) * 2005-07-15 2009-03-04 矽品精密工业股份有限公司 散热型半导体封装件及其制法
US8643163B2 (en) * 2005-08-08 2014-02-04 Stats Chippac Ltd. Integrated circuit package-on-package stacking system and method of manufacture thereof
US20070108583A1 (en) * 2005-08-08 2007-05-17 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
EP1764834B1 (en) * 2005-09-15 2009-03-04 Infineon Technologies AG Electromagnetic shielding of packages with a laminate substrate
US8624346B2 (en) * 2005-10-11 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Exclusion zone for stress-sensitive circuit design
US7582951B2 (en) * 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8039951B2 (en) 2006-01-19 2011-10-18 United Test And Assembly Center Ltd. Thermally enhanced semiconductor package and method of producing the same
US8022512B2 (en) * 2006-02-28 2011-09-20 Unisem (Mauritus) Holdings Limited No lead package with heat spreader
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US7808087B2 (en) 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US7741158B2 (en) * 2006-06-08 2010-06-22 Unisem (Mauritius) Holdings Limited Method of making thermally enhanced substrate-base package
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US8049313B2 (en) * 2006-09-20 2011-11-01 Freescale Semiconductor, Inc. Heat spreader for semiconductor package
US20080157300A1 (en) * 2006-12-27 2008-07-03 Shih-Fang Chuang Thermally Enhanced IC Package and Method
US8183687B2 (en) * 2007-02-16 2012-05-22 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
TWI332255B (en) * 2007-03-20 2010-10-21 Orient Semiconductor Elect Ltd Heat block
US7952167B2 (en) * 2007-04-27 2011-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line layout design
US8125052B2 (en) * 2007-05-14 2012-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure with improved cracking protection
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
US8643172B2 (en) * 2007-06-08 2014-02-04 Freescale Semiconductor, Inc. Heat spreader for center gate molding
US8643147B2 (en) 2007-11-01 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with improved cracking protection and reduced problems
US8178956B2 (en) * 2007-12-13 2012-05-15 Stats Chippac Ltd. Integrated circuit package system for shielding electromagnetic interference
CN101226888B (zh) * 2008-02-15 2010-09-15 日月光半导体制造股份有限公司 散热型芯片封装工艺及其构造
US8154134B2 (en) * 2008-05-12 2012-04-10 Texas Instruments Incorporated Packaged electronic devices with face-up die having TSV connection to leads and die pad
US8072047B2 (en) * 2008-05-21 2011-12-06 Stats Chippac Ltd. Integrated circuit package system with shield and tie bar
US8334582B2 (en) * 2008-06-26 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protective seal ring for preventing die-saw induced stress
US20100052156A1 (en) * 2008-08-27 2010-03-04 Advanced Semiconductor Engineering, Inc. Chip scale package structure and fabrication method thereof
US8390112B2 (en) * 2008-09-30 2013-03-05 Intel Corporation Underfill process and materials for singulated heat spreader stiffener for thin core panel processing
US7863722B2 (en) * 2008-10-20 2011-01-04 Micron Technology, Inc. Stackable semiconductor assemblies and methods of manufacturing such assemblies
US7906836B2 (en) * 2008-11-14 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreader structures in scribe lines
US7951643B2 (en) * 2008-11-29 2011-05-31 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
US8368180B2 (en) * 2009-02-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line metal structure
CN101533816B (zh) * 2009-05-06 2011-02-09 友达光电股份有限公司 导电凸块结构及显示面板的芯片焊接结构
US20110012257A1 (en) * 2009-07-14 2011-01-20 Freescale Semiconductor, Inc Heat spreader for semiconductor package
CN102097395A (zh) * 2009-12-11 2011-06-15 日月光半导体（上海）股份有限公司 具有内嵌芯片的基板结构
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8653635B2 (en) * 2011-08-16 2014-02-18 General Electric Company Power overlay structure with leadframe connections
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9159643B2 (en) 2012-09-14 2015-10-13 Freescale Semiconductor, Inc. Matrix lid heatspreader for flip chip package
US8921994B2 (en) 2012-09-14 2014-12-30 Freescale Semiconductor, Inc. Thermally enhanced package with lid heat spreader
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
TWI471988B (zh) * 2012-11-13 2015-02-01 矽品精密工業股份有限公司 半導體封裝件之製法
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9653405B2 (en) * 2013-02-20 2017-05-16 Infineon Technologies Ag Chip arrangement and a method of manufacturing a chip arrangement
US8987876B2 (en) 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
CN104916597B (zh) * 2014-03-14 2018-06-05 尼克森微电子股份有限公司 晶圆级扇出芯片的封装方法及封装结构
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
JP6017492B2 (ja) 2014-04-24 2016-11-02 Ｔｏｗａ株式会社 樹脂封止電子部品の製造方法、突起電極付き板状部材、及び樹脂封止電子部品
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
JP5944445B2 (ja) * 2014-07-18 2016-07-05 Ｔｏｗａ株式会社 樹脂封止電子部品の製造方法、突起電極付き板状部材、樹脂封止電子部品、及び突起電極付き板状部材の製造方法
CN105633027B (zh) * 2014-11-05 2019-07-16 无锡超钰微电子有限公司 扇出晶圆级芯片封装结构及其制造方法
JP2016092300A (ja) * 2014-11-07 2016-05-23 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
KR102117477B1 (ko) * 2015-04-23 2020-06-01 삼성전기주식회사 반도체 패키지 및 반도체 패키지의 제조방법
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
TWI594380B (zh) * 2015-05-21 2017-08-01 穩懋半導體股份有限公司 封裝結構及三維封裝結構
US9892935B2 (en) * 2015-05-28 2018-02-13 International Business Machines Corporation Limiting electronic package warpage with semiconductor chip lid and lid-ring
US9666556B2 (en) * 2015-06-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip packaging
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
JP6605382B2 (ja) * 2016-03-30 2019-11-13 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN110957286A (zh) * 2019-12-04 2020-04-03 矽品科技（苏州）有限公司 一种片状分离式散热片组件

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367196A (en) * 1992-09-17 1994-11-22 Olin Corporation Molded plastic semiconductor package including an aluminum alloy heat spreader
US5608267A (en) * 1992-09-17 1997-03-04 Olin Corporation Molded plastic semiconductor package including heat spreader
JPH06349893A (ja) * 1993-06-02 1994-12-22 Citizen Watch Co Ltd フリップチップ接続半導体パッケージ
US6271579B1 (en) * 1993-10-08 2001-08-07 Stratedge Corporation High-frequency passband microelectronics package
US5734201A (en) * 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5471011A (en) * 1994-05-26 1995-11-28 Ak Technology, Inc. Homogeneous thermoplastic semi-conductor chip carrier package
US5929513A (en) * 1994-08-16 1999-07-27 Fujitsu Limited Semiconductor device and heat sink used therein
JP3297251B2 (ja) * 1995-06-20 2002-07-02 株式会社東芝 携帯形電子機器
US5650663A (en) 1995-07-03 1997-07-22 Olin Corporation Electronic package with improved thermal properties
US5919329A (en) 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6409859B1 (en) * 1998-06-30 2002-06-25 Amerasia International Technology, Inc. Method of making a laminated adhesive lid, as for an Electronic device
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6057601A (en) 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
TW410446B (en) * 1999-01-21 2000-11-01 Siliconware Precision Industries Co Ltd BGA semiconductor package
US6432749B1 (en) * 1999-08-24 2002-08-13 Texas Instruments Incorporated Method of fabricating flip chip IC packages with heat spreaders in strip format
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
US6432742B1 (en) * 2000-08-17 2002-08-13 St Assembly Test Services Pte Ltd. Methods of forming drop-in heat spreader plastic ball grid array (PBGA) packages
US6432752B1 (en) 2000-08-17 2002-08-13 Micron Technology, Inc. Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages
JP2002289756A (ja) * 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
TW498516B (en) * 2001-08-08 2002-08-11 Siliconware Precision Industries Co Ltd Manufacturing method for semiconductor package with heat sink
US6534859B1 (en) * 2002-04-05 2003-03-18 St. Assembly Test Services Ltd. Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI643297B (zh) * 2016-12-20 2018-12-01 力成科技股份有限公司 具有內置散熱片之半導體封裝構造

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US7259445B2 (en) 2007-08-21
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