TWI471988B - 半導體封裝件之製法 - Google Patents

半導體封裝件之製法 Download PDF

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Publication number
TWI471988B
TWI471988B TW101142158A TW101142158A TWI471988B TW I471988 B TWI471988 B TW I471988B TW 101142158 A TW101142158 A TW 101142158A TW 101142158 A TW101142158 A TW 101142158A TW I471988 B TWI471988 B TW I471988B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
package according
fabricating
heat dissipating
encapsulant
Prior art date
Application number
TW101142158A
Other languages
English (en)
Other versions
TW201419466A (zh
Inventor
劉世耀
蔡岳穎
陳泳良
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101142158A priority Critical patent/TWI471988B/zh
Priority to CN201210499796.0A priority patent/CN103811359B/zh
Priority to US13/859,147 priority patent/US9257311B2/en
Publication of TW201419466A publication Critical patent/TW201419466A/zh
Application granted granted Critical
Publication of TWI471988B publication Critical patent/TWI471988B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Claims (9)

  1. 一種半導體封裝件之製法，係包括：提供一散熱結構，該散熱結構具有散熱部、與該散熱部結合之支撐部及與該支撐部結合之結合部，且該支撐部係為形變體，該結合部具有第一定位部；結合一其上承載有半導體元件之承載件至該散熱結構之結合部上，使該承載件與該散熱部之間形成一容置空間，而令該半導體元件收納於該容置空間中，該承載件具有對應該第一定位部之第二定位部；以及形成封裝膠體於該容置空間中，以由該封裝膠體包覆該半導體元件。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括於形成該封裝膠體後，移除該結合部及支撐部。
  3. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該散熱部具有溝槽。
  4. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該散熱部之尺寸係小於該結合部之尺寸。
  5. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該散熱部之尺寸係等於該結合部之尺寸。
  6. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，係於模具中形成該封裝膠體。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該模具係具有夾持部，以夾固該承載件與該結合部。
  8. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該模具係具有一模穴，該模穴之高度係小於該散熱結構之高度。
  9. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該模具係具有複數透孔，於形成該封裝膠體時，藉抽氣方式經該透孔吸附該散熱結構之散熱部。
TW101142158A 2012-11-13 2012-11-13 半導體封裝件之製法 TWI471988B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW101142158A TWI471988B (zh) 2012-11-13 2012-11-13 半導體封裝件之製法
CN201210499796.0A CN103811359B (zh) 2012-11-13 2012-11-29 半导体封装件的制法
US13/859,147 US9257311B2 (en) 2012-11-13 2013-04-09 Method of fabricating a semiconductor package with heat dissipating structure having a deformed supporting portion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101142158A TWI471988B (zh) 2012-11-13 2012-11-13 半導體封裝件之製法

Publications (2)

Publication Number Publication Date
TW201419466A TW201419466A (zh) 2014-05-16
TWI471988B true TWI471988B (zh) 2015-02-01

Family

ID=50682108

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101142158A TWI471988B (zh) 2012-11-13 2012-11-13 半導體封裝件之製法

Country Status (3)

Country Link
US (1) US9257311B2 (zh)
CN (1) CN103811359B (zh)
TW (1) TWI471988B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI629761B (zh) * 2017-10-27 2018-07-11 日月光半導體製造股份有限公司 基板結構及半導體封裝元件之製造方法
CN108417540B (zh) * 2018-03-26 2020-10-16 合肥源康信息科技有限公司 一种指纹识别芯片装置
CN108493165A (zh) * 2018-04-19 2018-09-04 苏州通富超威半导体有限公司 封装结构及焊接方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070065984A1 (en) * 2005-09-22 2007-03-22 Lau Daniel K Thermal enhanced package for block mold assembly
TW201230211A (en) * 2011-01-11 2012-07-16 Apic Yamada Corp Method for resin molding, resin molding apparatus and feeding handler

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890152A (en) * 1986-02-14 1989-12-26 Matsushita Electric Works, Ltd. Plastic molded chip carrier package and method of fabricating the same
KR970005712B1 (ko) * 1994-01-11 1997-04-19 삼성전자 주식회사 고 열방출용 반도체 패키지
TWI220783B (en) * 2002-08-26 2004-09-01 Siliconware Precision Industries Co Ltd A semiconductor device having a heat-dissipating structure
WO2004032186A2 (en) * 2002-09-30 2004-04-15 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly
CN1549337A (zh) * 2003-05-09 2004-11-24 华泰电子股份有限公司 防止半导体封装件中散热片溢胶的散热片装置
CN101221944A (zh) * 2007-01-09 2008-07-16 矽品精密工业股份有限公司 散热型半导体封装件

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070065984A1 (en) * 2005-09-22 2007-03-22 Lau Daniel K Thermal enhanced package for block mold assembly
TW201230211A (en) * 2011-01-11 2012-07-16 Apic Yamada Corp Method for resin molding, resin molding apparatus and feeding handler

Also Published As

Publication number Publication date
CN103811359B (zh) 2017-04-05
CN103811359A (zh) 2014-05-21
TW201419466A (zh) 2014-05-16
US9257311B2 (en) 2016-02-09
US20140134805A1 (en) 2014-05-15

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