TWI220783B - A semiconductor device having a heat-dissipating structure - Google Patents
A semiconductor device having a heat-dissipating structure Download PDFInfo
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- TWI220783B TWI220783B TW091119227A TW91119227A TWI220783B TW I220783 B TWI220783 B TW I220783B TW 091119227 A TW091119227 A TW 091119227A TW 91119227 A TW91119227 A TW 91119227A TW I220783 B TWI220783 B TW I220783B
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- heat
- heat sink
- semiconductor device
- heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
1220783 五、發明說明（1) [發明領域] 尤指一種具散熱件以 本發明係關於一種半導體裝置， 提升散熱效率之半導體裝置。 [發明背景] & 隨著半導體製程技術不斷進步，晶片的處理逮度與功 月曰b要求亦隨之提昇，伴隨而至之問題乃在於如何有效逸散 晶片運作時產生的熱量，以維繫半導體裝置之信賴性。以 球拇陣列封裝（BGA)之半導體裝置為例，如2D、3D%圖晶 片（Graphic Chip)、晶片組（Chipset)、中央處理器（cpu) 與主記憶裝置用記憶體上，均具有高數量之輸入/輸出 11 / 〇 )連結端以因應高度積集化之半導體晶片所需，如果 散熱問題未能有效解決，勢將嚴重影響此些裝置的使用效 能0 對BGA半導體裝置而言，傳統之散熱路徑係由晶片、 銀膠、基板至基板下方之導熱銲球（Therma丨Ban)而傳遞 至外界，或由晶片經由包覆晶片之封裝膠體（EncapsuUnt 〇r Molding Body)而傳遞至外界。是種散熱路徑甚長，且 政熱效率亦往往不足’為解決此散熱效率問題，一般在傳 統BG A半導體裝置結構上常增設一以銅或鋁製成的外露型 散熱件（Heat Slug)，如第7圖所示，以使晶片產生的熱量 付藉政熱件之外4表面而直接傳遞至外界，以提高封裝件 的散熱效能。 然上述没置有散熱件之半導體封裝件雖可有效改善散 熱效率，但傳統内傲式散熱件（Embedded Heat Sink)並1220783 V. Description of the invention (1) [Field of invention] In particular, the present invention relates to a semiconductor device with a heat sink, and the semiconductor device improves the heat dissipation efficiency. [Background of the Invention] & With the continuous progress of semiconductor process technology, the processing efficiency and power requirements of wafers have also increased. The accompanying problem is how to effectively dissipate the heat generated during wafer operation to maintain Reliability of semiconductor devices. Taking the semiconductor device of the ball-thumb-array package (BGA) as an example, such as 2D, 3D% Graphic Chip, Chipset, Central Processing Unit (CPU) and main memory device memory, all have high Number of input / output 11 / 〇) connection terminals to meet the needs of highly integrated semiconductor chips, if the heat dissipation problem is not effectively resolved, it will seriously affect the performance of these devices. 0 For BGA semiconductor devices, traditional The heat dissipation path is transmitted from the wafer, the silver glue, the substrate to the thermal pad (Therma 丨 Ban) below the substrate, or passed from the wafer to the outside through the encapsulating body (EncapsuUntor Molding Body) covering the wafer. This kind of heat dissipation path is very long, and the political and thermal efficiency is often insufficient. To solve this problem of heat dissipation efficiency, a conventional heat sink (made of copper or aluminum) is usually added to the traditional BG A semiconductor device structure. As shown in FIG. 7, the heat generated by the chip is directly transferred to the outside by borrowing the outer surface of the thermal element to improve the heat dissipation efficiency of the package. Although the above semiconductor package without heat sink can effectively improve the heat dissipation efficiency, the traditional Embedded Heat Sink
1220783 五、發明說明（2) 未與晶片直接接觸，導致晶片產生的熱量須要經過導熱性 差之封裝膠體才能傳遞至散熱件，是以此種型態之半導體 裝置其散熱效率仍緩不濟急。為解決此一問題，遂有使散 熱件與晶片直接接觸之半導體裝置之提出，以使晶片產生 之熱量可直接經散熱件散逸至外界，而毋須經由封裝膠體 ，遞。美國專利第5, 977, 626號案即揭示此種散熱效率較 高的半導體裝置，如第8圖所示，該半導體裝置大致上係 包括一基板31、接合於該基板31上之晶片32、黏著於該晶 片32上之散熱件33，以及用於包覆住基板31、晶片32與散 熱件33之封裝膠體34。由於以導熱性佳之材料製成的散熱 件33乃與該晶片32直接接觸，並具有外露出該封裝膠體34 =表面，故可將晶片32產生之熱量直接藉該散熱件33之外 路表面散逸至大氣，該散熱件33之表面上亦可外接熱管 (Heat Pipe)或風扇（Fan)等散熱裝置（未圖示），以進一步 提升散熱效率。 上述半導體裝置雖可大幅提昇散熱效率，惟在進行形 成該封裝膠體之模壓作業（Molding Process)中，如第9圖 所不’封裝模具（Mold)於合模後，若散熱件33頂面33〇 至基板31上表面310間之南度Η超過封裝模且35之模穴 (Mold Cavity) 35 0深度h，則封裝模具35之頂面51會壓迫 至散熱件33，而導致晶片32為散熱件33所壓裂；反之，若 散熱件33之頂面330至基板31之上表面31〇間之高度η小於 模穴35 0之深度h，則形成該封裝膠體34之封裝樹脂會溢膝 於該散熱件33之頂面330上’而影響製成品之外觀，並會1220783 V. Description of the invention (2) The heat generated by the wafer is not directly contacted with the wafer, and the heat generated by the wafer needs to be transmitted to the heat sink through a packaging gel with poor thermal conductivity. In this type of semiconductor device, the heat dissipation efficiency is still ineffective. In order to solve this problem, a semiconductor device has been proposed that directly dissipates the heat sink to the wafer, so that the heat generated by the wafer can be directly dissipated to the outside through the heat sink without passing through the packaging gel. US Patent No. 5,977, 626 discloses such a semiconductor device with high heat dissipation efficiency. As shown in FIG. 8, the semiconductor device generally includes a substrate 31, a wafer 32 bonded to the substrate 31, A heat sink 33 adhered to the chip 32 and a packaging gel 34 for covering the substrate 31, the chip 32, and the heat sink 33. Since the heat sink 33 made of a material with good thermal conductivity is in direct contact with the chip 32 and has the surface of the encapsulant 34 exposed, the heat generated by the chip 32 can be directly dissipated by the outer surface of the heat sink 33 To the atmosphere, a heat dissipation device (not shown) such as a heat pipe or a fan may be connected to the surface of the heat dissipation member 33 to further improve heat dissipation efficiency. Although the above-mentioned semiconductor device can greatly improve heat dissipation efficiency, in the molding process for forming the packaging colloid, as shown in FIG. 9, after the mold is packaged (Mold), the top surface 33 of the heat sink 33 The south degree between 310 and the upper surface of the substrate 31 exceeds the mold cavity and the mold cavity 35 depth 35 0, the top surface 51 of the packaging mold 35 will be pressed to the heat sink 33, which will cause the chip 32 to dissipate heat. On the contrary, if the height η between the top surface 330 of the heat sink 33 and the upper surface 31 of the substrate 31 is smaller than the depth h of the mold cavity 350, the sealing resin forming the sealing gel 34 will overflow the knees. The top surface 330 of the heat sink 33 affects the appearance of the finished product and will
1220783 五、發明說明（3) 減少政熱之面積；且若予以溢膠（Flwh)去除之處理，則 會提高封裝成本並導致製程複雜度增加。再者，欲有效控 制散熱件3 3頂面3 3 0至晶片3 2上表面3 2 0間之高度η相當於 模穴350之深度h，則散熱件33之製作精密度則須提升，而 提高封裝產品的製造成本。故習知半導體裝置實仍存有亟 待改良之問題’如何使散熱件得直接與晶片接觸以提升散 熱效率’而又能避免上述問題之發生，乃成一亟待解決之 課題。 [發明概述] 因 接觸晶 露之表 本 接觸’ 本 無溢膠 為 半導體 體晶片 件；一 該第一 底面位 該第一 一與半 此，本 片，以 面而逸 發明之 而無晶 發明之 之虞的 達前述 裝置， ;多數 具有第 散熱件 於該半 散熱件 導體晶 發明之一目的即在提供一種 產生之熱 中的具散 該基板上 之上方， 半導體晶 觸之基部 量可直接 熱結構之 種散熱結 熱結構之 種散熱結 體裝置。 明所提供 一接合於 板與半導 熱件之散 ’而使該 以供該第 片間，且 ，以及多 使晶片所 散至大氣 另一目的在提供一 片碎裂之虞的具散 再一目的在提供一 具散熱結構之半導 及其它目的，本發 係包括：一基板， 用以電性連接該基 一散熱件及第二散 係接置於 導體晶片 之底面與 片直接接 經過散熱結構外 半導體裝置。 構與晶片之直接 半導體裝置。 構之外露表面上 之具散熱結構的 該基板上之半導 體晶片之導電元 熱結構，其中， 第一散熱件之_ 二散熱件夾置於 該第二散熱件具 數之一端係以可1220783 V. Description of the invention (3) Reduce the area of political heat; and if the treatment of removing the overflow (Flwh) will increase the packaging cost and increase the complexity of the process. Furthermore, in order to effectively control the height η between the heat sink 3 3 top surface 3 3 0 and the wafer 3 2 upper surface 3 2 0 is equivalent to the depth h of the mold cavity 350, the precision of manufacturing the heat sink 33 must be improved, and Increase the manufacturing cost of packaged products. Therefore, it is known that there is still a problem in the semiconductor device that needs to be improved, ‘how to make the heat sink directly contact the chip to improve the heat dissipation efficiency’ while avoiding the above problems, which is an urgent problem to be solved. [Summary of the invention] The contact with the surface due to the contact with the crystal dew 'This non-overflow adhesive is a semiconductor wafer; the first bottom surface is the first one and a half of this. This film is invented face to face and there is no crystal invention One of the purposes of the invention is to provide a heat sink in the semi-radiator conductor crystal. One of the purposes of the invention is to provide a heat generated above the substrate, and the base of the semiconductor crystal can be directly heated. Structure type heat dissipation junction structure structure heat dissipation junction device. It is provided that the sheet is connected to the plate and the semi-heat-conducting member to make it available for the first piece, and, moreover, the chip is scattered to the atmosphere. The other purpose is to provide a piece of chip with the risk of fragmentation. In providing a semiconductor with a heat-dissipating structure and other purposes, the hair system includes: a base plate for electrically connecting the base with a heat-dissipating component and a second loose-film connection on the bottom surface of the conductor chip and the sheet directly passing through the heat-dissipating structure. Outer semiconductor device. Structure and wafer direct semiconductor device. The conductive element thermal structure of the semiconductor wafer on the substrate with a heat dissipation structure on the exposed surface of the structure, wherein one of the two heat sinks of the first heat sink is sandwiched between one of the two ends of the second heat sink.
1220783 五、發明說明（4) 撓方式連接至該基部上而另一端乃以可滑移方式抵接至第 一散熱件之底面上的翼部；以及一用以包覆該半導體晶 片、導電元件及散熱結構之封裝膠體，並使該散熱結構之 第一散熱件的一頂面外露出該封裝膠體。 該第二散熱件之翼部宜與其基部一體成型，且各翼部 之間彼此間隔一適當距離，以在該第二散熱件夾設於第一 散熱件之底面及半導體晶片間後，各翼部得各自相對於該 基邛而偏動，同時，各翼部宜由其與基部相連接之端向上 朝外傾斜延伸，以在該翼部受第一散熱件壓動時，翼部與 第一散熱件之底面抵接之端得能朝外微動，以釋除第一散 熱件傳遞而來之壓力，故可避免與第二散熱件直接黏接之 半導體晶片受損。亦即，藉由第二散熱件之翼部具可彈性 變形的特性，有效解決散熱結構因製造精度不足而導致與 之直接相接之半導體晶片於合模時受壓而裂損的問題，且 因無散熱結構之高製造精度的要求，亦可降低製造成本， 復可藉㈣二散熱件對第—散熱件之彈性支撐，使該第一 散熱件之頂面於模壓製程完成時無溢膠產生。 [發明之詳細說明] 以下錄以較佳具體例配合附圖詳細說明本發明之特點 及功效： 如第1圖所示，本發明 導體裝置1係包括一基板1〇 於該基板10之上表面100上 板1 0與晶片1 2間之金線1 3， 較佳實施例之具散熱結構的半 ’以銀膠等習用黏著劑1 1黏接 之晶片12，多數導電連接該基 分別與該晶片1 2及基板1 〇接連1220783 V. Description of the invention (4) The wing is connected to the base in a flexible manner and the other end is slidably abutted to the wing on the bottom surface of the first heat sink; and a cover for covering the semiconductor wafer and conductive elements And the packaging colloid of the heat dissipation structure, and a top surface of the first heat dissipation member of the heat dissipation structure is exposed to the packaging gel. The wing portion of the second heat sink is preferably integrally formed with its base, and the wings are spaced at an appropriate distance from each other so that after the second heat sink is sandwiched between the bottom surface of the first heat sink and the semiconductor wafer, the wings Each part may be biased relative to the base, and at the same time, each wing part should extend upward and outward from the end connected to the base part, so that when the wing part is pressed by the first heat sink, the wing part and the first The abutting end of the bottom surface of a heat sink must be able to move outward to relieve the pressure transmitted by the first heat sink, so that the semiconductor wafer directly bonded to the second heat sink can be prevented from being damaged. That is, by virtue of the elastic deformation of the wings of the second heat sink, the problem that the semiconductor chip directly connected to the heat sink structure is damaged during compression due to insufficient manufacturing precision, and Due to the high manufacturing accuracy requirements of the heat dissipation structure, the manufacturing cost can also be reduced. The elastic support of the first heat sink by the second heat sink can be used to make the top surface of the first heat sink free of overflowing glue when the molding process is completed. produce. [Detailed description of the invention] The following is a detailed description of the features and effects of the present invention with preferred specific examples and drawings: As shown in FIG. 1, the conductor device 1 of the present invention includes a substrate 10 on the upper surface of the substrate 10 The gold wire 1 3 between the 100 upper board 10 and the chip 12 is a half of the preferred embodiment with a heat dissipation structure. The wafer 12 is bonded with a conventional adhesive 11 such as silver glue. Most of the conductive connections connect the base to the Wafer 12 and substrate 1
1220783 五、發明說明（5) 之散熱結構14，包覆住該基板10、晶片12、金線13及部份 散熱結構14的封裝膠體15，以及多數之植接於該基板1〇之 下表面101上的錫球16。 該散熱結構14係由第一散熱件14a及第二散熱件14b所 構成者，且第一散熱件14a及第二散熱件14b均係由導熱性 佳之如銅或鋁等金屬材料製成者。該第一散熱件14a具有 供該第一散熱件1 4a接置於該基板10之上表面1〇〇上之支撐 部140a以及與該支揮部140a—體成型之平坦部141a，該平 坦部141a係由該支撐部140a撐起一預定高度，而使該平坦 部141a位於該晶片12之上，且不致接觸至金線13,並在該 封裝膠體15成形後，該平坦部141a之頂面142a得外露出該 封裝膠體15。而該第二散熱件14b則具有一與該晶片12相 接之基部1 4 0 b及多數片由該基部1 4 0 b侧邊朝上向外傾斜延 伸之翼部141b，如第1及2圖所示，以使該第二散熱件14b 藉該基部1 4 0 b以習用之絕緣導熱膠體1 7黏接至該晶片1 2上 後，各該翼部141b得可滑移地抵接至該第一散熱件1“之 平坦部141a的底面143a上，而使該第二散熱件14b央置於 晶片12與第一散熱件14a之平坦部141a的底面143a間，俾 供該晶片1 2所產生之熱量得經由與該晶片直接黏結之第二 散熱件14b的翼部141b傳遞至該第一散熱件14a，再從該第 一散熱件14a之平坦部14la外露出封裝膠體15的頂面142a 直接逸散至大氣中。此種封裝結構之散熱途徑毋須經過導 熱效果不佳之封裝膠體15，遂能有效提升散熱效率，而解 決習知BGA半導體裝置散熱效率不足之問題。1220783 V. Description of the invention (5) The heat dissipation structure 14 covers the substrate 10, the chip 12, the gold wire 13, and the encapsulating gel 15 of the heat dissipation structure 14, and most of it is implanted on the lower surface of the substrate 10. 101 的 锡 球 16。 101 on the solder ball 16. The heat dissipating structure 14 is composed of a first heat dissipating member 14a and a second heat dissipating member 14b, and the first heat dissipating member 14a and the second heat dissipating member 14b are both made of a metal material such as copper or aluminum with good thermal conductivity. The first heat radiating member 14a has a supporting portion 140a for the first heat radiating member 14a to be placed on the upper surface 100 of the substrate 10, and a flat portion 141a integrally formed with the supporting portion 140a. The flat portion 141a is supported by the supporting portion 140a to a predetermined height, so that the flat portion 141a is located on the wafer 12 without contacting the gold wire 13, and after the packaging gel 15 is formed, the top surface of the flat portion 141a 142a, the encapsulant 15 must be exposed. The second heat dissipating member 14b has a base portion 1 4 0 b connected to the wafer 12 and a plurality of wing portions 141 b extending obliquely upward and outward from the side of the base portion 1 4 0 b, such as the first and second parts. As shown in the figure, after the second heat dissipating member 14b is adhered to the wafer 12 by the conventional insulating and thermally conductive gel 17 by the base portion 1 40b, each of the wing portions 141b can be slidably abutted to the wafer 12 The first heat sink 1 ″ is on the bottom surface 143 a of the flat portion 141 a, and the second heat sink 14 b is centrally placed between the wafer 12 and the bottom surface 143 a of the flat portion 141 a of the first heat sink 14 a for the wafer 12. The generated heat must be transferred to the first heat sink 14a through the wing portion 141b of the second heat sink 14b directly bonded to the chip, and the top surface of the encapsulant 15 is exposed from the flat portion 14la of the first heat sink 14a. 142a directly escapes into the atmosphere. The heat dissipation path of this package structure does not need to pass through the packaging gel 15 with poor thermal conductivity, which can effectively improve the heat dissipation efficiency, and solve the problem of insufficient heat dissipation efficiency of conventional BGA semiconductor devices.
16903.ptd 第10頁 1220783 五、發明說明（6) 同時，該第二散熱件i 4b之翼部1 4 1 b彼此之間係間隔 一適當距離，因此相對於與其連結之基部14〇b得向外撓曲 變形’亦即，如第3圖所示，該第二散熱件1 4b藉其基部 14〇b黏接至晶片12上後，將第一散熱件14a黏接於基板1〇 之上表面100上時，若第一散熱件14a之平坦部141a的底面 143a至晶片12的上表面ι2〇間的距離^小於第二散熱件14b 與絕緣導熱膠17之高度和，則第一散熱件1“之平坦部 141a會施壓於與其底面143a抵接之翼部Ulb，使翼部Ulb 在保持與第一散熱件1 4a相接之狀況下朝外偏移；此種可 撓變形的特性提供一釋除第一散熱件1“傳遞壓力至晶片 12之機制’故可有效避免晶片12因受壓而裂損之狀況發 生。同理’如第4圖所示，當該基板1〇上已黏接有晶片12 及散熱結構14之結構體置於模具18之模穴18〇中進行形成 封裝膠體15之模壓作業時，若該第一散熱件1乜之平坦部 141a的頂面142a至基板1〇之上表面ι〇0的高度^略大於該 模穴180之深度H2’模具18之内頂面181即會下壓該第一散 熱件14a之平坦部141a，使平坦部141a亦會連帶地壓動與 之抵接之第二散熱件14b的翼部141b，而令該翼部141b會 再度朝外偏移’以釋除傳遞至該第二散熱件1“之壓力， 而不致使晶片1 2受損。因而，本發明之散熱結構丨4除能直 接黏結至晶片1 2上以有效逸散晶片J 2產生之熱量外，亦能 藉由該第二散熱件14b之翼片141b所具之可撓變形的特 性’在散熱結構14與基板1〇之接置作業或形成封裝膠體15 之模壓作業時’不致發生晶片丨2因受壓而裂損之問題。16903.ptd Page 10 1220783 V. Description of the invention (6) At the same time, the wings 1 4 1 b of the second heat sink i 4b are spaced at an appropriate distance from each other. Deflection outwards, that is, as shown in FIG. 3, after the second heat sink 14b is adhered to the wafer 12 by its base 14b, the first heat sink 14a is adhered to the substrate 10. On the upper surface 100, if the distance between the bottom surface 143a of the flat portion 141a of the first heat sink 14a and the upper surface ι20 of the chip 12 is smaller than the sum of the height of the second heat sink 14b and the insulating and thermally conductive adhesive 17, the first heat sink The flat portion 141a of the piece 1 "will press the wing portion Ulb abutting on its bottom surface 143a, so that the wing portion Ulb is shifted outward while maintaining contact with the first heat sink 14a; this kind of flexible deformable The feature provides a mechanism for eliminating the “transmission of pressure to the wafer 12” of the first heat sink 1 and thus can effectively prevent the wafer 12 from being damaged due to compression. Similarly, as shown in FIG. 4, when the structure having the wafer 12 and the heat dissipation structure 14 bonded to the substrate 10 is placed in the cavity 18 of the mold 18 to perform the molding operation for forming the encapsulating gel 15, The height from the top surface 142a of the flat portion 141a of the first heat sink 10a to the upper surface ι00 of the substrate 10 is slightly greater than the depth of the cavity 180. The top surface 181 of the mold 18 will push down the surface. The flat portion 141a of the first heat radiating member 14a causes the flat portion 141a to also press the wing portion 141b of the second heat radiating member 14b in contact with it, so that the wing portion 141b will shift outward again. In addition to the pressure transmitted to the second heat sink 1 ", the wafer 12 is not damaged. Therefore, the heat dissipation structure of the present invention can be directly bonded to the wafer 12 to effectively dissipate the heat generated by the wafer J2. In addition, the flexible deformation characteristics of the fins 141b of the second heat sink 14b can also be used to prevent the occurrence of wafers during the mounting operation of the heat dissipation structure 14 and the substrate 10 or the molding operation of forming the encapsulation gel 15.丨 2 The problem of cracking due to compression.
16903.ptd 第11頁 1220783 五、發明說明（7) *該第二散熱件14b之翼部141b與第一散熱件ua相抵接 之端處復可形成一延伸部142b (如第2圖所示），以增加 與第一散熱件14a之底面143a接觸之面積，俾提升第一散 熱件14a與第二散熱件14b間之散熱效率。再者，該翼部 l4lb與第一散熱件14a之底面14 3a抵接之位置宜與第一散 ^件14a之支撐部140a及平坦部141a的相接連處相隔一適16903.ptd Page 11 1220783 V. Description of the invention (7) * An end portion 142b of the wing portion 141b of the second heat sink 14b and the first heat sink ua may form an extension 142b (as shown in FIG. 2). ) To increase the area in contact with the bottom surface 143a of the first heat sink 14a, and to improve the heat dissipation efficiency between the first heat sink 14a and the second heat sink 14b. In addition, the position where the wing portion 14lb abuts the bottom surface 14 3a of the first heat sink 14a should be spaced from the connection between the support portion 140a and the flat portion 141a of the first heat sink 14a.
當距離，以使該翼部141b撓彎變形時具有足夠之移位* 間。 I 該第二散熱件14b之基部140b的形狀除為圖示之方形 外’復可為其它如圓形、八角形等之幾何形狀，無特別限 制，而與該基部140b—體連結之翼部141b之數量則可隨^ 部140b之形狀予以變化。而該基部14〇b之大小亦無特^ & 制，但為增加散熱效率，宜增大晶片丨2與基部丨4〇b相接^ 之面積，然須以不干涉金線13與晶片12銲接之範圍為限。 此外，該翼部141b除圖示之朝基部i4〇b之外部傾斜 伸’亦可朝基部140b之内部伸展，只要其可撓變形之特 仍可發揮者均包含於此翼部141b之適用範圍。同時，如 5圖所示’該晶片12’與基板1〇’之電性連結亦可藉多數 錫凸塊（SolderBumps)13’為之。 該基板上復可黏置有兩個以上之晶片，如第6圖所 示’該基板10"上黏置有二晶片12a”、12b"，此時，該一 晶片1 2 an、1 2 bπ上則分別黏結有一第二散熱件丨4 b "，且談 第二散熱件14b”可共同彈性抵接至一第一散熱件14a"。一 以上所述者，僅為本發明之具體實施例而已，其它任When the distance is such that the wing portion 141b is flexed and deformed, there is sufficient displacement *. I The shape of the base 140b of the second heat radiating member 14b may be other geometric shapes such as a circle, an octagon, etc., except for a square as shown in the figure. There is no particular limitation, and the wings connected to the base 140b are integrally formed. The number of 141b can be changed according to the shape of the part 140b. The size of the base portion 14b is not specially defined, but in order to increase the heat dissipation efficiency, it is desirable to increase the area where the wafer 2 and the base portion 4b are connected ^, but the gold wire 13 and the wafer must not be interfered with. The range of 12 welding is limited. In addition, the wing portion 141b can be extended toward the inside of the base portion 140b in addition to the oblique extension of the base portion i4〇b as shown in the figure. As long as its flexible deformation is still available, it is included in the scope of application of this wing portion 141b. . At the same time, as shown in Fig. 5, the electrical connection between 'the wafer 12' and the substrate 10 'can also be made by most of the solder bumps 13'. Two or more wafers can be glued on the substrate, as shown in FIG. 6 'two wafers 12a and 12b are glued on the substrate 10', at this time, the one wafer 1 2 an, 1 2 bπ A second heat sink 4b " is bonded to each other, and the second heat sink 14b "can be elastically abutted to a first heat sink 14a" together. One of the above is only a specific embodiment of the present invention.
16903.ptd 第12頁 1220783 五、發明說明（8) 何未背離本發明之精神與技術下所作之等效改變或修飾， 均應仍包含在下述專利範圍之内。 IHiil 16903.ptd 第13頁 1220783 圖式簡單說明 [圖示簡單說明] 第1圖係本發明第一實施例之半導體裝置之剖視圖； 第2圖係第1圖所示之較佳實施例中，該散熱結構之上 視圖； 第3圖係第1圖所示之半導體裝置模壓前後之狀態示意 圖； 第4圖係本發明半導體裝置於模壓製程合模時之剖視 圖； 第5圖係本發明另一實施例之半導體裝置之剖視圖； 第6圖係本發明再一實施例之半導體裝置之剖視圖； 第7圖係習知具散熱結構之半導體裝置之剖視圖； 第8圖係美國專利第5, 9 77, 62 6號案之半導體裝置之剖 視圖，以及 第9圖係第8圖所示之半導體裝置於模壓製程中之剖視 圖。 [圖式符號說明] 1 半導體裝置 10 基板 1(Γ 基板 100 上表面 11 黏著劑 12 晶片 12a’ 晶片 12a” 晶片 12bf, 晶片 120 上表面 13 金線 13’ 銲錫凸塊 14 散熱結構 14a 第一散熱件 14an 第一散熱件 14b 第二散熱件16903.ptd Page 12 1220783 V. Description of the invention (8) Any equivalent changes or modifications made without departing from the spirit and technology of the present invention should still be included in the scope of the following patents. IHiil 16903.ptd Page 13 1220783 Brief description of the drawings [Simplified illustration of the drawings] FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention; FIG. 2 is a preferred embodiment shown in FIG. Top view of the heat dissipation structure; FIG. 3 is a schematic view of the state of the semiconductor device before and after molding shown in FIG. 1; FIG. 4 is a cross-sectional view of the semiconductor device of the present invention when the mold is closed; FIG. 5 is another view of the present invention Cross-sectional view of a semiconductor device according to an embodiment; FIG. 6 is a cross-sectional view of a semiconductor device according to yet another embodiment of the present invention; FIG. 7 is a cross-sectional view of a conventional semiconductor device having a heat-dissipating structure; and FIG. 8 is US Patent No. 5, 9 77 , 62 is a cross-sectional view of the semiconductor device in case 6, and FIG. 9 is a cross-sectional view of the semiconductor device shown in FIG. 8 during the molding process. [Description of Symbols] 1 Semiconductor device 10 Substrate 1 (Γ Substrate 100 upper surface 11 adhesive 12 wafer 12a 'wafer 12a "wafer 12bf, wafer 120 upper surface 13 gold wire 13' solder bump 14 heat dissipation structure 14a first heat dissipation 14an first heat sink 14b second heat sink
16903.ptd 第14頁 122078316903.ptd Page 14 1220783
圖式簡單說明 14bn 第二散熱 件 140a 支撐部 140b 基部 141a 平坦部 141b 翼部 142a 頂面 142b 延伸部 143a 底面 15 封裝膠體 18 模具 180 模穴 31 基板 310 基板上表 面 32 晶片 320 上表面 33 散熱件 330 頂面 34 封裝膠體 35 封裝模具 350 模穴 51 頂面 Η 高度 h 深度 W! 距離 w2 南度和 16903.ptd 第15頁14bn second heat sink 140a support 140b base 141a flat 141b wing 142a top 142b extension 143a bottom 15 package gel 18 mold 180 cavity 31 substrate 310 substrate upper surface 32 wafer 320 upper surface 33 heat sink 330 Top surface 34 Encapsulated gel 35 Encapsulated mold 350 Cavity 51 Top surface Η Height h Depth W! Distance w2 South and 16903.ptd Page 15
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091119227A TWI220783B (en) | 2002-08-26 | 2002-08-26 | A semiconductor device having a heat-dissipating structure |
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| Application Number | Priority Date | Filing Date | Title |
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| TW091119227A TWI220783B (en) | 2002-08-26 | 2002-08-26 | A semiconductor device having a heat-dissipating structure |
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| TWI220783B true TWI220783B (en) | 2004-09-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811359A (en) * | 2012-11-13 | 2014-05-21 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811359A (en) * | 2012-11-13 | 2014-05-21 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
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