CN102097395A - 具有内嵌芯片的基板结构 - Google Patents

具有内嵌芯片的基板结构 Download PDF

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CN102097395A
CN102097395A CN2009102003554A CN200910200355A CN102097395A CN 102097395 A CN102097395 A CN 102097395A CN 2009102003554 A CN2009102003554 A CN 2009102003554A CN 200910200355 A CN200910200355 A CN 200910200355A CN 102097395 A CN102097395 A CN 102097395A
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chip
layer
embedded chip
board unit
board structure
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罗光淋
方仁广
孙骐
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Advanced Semiconductor Engineering Shanghai Inc
Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Shanghai Inc
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Abstract

本发明公开一种具有内嵌芯片的基板结构，所述基板结构包含一基板单元、至少一芯片及一覆盖层。所述基板单元的至少一表面设有一电路层，所述至少一芯片的一背面固定于所述基板单元的表面上，及所述至少一芯片的一有源表面的多个焊垫通过多个连接线电性连接所述基板单元的电路层的多个接垫，所述覆盖层设于所述基板单元的表面上且覆盖所述电路层、所述至少一芯片及所述多个连接线，以形成具有内嵌芯片的基板结构。由于连接线多为金线或铜线，其具有良好的延展性；并且，相对于凸块，本发明在所述连接线与所述焊垫或接垫的连接处相对牢固。因此，所述具有内嵌芯片的基板结构遇热胀冷缩或基板翘曲时，接垫不容易断开，具有较佳的可信赖性。

Description

具有内嵌芯片的基板结构
【技术领域】
本发明涉及一种具有内嵌芯片的基板结构，特别是涉及一种在基板单元的表面利用连接线电性连接内嵌芯片并具有覆盖层覆盖内嵌芯片的基板结构。
【背景技术】
现今，半导体封装产业为了满足各种高密度封装的需求，逐渐发展出各种不同型式的封装构造，其中各种不同的系统封装(system in package，SIP)设计概念常用于架构高密度封装构造。一般而言，系统封装可分为多芯片模块(multi chip module，MCM)、封装体上堆叠封装体(package on package，POP)及封装体内堆叠封装体(package in package，PIP)等。所述多芯片模块(MCM)是指在同一基板上布设数个芯片，在设置芯片后，再利用同一封装胶体包埋所有芯片，且依芯片排列方式又可将其细分为堆叠芯片(stacked die)封装或并列芯片(side-by-side)封装。再者，所述封装体上堆叠封装体(POP)的构造是指先完成一具有基板的第一封装体，接着再于第一封装体的封装胶体上表面堆叠另一完整的第二封装体，第二封装体会透过适当的转接组件电性连接至第一封装体的基板上，因而成为一复合封装构造。相较之下，所述封装体内堆叠封装体(PIP)的构造则是更进一步利用另一封装胶体将第二封装体、转接组件及第一封装体的原封装胶体等一起包埋固定在第一封装体的基板上，因而成为一复合封装构造。
然而，随着集成电路复杂度的增加，因而产生了在基板中内嵌芯片(embedded chip)的需求，尤其是在POP堆叠封装体的某些基板结构中加入内嵌式芯片是内存芯片发展的一个主要的技术方向。举例来说，请参照图1A所示，其揭示一种现有封装体上堆叠封装体(POP)的组合构造，其包含一第一封装体11及一第二封装体12，其中所述第一封装体11属于球栅阵列封装构造(ball grid array，BGA)，所述第二封装体12属于具有内嵌芯片的基板封装构造。所述第一封装体11的上表面承载堆叠芯片111，所述第一封装体11的下表面则结合数个锡球112。所述第二封装体12的内部嵌置一个芯片121，所述第二封装体12的下表面则结合数个锡球122。在堆叠时，利用所述第一封装体11的数个锡球112即可电性连接所述第一及第二封装体11、12，如此即可构成一封装体上堆叠封装体(POP)的组合构造。
请再参照图1B所示，其揭示图1A所示的一种现有具有内嵌芯片的基板(第二封装体12)结构的局部放大图，所述第二封装体12内部另设有一容置空间120，所述芯片121是一倒装芯片(flip chip)，其下表面是一有源表面，且所述有源表面设有数个凸块123，所述芯片121利用所述数个凸块123电性连接所述第二封装体12的数个接垫124。接着，再利用胶体125填满所述容置空间120，以包埋所述芯片121及凸块123。
然而，在现有具有内嵌芯片的基板结构中，其大多以金属电镀层的接垫124来连接芯片121与基板电路，因为材料属性的不同，芯片121的焊垫多为铝，基板电路的接垫124多为铜，基于不同材质的热膨胀系数(coefficient ofthermal expansion，CTE)不同，而容易在凸块123连接处产生信赖性(reliability)的问题。例如，基板遇热胀冷缩时容易使凸块123与接垫124的连接处断开；或因为基板本身较软，在产生翘曲(warpage)时也容易发生接垫124的连接处断开问题。
因此，有必要提供一种具有内嵌芯片的基板结构，以解决现有技术所存在的问题。
【发明内容】
本发明的主要目的是提供一种具有内嵌芯片的基板结构，其中基板单元的表面上设有电性连接内嵌芯片与电路层的连接线，并具有覆盖层以覆盖连接线与芯片，由于连接线具有良好延展性，故可以使基板遇热胀冷缩或翘曲时不容易发生连接处断开问题，因而有利于提高具有内嵌芯片的基板结构的可信赖性。
本发明的次要目的是提供一种具有内嵌芯片的基板结构，其中基板单元的表面上设有一凹槽，以容置更大尺寸的芯片，或者相对降低芯片高度，进而减少所述覆盖层的高度及基板整体的厚度。
本发明的再一目的是提供一种具有内嵌芯片的基板结构，其中覆盖层上另具有一电磁屏蔽层，因而可对基板内部的内嵌芯片进一步提供电磁屏蔽效果。
为达上述目的，本发明提供一种具有内嵌芯片的基板结构，所述基板结构包含一基板单元、至少一芯片及一覆盖层。所述基板单元的至少一表面设有一电路层，所述电路层具有多个接垫；所述至少一芯片的一背面固定于所述基板单元的表面上，及所述至少一芯片的一有源表面的多个焊垫通过多条连接线电性连接所述基板单元的电路层的多个接垫，所述覆盖层设于所述基板单元的表面上，且覆盖所述电路层、所述至少一芯片及所述多个连接线，以形成具有内嵌芯片的基板结构。
在本发明的一实施例中，所述覆盖层是一防焊层(solder mask)。
在本发明的一实施例中，所述防焊层是一环氧树脂防焊层。
在本发明的一实施例中，所述覆盖层是所述基板单元的一内绝缘层。
在本发明的一实施例中，所述内绝缘层是一预浸胶片层(prepreg)。
在本发明的一实施例中，所述覆盖层上另具有一电磁屏蔽层(electromagnetic interference shielding，EMI shielding)。
在本发明的一实施例中，所述覆盖层高度大于所述数条连接线的最大高度。
在本发明的一实施例中，所述基板单元的表面另设有一凹槽，以容置所述至少一芯片。
在本发明的一实施例中，所述基板单元另包含多个外露的接垫。
在本发明的一实施例中，所述外露的接垫电性连接于另一封装构造的一基板的多个锡球。
【附图说明】
图1A：一种现有封装体上堆叠封装体(POP)的组合构造图。
图1B：一种现有具有内嵌芯片的基板结构的局部放大图。
图2A及2B：本发明第一实施例的具有内嵌芯片的基板结构的制造方法流程示意图。
图3：本发明第一实施例的具有内嵌芯片的基板结构与另一基板迭置示意图。
图4：本发明第二实施例的具有内嵌芯片的基板结构示意图。
图5A至5C：本发明第三实施例的具有内嵌芯片的基板结构的制造方法流程示意图。
【具体实施方式】
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下：
请参照图2A及2B所示，其揭示本发明第一实施例的具有内嵌芯片的基板结构的制造方法流程，其用以完成一第一基板20，所述第一基板20适用于制作封装体上堆叠封装体(POP)的组合构造，但并不限于此。请参照图2A所示，所述制造方法的第一步骤是：提供一第一基板单元21，所述第一基板单元21可以是单层绝缘芯层或具有多层绝缘层与多层内电路层(未绘示)的复合层。所述第一基板单元21的上表面设置一第一电路层22a，下表面设置一第二电路层22b。所述第一电路层22a及所述第二电路层22b通常是图案化电路层。并且，所述第一基板单元21设有至少一导通孔或镀通孔(未标示)，以电性连接所述第一电路层22a及所述第二电路层22b。另外，所述制造方法的第二步骤是：将至少一芯片23设置于所述第一基板单元21的上表面(及/或下表面)，其中所述至少一芯片23的下表面是一背面(无源表面)，其利用液态胶或粘贴层(adhesive film)固定于所述第一基板单元21的上表面上。所述至少一芯片23的上表面是一有源表面(active surface)，其设有多个焊垫(未标示)。在本发明中，所述制造方法的第三步骤是：通过打线工艺以数条连接线24电性连接所述至少一芯片23的多个焊垫及所述第一基板单元21上表面的第一电路层22a(及/或下表面的第二电路层22b)，其中，所述数条连接线24可为金线、铜线或其他金属线材，其形状大约呈一向上的弧线或多角度弯折线。
请参照图2B所示，其揭示本发明第一实施例的具有内嵌芯片的基板结构的制造方法的第四步骤：分别形成一覆盖层25于所述第一基板单元21的上表面及下表面，以覆盖所述第一电路层22a及所述第二电路层22b，并同时覆盖所述至少一芯片23及所述多个连接线24。在本实施例中，所述覆盖层25是选自一阻焊层(solder mask)25。并且，通过现有图案化工艺处理所述阻焊层25，以图案化所述阻焊层25，进而形成数个开口外露出所述第一电路层22a(及/或第二电路层22b)的数个接垫26。其中所述阻焊层25优选是一种环氧树脂层(epoxy，俗称为绿漆)。并且，所述第一基板单元21上表面的阻焊层25高度必需大于所述数条连接线24的最大高度(弧线最高处)，以完全覆盖所述数条连接线24。
由于所述数条连接线24多为金线或铜线，其具有良好的延展性，即使在所述第一基板单元21翘曲时，所述数条连接线24本身不容易断裂，且在所述连接线24与所述芯片23的焊垫或所述第一电路层22a的接垫26之间的连接处相对牢固。因此，所述第一基板单元21遇热胀冷缩或翘曲时，所述芯片23与所述第一基板单元21之间的电性连接关系不容易受到影响，故具有较佳的可信赖性。
请再参照图3所示，其揭示本发明第一实施例的具有内嵌芯片的基板结构与另一基板迭置的示意图。本发明另提供一第二基板30，其下表面预先结合有数个锡球31，将所述第二基板30迭置于所述第一基板20之上，利用所述第二基板30的数个锡球31即可电性连接所述第一及第二基板20、30，如此即可构成一封装体上堆叠封装体(POP)的组合构造。所述第二基板30可以是任何种类的基板结构，例如所述第二基板30的上表面可能承载有其对应的芯片(未绘示)或在其内部嵌埋有对应的芯片(未绘示)；而所述第二基板30也可以是迭置于所述第一基板20之下方，或者也可以是二个所述第二基板30同时迭置于所述第一基板20之上方及下方，以构成封装体上堆叠封装体(POP)的组合构造。再者，虽然本发明第一实施例揭示的是所述第一基板20应用于封装体上堆叠封装体(POP)的组合构造，但本发明并不限于此。
请参照图4所示，其揭示本发明第二实施例的具有内嵌芯片的基板结构，本发明第二实施例相似于本发明第一实施例，并大致沿用相同的标号及名称。本发明第二实施例不同于第一实施例之处在于：所述第一基板单元21的上表面另设有至少一凹槽211，以容置所述至少一内嵌芯片23。所述凹槽211的宽度优选为大于或等于所述至少一芯片23的宽度，所述凹槽211的深度优选为小于或等于所述至少一芯片23的高度。因此，所述第一基板20可容置更大尺寸的所述至少一芯片23，或者所述第一基板20可相对降低所述芯片23的高度，进而减少所述阻焊层25的高度及所述第一基板20整体的厚度。
请参照图5A及5C所示，其揭示本发明第三实施例的具有内嵌芯片的基板结构的制造方法流程，其用以完成一基板40，所述基板40适用于制作封装体上堆叠封装体(POP)的组合构造，但并不限于此。请参照图5A所示，所述制造方法的第一步骤是：提供一基板单元41a，所述基板单元41a可以是单层绝缘芯层或具有多层绝缘层与多层内电路层(未绘示)的复合层，所述基板单元41a的上表面设置一第一电路层42a，下表面设置一第二电路层42b。所述第一电路层42a及第二电路层42b可以是图案化电路层。且所述基板单元41a开设有至少一导通孔或镀通孔(未标示)，以电性连接所述第一电路层42a及所述第二电路层42b。另外，所述制造方法的第二步骤是：将至少一芯片23设置于所述基板单元41a的上表面(及/或下表面)，其中所述至少一芯片43的上表面(有源表面)设有多个焊垫(未标示)，所述至少一芯片43的下表面(无源表面)与所述基板单元41a的上表面黏合。再者，所述制造方法的第三步骤是：通过打线工艺以数条连接线44电性连接所述至少一芯片43的多个焊垫及所述基板单元41a上表面的第一电路层42a(及/或下表面的第二电路层22b)，其中，所述数条连接线44可为金线、铜线或其他金属线材，其形状大约呈一向上的弧线或多角度弯折线。
请参照图5B所示，其揭示本发明第三实施例的具有内嵌芯片的基板结构的制造方法的第四步骤：分别形成一预浸胶片层(prepreg)41b及另一预浸胶片层41c于所述基板单元41a的上表面及下表面，分别覆盖所述第一电路层42a及所述第二电路层42b，特别说明的是，在本实施例中，所述预浸胶片层41b即是本实施例的覆盖层，并且于所述基板40制造完成后，所述覆盖层亦是所述基板单元41a的一内绝缘层。并对所述预浸胶片层41b及所述预浸胶片层41c进行钻孔，以裸露形成数个外露的接垫46。其中所述预浸胶片层41b及所述预浸胶片层41c是一种未固化的预浸材料胶片(prepreg)。并且，所述预浸胶片层41b的高度必需大于所述数条连接线44的最大高度(弧线最高处)，以便完全覆盖所述数条连接线44。以及，在所述预浸胶片层41b的上表面(外表面)设置一第三电路层42c，在所述预浸胶片层41c的下表面(外表面)设置一第四电路层42d，并图案化所述第三电路层42c及第四电路层42d。
请参照图5C所示，其揭示本发明第三实施例的具有内嵌芯片的基板结构的制造方法的第五步骤：分别形成阻焊层(solder mask)45于所述预浸胶片层41b的上表面及所述预浸胶片层41c的下表面，同时分别覆盖所述第三电路层42c及所述第四电路层42d。接着，并图案化所述阻焊层45，以曝露所述数个外露的接垫46。其中所述阻焊层45是一种环氧树脂层(绿漆)。
在本发明第三实施例中，所述预浸胶片层41b是一种未固化的预浸材料胶片，相较于第一实施例的阻焊层45，遇到当所述芯片43厚度或连接线弧线高度较高时，第一实施例的阻焊层45无法完全覆盖所述芯片或连接线，本发明第三实施例中预浸胶片层可提供较厚的覆盖厚度以满足此需求。
在本发明第三实施例中，除了所述第一电路层42a外，其它电路层的数量并没有限制，所述第二至第四电路层42b、42c、42d的任一层也可以是一种没有图案化的电路层。如图5C所示，所述第三及/或第四电路层42c、42d是未图案化的电路层，其相当于在所述预浸胶片层41b、41c(覆盖层)上另形成一电磁屏蔽层(electromagnetic interference shielding，EMI shielding)，故可用以产生电磁遮蔽的效果，以防止外来电磁波干扰所述芯片43，或防止所述芯片43的电磁波干扰外部电路或其他封装构造或电子装置。
综上所述，相较于图1B中现有的具有内嵌芯片的基板结构，由于以所述凸块123来连接所述芯片121与所述基板电路的接垫124，容易在所述第二封装体12的基板热胀冷缩或产生翘曲时造成所述凸块123与接垫124的连接处断开而产生信赖性的问题。图2至5C中本发明在所述第一基板单元21的上表面设有至少一芯片23，并通过打线工艺以数条连接线24电性连接所述至少一芯片23及所述第一基板单元21上表面的第一电路层22a，且通过一覆盖层(阻焊层25或预浸胶片层41b)覆盖所述数条连接线24，以形成具有内嵌芯片的基板结构，由于连接线多为金线或铜线，其具有良好的延展性，故可以使所述第一基板20遇热胀冷缩或翘曲时不容易在所述连接线24与所述芯片23的焊垫或所述第一基板单元21的第一电路层22a的接垫之间的连接处发生断开问题，因而有利于提高具有内嵌芯片的基板结构的可信赖性。再者，所述第一基板单元21的表面上也可设有一凹槽211，以容置更大尺寸的芯片23，或者相对降低所述芯片23的高度，进而减少所述覆盖层25的高度及所述第一基板20整体的厚度。另外，所述覆盖层(如所述预浸胶片层41b、41c)上亦可另具有一电磁屏蔽层(未图案化的第三及/或第四电路层42c、42d)，因而可对所述基板40内部的芯片43进一步提供电磁屏蔽效果。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (10)

1.一种具有内嵌芯片的基板结构，其特征在于：所述具有内嵌芯片的基板结构包含：
一基板单元，所述基板单元的至少一表面设有一电路层，所述电路层具有多个接垫；
至少一芯片，所述至少一芯片的一背面固定于所述基板单元的表面上，及所述至少一芯片的一有源表面的多个焊垫通过多个连接线电性连接所述基板单元的电路层的多个接垫；及
一覆盖层，所述覆盖层设于所述基板单元的表面上，所述覆盖层覆盖所述电路层、所述至少一芯片及所述多个连接线。
2.如权利要求1所述具有内嵌芯片的基板结构，其特征在于：所述覆盖层是一防焊层。
3.如权利要求2所述具有内嵌芯片的基板结构，其特征在于：所述防焊层是一环氧树脂防焊层。
4.如权利要求1所述具有内嵌芯片的基板结构，其特征在于：所述覆盖层是所述基板单元的一内绝缘层。
5.如权利要求4所述具有内嵌芯片的基板结构，其特征在于：所述内绝缘层是一预浸胶片层。
6.如权利要求4或5所述具有内嵌芯片的基板结构，其特征在于：所述覆盖层上另具有一电磁屏蔽层。
7.如权利要求1所述具有内嵌芯片的基板结构，其特征在于：所述覆盖层高度大于所述数条连接线的最大高度。
8.如权利要求1所述具有内嵌芯片的基板结构，其特征在于：所述基板单元的表面另设有一凹槽，以容置所述至少一芯片。
9.如权利要求1所述具有内嵌芯片的基板结构，其特征在于：所述基板单元另包含多个外露的接垫。
10.如权利要求9所述具有内嵌芯片的基板结构，其特征在于：所述多个外露的接垫电性连接于另一封装构造的一基板的多个锡球。
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