TWI269683B - Vertical removal of excess solder from a circuit substrate - Google Patents

Vertical removal of excess solder from a circuit substrate Download PDF

Info

Publication number
TWI269683B
TWI269683B TW093132652A TW93132652A TWI269683B TW I269683 B TWI269683 B TW I269683B TW 093132652 A TW093132652 A TW 093132652A TW 93132652 A TW93132652 A TW 93132652A TW I269683 B TWI269683 B TW I269683B
Authority
TW
Taiwan
Prior art keywords
solder
circuit substrate
sacrificial
excess
channels
Prior art date
Application number
TW093132652A
Other languages
English (en)
Other versions
TW200536646A (en
Inventor
William C Weigler
Robert Babula
James E Herbold
Thomas P Gall
Steven G Sharkey
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of TW200536646A publication Critical patent/TW200536646A/zh
Application granted granted Critical
Publication of TWI269683B publication Critical patent/TWI269683B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/018—Unsoldering; Removal of melted solder or other residues
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0101—Neon [Ne]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10204—Dummy component, dummy PCB or template, e.g. for monitoring, controlling of processes, comparing, scanning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/046—Means for drawing solder, e.g. for removing excess solder from pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

1269683 九、發明說明： 【發明所屬之技術領域】 本發明大體係關於印刷電路基板，且更特定言之係關於 預防再加工之印刷電路基板上的谭錫缺陷。 【先前技術】 在電子工業中使用印刷電路基板來置放及互連電子電 路。用於電子工業之印刷電路基板的實例包括··陶瓷基 板，印刷電路板；有彈性印刷電路；金屬上瓷美板 (P〇rxelain-on_metal substrate)及石夕上石夕基板 仙叫。此等電子電路在大型封裝中可包含昂貴的微處理 器或數位訊號處理器電路，此等大型封裝需要很多引腳而 連接至印刷電路基板。例如，一球狀晶格陣列（BGA)封裝 二用於此電路。此等BGA封裝通常藉由_表面黏著技術 (諸如使用熱空氣或諸如氮之其它熱氣體對—塊焊錫進行 迴焊操作）而電連接至一印刷電路基板。 洋5之，當自印刷電路基板至BGA引腳之焊錫連接直接 位於BGA封裝下方時，BGA封裝會導致某些製造困難。因 此，當焊錫不能在封裝下方移動以進行連接日寺，不能使用 標準焊錫波迴焊技術。而且，此等連接之密度相當大可導 致，接間之間距非常小，此會導致形成使連接共同電短路 之焊錫橋。結果’必須❹特殊裝配技術 球、印刷焊錫膏或預先置放於電路基板上且由—焊錫^ 工間刀離之桿錫凸塊。然後’將該bga封裝置放在錫膏、 焊錫凸塊或錫球上，且使用熱氣或諸如氮之其他熱氣體， 97073.doc 1269683 帝’、、、/心成以烙融該焊錫，從而將bGA引腳連接至印螂 *，基板連接處。雖然大多數bga黏著及修復技術使用熱 《來炫融知錫’對於單邊總成而言，有時使用在電路基 板下之熱板或加熱管來溶融焊錫。已用於局部炼融焊錫之 Ϊ它局部加熱電路基板之方法包括：紅外輻射；軟光束能 里’雷射光能量；及應用—諸如含氟化物之熱冷凝蒸汽 (如用於蒸汽迴焊系統）。 因為移除處理通常包括：重新加熱焊錫連接，及小心移 除4 BGA#置’所以當移除有缺陷之BGA封裝時，問題變 得更糟。若不正確地將BGA裝置自板上提起（即，橫向移 動發生），則會產生焊錫橋，f要進—步修復措施或廢棄 該電路基，。此外，在多個連接之間使用之焊錫遮罩，係 易碎且有彈) 生’而且若在移除bga封裝時，發生任何橫向 移動’則會知壞該焊錫遮罩。若該焊錫遮罩受到損壞，則 在再加工之電路基板上重新安裝一新的bga裝置，可能容 易導致產生-新的焊錫橋，需要進一步再加工。 先前技術之方法台枯·/由田 ,^ ^ 友匕祜·使用一切割線來移除該封裝，及 使H水射e然而’此等機械技術必定會毀壞該焊錫 料。迴焊該焊錫，以移除此部分，對該焊錫遮罩的毁壞 最小。然而，在移除BGA封裝之後，可能會留下過量之殘 留焊錫’此需要對電路基板進一步再加工，諸如使用技術 中所知之-銅編織谭錫毛細（㈤㈣c〇pper㈤如。 但此進一步再加工亦可能損壞焊錫遮罩。 口此而要種用於自一電路基板移除可導致焊錫橋之 97073.doc Ϊ269683 過量禪錫4損壞焊錫遮罩的改良技術 制招掄4* / 々而要提供對限 知壞檢向移動之潛在可能性的簡單而 _ 。® 1 卞 '^組操作的改 义°更有利的係使助同設備以用於將電路至 路基板或將電路自該基板斷開 ，“ 濟並保持處理控制。 了“移除技術更經 【實施方式】 ^明提供-㈣於自-電路基板移除過量剩餘焊錫而 貝展焊錫遮罩的改良技術。本發明亦提供_限制損壞橫 :移動之潛在可能性的簡單而容易的組操作。此外，用於 电路基板總成的相同設備亦可用於自印刷電路基板斷開電 路，而在保持處理控制的同時亦使本發明較經濟。 本發明不僅可用於球狀刪格陣列，亦可用於自任何精細 間距電子組件之再加工處移除過量焊錫。本發明亦可用於 BGA、微型BGA、晶片級封裝（csp)及覆晶裝置以及精細 間距四平包裝（QFP)與四平無引線（QFN)封裝。將本發明配 置成提供與將用於再加工之組件之佔據面積相匹配的通 道。因為典型BGA焊墊直徑範圍係自27 mil降至19 ， 所以對於此等封裝而言本發明之通道直徑大約為ι〇爪记。 然而，此尺寸BGA之通道直徑範圍可自1〇加丨至⑼mn 厚。此尺寸亦適用於QFP或QFN封裝。微BGA封裝可具有 小如12 mil之焊墊，且因此可使用更小之通道直徑。此尺 寸微BGA之SCS可自1〇 mil至30 mil厚。對於CSP及覆晶而 言’焊墊直徑係8至1 5 mil，且通道甚至可更小，其自5 mil至 18 mil厚。 97073.doc 1269683 圖1展示一諸如球狀删袼陣列（BGA)裝置之積體電路裝 置10至一印刷電路基板12(如一）的已知總成。焊錫丨4連接 個別BGA引腳至印刷電路基板12上之各自電焊墊18，該等 電焊墊具有運行至位於此項技術中已知之電路基板上或其 外部之其他電路的電跡線（未圖示）。在電谭墊丨8之間存在 一焊錫遮罩20。如技術中所已知，該焊錫遮罩2〇由一種排 斥熔融焊錫14之材料製成。因此，焊錫遮罩2〇可防止導致 電連接16、18短路之焊錫橋接，此短路會導致總成之電故 障而需對總成進行再加工且對BGA裝置1〇與（或）印刷電路 基板12進行有希望的修復。然而，應認識到··其它共同類 型之電路故障亦需對總成進行再加工。對於有彈性之電路 基板12而言，該焊錫遮罩2〇亦必須是有彈性的，從而導致 在再加工過程中，該焊錫遮罩2〇易受到損壞。 圖2展示移除該BGA裝置後之一典型印刷電路基板12。 通苇§ 一 BGA裝置焊接至一電路基板時，超過9〇%之焊錫 由忒BGA裝置供應，而只有不到1〇%來自沉積在該電路基 板上之焊錫膏。如所見，移除一裝置後，在該印刷電路基 板2之若干位置上，可能存在過量的焊錫14。過量焊錫的 里是不疋的，但通常約為原始量之50%，而再加工處理 僅需要10%。每個位置之過量焊錫的數量係可變的。雖然 希望在組件之重新裝配中，使一些焊錫留在該印刷電路基 2之電連接上’但是並不希望有過量的焊錫留了，因為如 ^面所解釋’上述會導致焊錫橋。圖3.5顯示根據本發 月 用於自一電路基板垂直移除過量之焊錫，以保護該 97073.doc 1269683 焊錫遮罩的系統》 圖3展示一置放於該印刷電路基板12之過量焊錫μ附 近，為矛多除該過量之焊錫14作準備的犧牲性電路基板 (SCS)30。該犧牲性電路基板3〇包括複數個金屬焊墊π。 該犧牲性電路基板3G最好亦包括複數個連接至該等焊塾％ 之通道32。該等通道可為各種形狀，但圓柱形較佳。通 常，如該技藝中所熟知，該電路基板由薄且有彈性的材料 (諸如FR4)製成。該犧牲性電路基板％亦可與該電路基板 12相似，由諸如FR4之薄且有彈性的材料製成。然而，較 佳在一諸如樹脂浸潰玻璃織物（resin_impregnated d咖 weave)之剛性基板中提供犧牲性電路基板3〇，此在此項技 術中是已知的而且比有彈性FR4便宜許多。通道W通常係 穿過板30而形成之通孔且以與所移除之裝置之引腳之模式 相匹配的模式配置。舉例而言，一遍封裝以對應於電二 基板12之焊墊18之位置㈣㈣成規律地㈣彡丨腳。犧牲 性電路基板3 G之焊墊3 8及通道3 2可類似地㈣成—陣列以 與電路基板12上之複數個過量焊錫14凸塊對準。 每一焊墊38及通道32之一部分上安置有谭錫可潤濕材料 34。銅或銅合金通常用作焊錫可潤濕材料34。較佳將焊墊 38及通道32鍍金來保持其焊錫可潤濕特性之完整性。然 而，亦可同樣使用其他焊錫可潤濕材料及合金。犧牲性電 路基板30之通道32包括利用焊錫可潤濕材料電鍍之通孔 34。烊塾38以及可選通道32與通孔％配置成提供所要量之 過量焊錫毛細作用，此將在下文詳細說明。 97073.doc 1269683 歸因於過量焊錫凸塊14之不均勻特性，犧牲板3〇之焊墊 3 8將不能與過量焊錫凸塊完全接觸。然而，一旦迴焊，將 與過量焊錫凸塊14完全接觸。而且，犧牲性電路基板3〇在 電路基板12上之置放對準並非關鍵的，因為如圖&中所示 迴焊之焊錫凸塊將用於對準以上兩者。 圖4展示迴焊總成上之犧牲性電路基板之操作。具體言 之，犧牲性電路基板30之複數個焊墊38及通道32係位於電 路基板12之過量焊錫14垂直附近，從而藉由毛細作用將過 量焊錫垂直傳送至焊塾38及通道32上，且接著進入犧牲性 電路基板30之通道32的通孔36。提供一熱源％來加熱過量 焊錫至液態。該熱源較佳係—諸如空氣或氮之熱源來迴焊 過量焊錫。迴焊焊錫14將黏附至谭墊38及通道取谭錫可 潤濕表面34,且表㈣力藉由—毛細（毛細）作用將使過量 焊鍚Μ進人通道32。為了移除大多數過量焊心是在電路 12之焊墊18上留下預定量之焊錫以允許附著—新的部件 (例如BGA裝置），給定焊錫可㈣表面34之材料以及供執 之量及時間而選擇通道、通孔及焊墊之直徑。 … 社一較侄貫施例 _ - w八·堂及 iS* λ： 應助_輔助焊錫可潤濕材料之可潤湯性。更奸: =應-真空源4。來進一步辅助過量焊錫之毛細作二 道之真空罩殼42來供應真空，或可藉㈣ 他適虽方式來向每一通道供應真空。將 ^ 過量焊錫液體相對的通 、、供應至輿 入通道。所使…^ 辅料錫藉由毛細作用進 吏用的真1可控制在過量焊錫藉由毛細作用 97073.doc 1269683 進入通道後在電路基板上剩餘焊錫之殘餘量。可供應真空 以使得焊錫部分延仲$ ^ ^ 八· |刀之伸至通孔中、完全進入通孔中或甚至延 伸超過通孔之頂端。 圖5展示垂直移除犧牲性電路基板14後之印刷電路基板 12。垂直移除可採用或不採用所供應之真空來執行（如圖 示），但是焊錫必須為液態。焊墊38及通道32保留過量焊 錫15 ’纟中在移除處理後留下預定量之剩餘焊錫μ。對於 有彈性電路基板而言，焊錫遮罩極易受到損壞。因此，犧 牲性電路基板14垂直提昇以防止焊錫遮罩受到損壞，此會 便利新裝置至電路基板之適當裝配而不會損壞焊錫橋構 成，並且在電路基板12之焊墊18上保留適當量之剩餘焊錫 14。而且，垂直移除減少了電路基板受到污染之可能性。 在移除後，可再加工犧牲性電路基板以進一步使用。然 而’安置犧牲板係更經濟的。 本發明亦包含一種用於自一電路基板垂直移除過量焊錫 之方法。參照圖6，該方法包括提供具有複數個焊墊及可 選通道之犧牲性電路基板的第一步驟60。較佳情況係，電 路基板為一有彈性電路板及犧牲性電路基板為一剛性電路 板。然而，犧牲性電路基板亦可為有彈性或剛性的。每個 焊墊及通道之一部分上安置有焊錫可潤濕材料。具體言 之’此步驟60包括提供連接至具有藉由焊錫可潤濕材料電 鍍之通孔之通道的焊墊。 較佳情況係，下一步驟62包括施加助炫劑至犧牲性電路 基板或需再加工處。 97073.doc 12 1269683 下一步驟64包括將犧牲性電路基板之複數個焊墊及通道 置放於電路基板之過量焊錫之垂直附近。 下一步驟66包括加熱過量焊錫至液態。較佳包括使用熱 空氣或者諸如氮之其他熱氣體來迴焊過量焊錫。與用於 BGA移除類似之-焊錫迴焊溫度分佈使得過量焊錫變為液 體且潤濕犧牲性電路基板之焊墊及通道。 下一步驟68包括藉由毛細作用將過量焊錫垂直傳送至焊 墊上並進入犧牲性電路基板之可選通道中。在匕步驟較佳包 括施加真空至此等通道以輔助焊錫藉由毛細作用進入通道 之通孔中，但是此步驟可藉由通道中之焊錫的毛細作用而 不需要真空來實現。 下-步驟70包括當焊錫為液態時自電路基板之附近垂直 提昇犧牲性電路基板。為此目的可使用之前—步雜之真 空。舉例而言’當焊錫為液態時’使用真空作用提昇犧牲 性電路基板。垂直進行提以防止對電路基板之焊錫遮罩 造成損壞。事務上，將提供步驟6〇之焊墊、通道及通孔之 直控配置成使得在毛細作用6 8及提昇步驟7 〇後在電路基板 上留下所要剩餘量之焊錫。 本务明之以上描述僅為例示性的但並不意欲限制自此申 叫案頒發之任何專利的範疇。本發明意為僅受下列申請專 利範圍之廣泛範疇所限制。 【圖式簡單說明】 圖1係此項技術中已知的BGA裝置及印刷電路基板總成 之橫截面圖； 97073.doc -13- 1269683 圖2係一 BGA裝置之典型焊錫迴焊移除後圖丨所示之印刷 電路基板的橫截面圖； 圖3根據本發明置放於圖2之印刷電路基板之過量焊錫附 近之一犧牲性電路基板的橫截面圖； 圖4係根據本發明之圖3之迴焊總成上的犧牲性電路基板 之操作的橫截面圖； 圖5係根據本發明在移除犧牲電路板後之圖4之印刷電路 基板的橫截面圖； 圖6係根據本發明之方法的流程圖。 雖然本發明易受不同之修改及替代形式的影響，但是已 在附圖中以實例方式展示特定實施例並將於本文中詳細描 述。然而，應瞭解本發明並不意欲限於所揭示之特殊形 式。相反，本發明涵蓋屬於由附加申請專利範圍界定之本 發明之廣泛範疇的所有修改、均等物及替代物。 【主要元件符號說明】 10 積體電路裝置/BGA裝置 12 印刷電路基板 14 焊錫凸塊 15 過量焊錫 16 電連接 18 電焊墊 20 焊錫遮罩 30 犧牲性電路基板 32 通道 97073.doc 14

Claims (1)

1269683 十、申請專利範圍： 1· 種用於自一電路基板垂直移除過量焊錫之方法，該方 法包含以下步驟： 提供一具有複數個焊墊之犧牲性電路基板，每個焊墊 之一部分上配置有一焊錫可潤濕材料； 將該犧牲性電路基板之該等複數個焊墊垂直置放於該 電路基板之該過量焊錫附近； 加熱該過量焊錫變成液態； 該過量焊錫藉由垂直毛細毛細作用至該犧牲性電路基 板之該等焊墊上；及 萄該焊錫處於液態時 牲性電路基板。 2.如請求们之方法，其中該電路基板是有彈性的，且立 中該提供之步驟包括：提供—堅硬的犧牲性電路基板Γ 來：二:1之方法’其中該加熱步驟包括··使用熱氣體 來迴焊該過量焊錫。 4· 之方法’其中該提供之步驟：包括提供連接 ;、=之焊錫可潤濕通道，該等通道包括藉由一焊錫 了 /閏濕材料電鍍之通孔。 5·如請求項4之方法’其中該毛細 藉由主4 A π ^ ^從·该焊錫 、、、田乍用進入該等通道之該等通孔中。 6 ·如晴求項4之：、、土 〇+ 彳等料、通道及通孔之直 破配置，以在該毛細作用步驟及該 在該電路基板上留下-剩餘量之焊錫。驟之後， 97073.doc 1269683 7 ·如明求項4之方法，其中該毛細作用步驟：包括使該等 通道成為真空狀悲，以輔助該焊錫藉由毛細作用進入該 等通道。 8·如請求項1之方法，進一步包含對該犧牲性電路基板施 加助熔劑之步驟。 •種用於自一電路基板垂直移除過量焊錫之系統，該系 統包含： 一用於加熱該過量焊錫變成液態之熱源； 一具有複數個通道之犧牲性電路基板，每個通道之一 ^刀上配置有纟干錫可潤濕材料，該等通道配置，以與該 电路基板上之複數個過量焊錫凸塊對準，該犧牲性電路 土板之4等複數個通道被垂直安置於該電路基板之該過 量焊錫之附近，以藉由毛細作用使該過量焊錫垂直進入 5亥犧牲性電路基板之該等通道内；及 施加至該電路基板之助熔劑。 士明求項9之系統，其中該犧牲性電路基板之該等通道 匕括·-電艘焊錫可潤濕材料之通孔，及連接至該等通 2之蛘錫可潤濕材料所形成之焊墊，且進一步包含一真 ^ 了中β亥真空源被應用於與該過量焊錫液體相對之 、μ、I通孔以輔助該焊錫藉由毛細作用進入該等通 道’忒真空源及該等通道配置，以在該過量焊錫藉由毛 作用進入该等通道之後，在該電路基板上留下一剩餘 量之焊錫。 97073.doc
TW093132652A 2003-10-28 2004-10-28 Vertical removal of excess solder from a circuit substrate TWI269683B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/695,187 US7353983B2 (en) 2003-10-28 2003-10-28 Vertical removal of excess solder from a circuit substrate

Publications (2)

Publication Number Publication Date
TW200536646A TW200536646A (en) 2005-11-16
TWI269683B true TWI269683B (en) 2007-01-01

Family

ID=34522732

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093132652A TWI269683B (en) 2003-10-28 2004-10-28 Vertical removal of excess solder from a circuit substrate

Country Status (7)

Country Link
US (1) US7353983B2 (zh)
EP (1) EP1687114A4 (zh)
KR (1) KR100810462B1 (zh)
CN (1) CN1874868A (zh)
CA (1) CA2541977A1 (zh)
TW (1) TWI269683B (zh)
WO (1) WO2005044499A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007033074A1 (de) 2007-07-13 2009-01-15 Pac Tech-Packaging Technologies Gmbh Verfahren und Vorrichtung zur Entfernung von Lotmaterialdepots von einem Substrat
FR2924839B1 (fr) * 2007-12-06 2010-03-19 Agematis Procede de sauvegarde automatique de donnees numeriques conservees en memoire dans une installation informatique, support de donnees lisible par un ordinateur, installation informatique et systeme pour la mise en oeuvre de ce procede
KR101104352B1 (ko) * 2009-12-23 2012-01-16 (주)솔리드메카 Ｂｇａ 패키지 테스트용 인터포저 ｐｃｂ 고정방법
JP2012160310A (ja) * 2011-01-31 2012-08-23 Fujitsu Component Ltd 表面実装部品及び製造方法
US9123860B2 (en) * 2012-08-01 2015-09-01 Flextronics Ap, Llc Vacuum reflow voiding rework system
CN103819956A (zh) * 2014-03-01 2014-05-28 陈廷 用于覆铜板覆盖金属箔的笔
US10362720B2 (en) 2014-08-06 2019-07-23 Greene Lyon Group, Inc. Rotational removal of electronic chips and other components from printed wire boards using liquid heat media
CN104470262A (zh) * 2014-10-24 2015-03-25 成都博芯联科科技有限公司 一种基于焊锡熔接技术的三维电路层间连接方法
US10269762B2 (en) * 2015-10-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Rework process and tool design for semiconductor package
CN110958787A (zh) * 2020-01-07 2020-04-03 珠海元盛电子科技股份有限公司 一种多层互联fpc预设锡膏的焊接方法
US11963307B2 (en) * 2021-03-30 2024-04-16 International Business Machines Corporation Vacuum-assisted BGA joint formation
US11948807B2 (en) * 2021-03-30 2024-04-02 International Business Machines Corporation Feature selection through solder-ball population

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3050612A (en) * 1960-10-26 1962-08-21 Ralph M Eversole Desoldering tip
US3580462A (en) * 1967-12-14 1971-05-25 Louis Vanyi Soldering apparatus
US3618846A (en) * 1969-02-17 1971-11-09 Patrick J Poli Manually operated suction device
US3661315A (en) * 1969-06-13 1972-05-09 North American Rockwell Material removing device
US3751799A (en) * 1972-04-26 1973-08-14 Ibm Solder terminal rework technique
DE2529554A1 (de) * 1975-07-02 1977-01-20 Siemens Ag Verfahren und vorrichtung zum abloeten von halbleiterbausteinen in flip- chip-technik
US4632294A (en) * 1984-12-20 1986-12-30 International Business Machines Corporation Process and apparatus for individual pin repair in a dense array of connector pins of an electronic packaging structure
JPH01192466A (ja) * 1988-01-28 1989-08-02 Fujitsu Ltd はんだ除去プレート
US4923521A (en) * 1988-10-11 1990-05-08 American Telephone And Telegraph Company Method and apparatus for removing solder
US4877175A (en) * 1988-12-30 1989-10-31 General Electric Company Laser debridging of microelectronic solder joints
US5072873A (en) * 1990-05-03 1991-12-17 Motorola, Inc. Device for solder removal
US5143272A (en) * 1991-07-09 1992-09-01 Metcal, Inc. Desoldering device
US5227589A (en) 1991-12-23 1993-07-13 Motorola, Inc. Plated-through interconnect solder thief
US5305941A (en) * 1992-12-28 1994-04-26 Plato Products, Inc. Desoldering wick
US5282565A (en) 1992-12-29 1994-02-01 Motorola, Inc. Solder bump interconnection formed using spaced solder deposit and consumable path
JP2508415B2 (ja) * 1993-05-25 1996-06-19 日本電気株式会社 半田除去装置
US5392980A (en) 1993-12-29 1995-02-28 Dell Usa, L.P. Method and apparatus for reworking ball grid array packages to allow reuse of functional devices
TW336371B (en) 1995-07-13 1998-07-11 Motorola Inc Method for forming bumps on a substrate the invention relates to a method for forming bumps on a substrate
JPH09260835A (ja) 1996-03-18 1997-10-03 Sony Corp はんだ付け装置
US5934545A (en) * 1997-02-21 1999-08-10 Gordon; Thomas A. Ball placement method and apparatus for forming a ball grid array
US5921462A (en) * 1997-02-21 1999-07-13 Gordon; Thomas A. Ball grid array ball placement method and apparatus
US5929518A (en) 1997-07-20 1999-07-27 Motorola, Inc. Circuit board and method
US6156408A (en) 1997-08-29 2000-12-05 Motorola, Inc. Device for reworkable direct chip attachment
US6569248B1 (en) * 2000-09-11 2003-05-27 Allen David Hertz Apparatus for selectively applying solder mask
US6719188B2 (en) 2001-07-24 2004-04-13 International Business Machines Corporation Rework methods for lead BGA/CGA

Also Published As

Publication number Publication date
KR100810462B1 (ko) 2008-03-07
EP1687114A1 (en) 2006-08-09
KR20060073648A (ko) 2006-06-28
TW200536646A (en) 2005-11-16
US7353983B2 (en) 2008-04-08
CA2541977A1 (en) 2005-05-19
US20050087588A1 (en) 2005-04-28
WO2005044499A1 (en) 2005-05-19
CN1874868A (zh) 2006-12-06
EP1687114A4 (en) 2008-10-29

Similar Documents

Publication Publication Date Title
KR100257420B1 (ko) 결합 재료 범프에 의해 상호접속되는 시스템
JP3480826B2 (ja) 電子モジュール製造方法、基板間接合方法、円錐形状半田形成方法、及び基板
JP3202903B2 (ja) 基板上にソルダ・ボールを形成する方法
KR100555395B1 (ko) 무세척 플럭스를 사용한 플립칩 상호 접속
EP0473929B1 (en) Method of forming a thin film electronic device
TWI269683B (en) Vertical removal of excess solder from a circuit substrate
CA2302907C (en) Plaster solder array using injection molded solder
JPH0750725B2 (ja) チップ接続構造体
JPH09214121A (ja) ハンダによるコラム・グリッド・アレー相互接続を有する回路ボード上に実装されたマイクロエレクトロニクス集積回路及びコラム・グリッド・アレー作成方法
JP4720438B2 (ja) フリップチップ接続方法
JPH04504230A (ja) 半田付けされた物品を製造するための方法
US5115964A (en) Method for bonding thin film electronic device
US6413849B1 (en) Integrated circuit package with surface mounted pins on an organic substrate and method of fabrication therefor
US6375060B1 (en) Fluxless solder attachment of a microelectronic chip to a substrate
JP4946965B2 (ja) 電子部品実装装置及びその製造方法
JPH0737890A (ja) 半田ボール接合装置およびその接合方法
JP4102538B2 (ja) 電子回路基板補修方法
JPH0983128A (ja) 半導体モジュールの接合構造
JPH09186162A (ja) 金属バンプの形成方法
JPH09270428A (ja) はんだバンプ形成方法
WO1999017593A1 (en) Fluxless laser reflow with template for solder balls of bga packaging
JP3997614B2 (ja) 実装ハンダ付け方法
MXPA06004663A (en) Vertical removal of excess solder from a circuit substrate
JP2005203664A (ja) 半導体装置の実装方法
WO1999017595A1 (en) Solder ball placement with flux, template and laser tag