TWI261318B - Method for dicing wafer stacks to provide access to interior structures - Google Patents

Method for dicing wafer stacks to provide access to interior structures Download PDF

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Publication number
TWI261318B
TWI261318B TW091133648A TW91133648A TWI261318B TW I261318 B TWI261318 B TW I261318B TW 091133648 A TW091133648 A TW 091133648A TW 91133648 A TW91133648 A TW 91133648A TW I261318 B TWI261318 B TW I261318B
Authority
TW
Taiwan
Prior art keywords
wafer
stack
slit
composition
cutting
Prior art date
Application number
TW091133648A
Other languages
English (en)
Chinese (zh)
Other versions
TW200303046A (en
Inventor
Peter G Hartwell
David Horsley
Storrs T Hoen
Jonah A Harley
Original Assignee
Hewlett Packard Co
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co, Agilent Technologies Inc filed Critical Hewlett Packard Co
Publication of TW200303046A publication Critical patent/TW200303046A/zh
Application granted granted Critical
Publication of TWI261318B publication Critical patent/TWI261318B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00865Multistep processes for the separation of wafers into individual elements
    • B81C1/00873Multistep processes for the separation of wafers into individual elements characterised by special arrangements of the devices, allowing an easier separation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dicing (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
TW091133648A 2002-02-01 2002-11-18 Method for dicing wafer stacks to provide access to interior structures TWI261318B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/066,213 US6955976B2 (en) 2002-02-01 2002-02-01 Method for dicing wafer stacks to provide access to interior structures

Publications (2)

Publication Number Publication Date
TW200303046A TW200303046A (en) 2003-08-16
TWI261318B true TWI261318B (en) 2006-09-01

Family

ID=22068009

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091133648A TWI261318B (en) 2002-02-01 2002-11-18 Method for dicing wafer stacks to provide access to interior structures

Country Status (4)

Country Link
US (2) US6955976B2 (https=)
EP (1) EP1333485A3 (https=)
JP (1) JP2003234311A (https=)
TW (1) TWI261318B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9937601B2 (en) 2003-11-13 2018-04-10 Applied Materials, Inc. Retaining ring with Shaped Surface

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DE10232190A1 (de) * 2002-07-16 2004-02-05 Austriamicrosystems Ag Verfahren zur Herstellung eines Bauelements mit tiefliegenden Anschlußflächen
DE10322751B3 (de) * 2003-05-19 2004-09-30 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung eines in Kunststoff verschlossenen optoelektronischen Bauelementes
US7183622B2 (en) * 2004-06-30 2007-02-27 Intel Corporation Module integrating MEMS and passive components
US7422962B2 (en) * 2004-10-27 2008-09-09 Hewlett-Packard Development Company, L.P. Method of singulating electronic devices
US7344956B2 (en) * 2004-12-08 2008-03-18 Miradia Inc. Method and device for wafer scale packaging of optical devices using a scribe and break process
US7282425B2 (en) * 2005-01-31 2007-10-16 International Business Machines Corporation Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
DE102006033502A1 (de) 2006-05-03 2007-11-15 Osram Opto Semiconductors Gmbh Strahlungsemittierender Halbleiterkörper mit Trägersubstrat und Verfahren zur Herstellung eines solchen
US7808061B2 (en) * 2006-07-28 2010-10-05 Hewlett-Packard Development Company, L.P. Multi-die apparatus including moveable portions
US7892891B2 (en) * 2006-10-11 2011-02-22 SemiLEDs Optoelectronics Co., Ltd. Die separation
US8030754B2 (en) 2007-01-31 2011-10-04 Hewlett-Packard Development Company, L.P. Chip cooling channels formed in wafer bonding gap
US20080181558A1 (en) 2007-01-31 2008-07-31 Hartwell Peter G Electronic and optical circuit integration through wafer bonding
KR100826394B1 (ko) * 2007-05-17 2008-05-02 삼성전기주식회사 반도체 패키지 제조방법
US7662669B2 (en) * 2007-07-24 2010-02-16 Northrop Grumman Space & Mission Systems Corp. Method of exposing circuit lateral interconnect contacts by wafer saw
US7972940B2 (en) * 2007-12-28 2011-07-05 Micron Technology, Inc. Wafer processing
JPWO2010061470A1 (ja) * 2008-11-28 2012-04-19 セイコーインスツル株式会社 ウエハおよびパッケージ製品の製造方法
WO2010070753A1 (ja) * 2008-12-18 2010-06-24 セイコーインスツル株式会社 ウエハおよびパッケージ製品の製造方法
TWI513668B (zh) * 2009-02-23 2015-12-21 精工電子有限公司 玻璃密封型封裝的製造方法及玻璃基板
JP2012186532A (ja) 2011-03-03 2012-09-27 Seiko Instruments Inc ウエハ、パッケージの製造方法、及び圧電振動子
CN102744795A (zh) * 2011-04-21 2012-10-24 菱生精密工业股份有限公司 晶圆切割方法
TW201243930A (en) * 2011-04-21 2012-11-01 Lingsen Precision Ind Ltd Wafer dicing method
JP5875267B2 (ja) * 2011-07-11 2016-03-02 株式会社ディスコ 積層ウェーハの加工方法
US8980676B2 (en) * 2012-06-25 2015-03-17 Raytheon Company Fabrication of window cavity cap structures in wafer level packaging
CN104340952A (zh) * 2013-08-09 2015-02-11 比亚迪股份有限公司 Mems圆片级真空封装方法及结构
TW202516601A (zh) 2018-09-06 2025-04-16 德克薩斯大學系統董事會 用於三維ics和可配置asics的奈米製造和設計技術
SE546936C2 (en) 2021-10-15 2025-03-11 Skechers Usa Inc Ii A shoe comprising a heel cup attached to an interior compressible layer

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Publication number Priority date Publication date Assignee Title
EP0137988B1 (en) * 1983-08-31 1989-11-29 Texas Instruments Incorporated Infrared imager
JP3584635B2 (ja) * 1996-10-04 2004-11-04 株式会社デンソー 半導体装置及びその製造方法
US6436793B1 (en) * 2000-12-28 2002-08-20 Xerox Corporation Methods of forming semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9937601B2 (en) 2003-11-13 2018-04-10 Applied Materials, Inc. Retaining ring with Shaped Surface

Also Published As

Publication number Publication date
TW200303046A (en) 2003-08-16
US6955976B2 (en) 2005-10-18
EP1333485A3 (en) 2005-11-30
US20050191791A1 (en) 2005-09-01
EP1333485A2 (en) 2003-08-06
US20030148553A1 (en) 2003-08-07
US7042105B2 (en) 2006-05-09
JP2003234311A (ja) 2003-08-22

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MM4A Annulment or lapse of patent due to non-payment of fees