CN103493189B - 用于切割电器件的支承体的方法 - Google Patents
用于切割电器件的支承体的方法 Download PDFInfo
- Publication number
- CN103493189B CN103493189B CN201280019178.XA CN201280019178A CN103493189B CN 103493189 B CN103493189 B CN 103493189B CN 201280019178 A CN201280019178 A CN 201280019178A CN 103493189 B CN103493189 B CN 103493189B
- Authority
- CN
- China
- Prior art keywords
- supporting mass
- groove
- width
- cutter sweep
- incorporated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 33
- 239000000463 material Substances 0.000 claims abstract description 54
- 230000011218 segmentation Effects 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 238000003754 machining Methods 0.000 claims 1
- 238000005192 partition Methods 0.000 abstract description 3
- 230000005611 electricity Effects 0.000 description 17
- 238000004880 explosion Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000011230 binding agent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
- Pressure Sensors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Processing Of Stones Or Stones Resemblance Materials (AREA)
Abstract
在用于电器件(30)的支承体(10)中,在所述支承体的第一表面(O10a)上将沟槽(20)引入到所述支承体(10)的材料中。所述支承体(10)被切穿,其方式是将切痕(60)从支承体(10)的与第一表面对置的第二表面(O10b)引入到所述支承体的材料中。切割引导进行为使得切痕(60)在支承体的第一表面(O10a)上通过沟槽(20)走向。通过将沟槽(20)设置在支承体(10)的表面附近的材料层中,可以避免分割部件(1,2)时材料从支承体(10)破裂出来。
Description
本发明涉及一种用于切割、尤其是锯割电器件的支承体的方法,其中将布置在支承体上的部件分割。
电部件在大面积的支承体(所谓的晶片)上制造。电部件包括关联的支承体,在所述支承体上设置有电器件和接触端子用于施加或截取电压。在制造电部件时,晶片首先具有多个部件,所述多个部件并排地设置在大面积的支承体上。为了将部件分割,将切痕设置在支承体的材料中。为此可以锯开晶片。为了在部件分割时避免部件的器件损坏,器件必须与锯痕有足够距离地布置。
所希望的是,说明一种用于切割电器件的支承体的方法,其中供支承体上的器件使用的面积尽可能大。此外,要说明一种电部件,所述部件根据上述方法制造。
所述用于切割电器件的支承体的方法的实施形式和借助所述方法制造的电器件的实施形式可以从权利要求中得到。
根据一个实施形式,用于切割电器件的支承体以将电器件分割的方法包括提供电器件的支承体。沟槽在支承体的第一表面上引入到所述支承体的材料中。所述支承体被切穿,其方式将切痕从支承体的与第一表面对置的第二表面引入到所述支承体的材料中,其中,切痕引导进行为使得切痕在支承体的第一表面上通过沟槽地走向。
支承体可以在两侧具有有效面(aktive Flaechen)。例如电器件可以布置在支承体的第一表面上,而在支承体的与第一表面对置的第二表面上可以布置接触端子,例如可以布置焊料凸块。接触端子可以通过支承体的材料中的穿通接触部来与所述器件连接。第二表面也可以装配有其他器件,例如有源/无源电路、传感器区域或者检测器。所述器件可以是CMOS技术中的器件。为了分割布置在支承体上的部件,借助切割装置将支承体切穿。切割装置可以是锯片。为了锯穿支承体,将切割装置设置在支承体的第二表面上。
通过设置在支承体的第一表面上的沟槽,最大程度地避免了在从第二表面出发来切穿支承体的材料时支承体第一表面上的支承体材料的破碎和爆裂。锯路宽度表示相邻地设置在支承体上的、属于不同部件的两个器件之间的必要距离。与其中在第一表面上的支承体材料中没有设置沟槽并且其中必要的锯路宽度例如为80μm的支承体相比,通过把沟槽引入到支承体的第一表面中,可以根据晶片/器件的厚度来明显地减小锯路宽度,例如减小到50μm或者更小。由此可以明显增大在第一表面上用于布置电器件的面。
电部件的一个实施形式包括带有电器件的支承体,所述电器件布置在支承体的第一表面上。支承体在该支承体的第一表面的边缘上具有切口,所述切口通过将沟槽引入支承体中而引起。
以下借助示出本发明的实施例的附图更为详尽地阐明本发明。其中:
图1示出了用于切割电器件支承体的方法的一个实施形式;
图2示出了借助在支承体表面上的锯路中引入沟槽来切割电器件支承体的方法的另一实施形式;
图3示出了用于切割电器件支承体的方法的另一实施形式,其中借助引入通过支承体的切痕来将部件分离;
图4在放大的视图中示出了引入支承体中的沟槽的一个实施形式;
图5示出了用于切割支承体的方法的一个实施形式,其中带有引入支承体表面中的沟槽;
图6示出了电部件的一个实施形式,其带有引入支承体表面中的切口。
为了制造电部件,在支承体上、例如硅构成的晶片上布置有多个部件。为了分割部件,借助切割装置来切穿晶片。
图1示出了用于切割电部件1、2的支承体10的方法的一个实施形式。电部件1、2的每个都包括支承体10的一部分、电器件30和接触端子40。器件30例如可以是用CMOS技术制造的芯片器件。电器件30可以包含有源组件和/或无源组件,例如电感、电容器或者表面波滤波器。电器件30布置在支承体10的表面O10a上。接触端子40布置在支承体10的与表面O10a对置的表面O10b上。器件30与接触端子40之间的连接通过支承体10的材料中的穿通接触部实现。晶片10在表面O10b上还可以具有其他部件30。表面O10a上设置有锯割膜50,所述锯割膜50覆盖表面O10a和器件30。该膜可以用粘合剂涂覆并且可以一件式地粘贴到整个支承体10上。
为了分割电部件1、2,用切割装置100切穿支承体10。切割装置100例如可以构建为带有锯片的锯装置。驱动装置200使得锯片运动。为了分割电部件,锯片100被设置在支承体的表面O10b上并且切痕60被引入支承体30中。锯片100的切割引导使得将支承体10的材料完全切穿。锯割膜没有被完全地分开。在分割之后,各部件1、2由此附着在膜50上。
在锯开支承体10时,当锯片从表面附近的材料层显现时,在表面O10a上出现材料块从支承体10的材料的折断。在表面O10b上通过锯片而出现切痕60周围的大约10μm范围内的表面损坏,而在表面O10a上出现支承体10的材料的较大爆裂。由于材料的爆裂和损坏,在表面O10a上距切痕60的两侧大约100μm距离中的平面不能够用作有效面来设置器件。出于安全性原因,例如锯路宽度设定在180μm到250μm之间,其不用作在表面O10a上装备器件的面。
在图2和图3中示出了用于切割支承体10以分割电部件1、2、3和4的方法的另一实施形式。支承体10可以是由硅材料构成的晶片,所述晶体包含多个部件。每个部件都包括支承体10的一部分、电器件30和用于施加和截取电压的接触端子40。部件可以两侧地具有有效面。电器件30例如可以布置在支承体10的表面O10a上。在支承体10的与表面O10a对置的表面O10b上可以布置接触端子40例如焊料凸块,和/或布置其他电器件30。通过在支承体内部的穿通接触部70,电器件30可以与接触端子40连接。器件30例如可以用CMOS技术制造。所述器件可以包含有源组件和无源组件,例如电容器、电感或者表面波滤波器。
为了分割电部件1、2、3和4而将支承体10的材料切穿。在切穿整个支承体10之前,在支承体的表面O10a上将沟槽20引入到支承体10的材料中。所述沟槽例如可以通过机械加工方法、例如通过锯割来引入到支承体的材料中。为此,可以将驱动装置200与切割装置100a耦合。切割装置例如可以具有锯片100a,所述锯片具有宽度B100a,例如具有15μm到80μm之间的宽度。优选的是,切割装置100a具有40μm的宽度。锯路宽度于是例如可以为45μm。沟槽通过锯入表面O10a而引入到晶片中。在该预锯割工艺中,没有完全地切穿支承体,而是仅仅去除了支承体的表面附近的层。
为了将沟槽20引入支承体10的材料中,替代锯割可以使用刻蚀方法。沟槽例如可以通过干法刻蚀引入支承体10的材料中。为此使用相应的掩膜。所述掩膜例如具有支承体的宽度。
在引入沟槽时,支承体固定在膜50上。膜50可以施加在支承体的表面O10b上。膜例如可以是涂覆有粘合剂的膜。所述膜优选布置在支承体的表面O10b上,使得接触端子40沉入膜的材料中并且由此完全被膜的材料包围,其中所述接触端子例如可以构建为具有80μm的高度的焊料球。此外,膜直接附着在支承体的表面O10b上,并且尤其是在支承体的边缘上近似为不透气地致密附着,使得可以避免表面O10b由于污物颗粒或者水导致的污染。
图3示出了分割部件1、2、3和4的步骤。为此,膜50布置在支承体的表面O10a上以及布置在器件30上。所述膜例如可以用粘合剂涂覆并且粘贴到表面O10a和器件30上。
切割装置100b与驱动单元200耦合。为了分割部件1、2、3和4,支承体10被切割装置100b分开。为了切穿支承体10,切割装置100b设置在支承体的表面O10b上。切割装置100b可以具有锯片宽度为25μm的锯片,这大致对应于30μm的锯路宽度。切割装置100b在表面O10a上的定位在此以一定位精度来实现。该定位精度可以在±10μm之间,并且优选在±5μm之间。在切穿支承体10的材料时,在支承体10的材料中形成切痕60。切割装置100b在表面O10b上侵入支承体的材料中,并且在表面O10a上又出现。切割引导进行为使得切痕60通过表面O10a上的沟槽20走向。在一个优选的实施形式中,切割引导居中地通过沟槽20走向。在部件分割之后,单个部件1、2、3和4附着在膜50上并且可以从膜上取下。
通过在支承体10的表面O10a上引入沟槽20,可以在很大程度上避免在表面附近的材料层的区域内锯穿支承体10时材料的爆裂。相对于图1示出的实施形式,由此可以缩小不同部件的电器件30之间的所需距离。表面O10a上的要保持未被使用的区域例如可以减小到50μm。
图4在放大的视图中示出了沟槽20的一个实施形式。沟槽20具有宽度B20和深度T20。引入支承体10的材料中的切痕60具有宽度B60,其中宽度B60基本上对应于锯片B100的宽度。沟槽20例如可以相对于支承体10的材料中的切痕60的切割引导而居中地走向。当在锯穿支承体时,锯片100在沟槽20内中央地从支承体10的材料突出时,实现了这一点。
沟槽20的宽度可以根据切痕60的宽度B60或者锯片100b的宽度B100来选择。锯片100a可以实施为比锯片100b更宽,使得沟槽例如比锯装置的锯片100b的宽度B100b宽10μm到30μm。由此,沟槽比用于分开晶片的切痕宽。此外,沟槽的宽度还可以附加地根据定位精度来选择,其中以所述定位精度将切割装置100b设置到支承体10的表面O10b上。沟槽20例如可以以宽度B20引入到支承体10的材料中,其中所述宽度B20对应于锯片100B或者切痕60的宽度B100b加上切割装置100b的定位精度。当借助切割装置100a引入沟槽时,切割装置的宽度B100a可以相应地选择。
当锯片B100b例如具有10μm到50μm之间的宽度B100b并且定位精度在±5μm之间时,沟槽20可以具有15μm到80μm之间的宽度B20。证明为特别有利的是,在支承体10的材料中设置宽度大于20μm的沟槽,优选是宽度为40μm的沟槽。为此,锯片的宽度B100a例如可以为40μm。沟槽可以以超过10μm的深度T20并且优选以20μm的深度从表面010a出发引入支承体10的材料中。
图5示出了在分割前的支承体10的一个实施形式。在支承体的材料中,沟槽20棋盘式地布置在支承体10的表面O10a上。沟槽可以分别相对于彼此成直角地走向。为了分割电部件,支承体10从与表面O10a对置的表面O10b出发由切割装置(例如锯片)切穿。当锯片完全地切穿了支承体10的材料并且通入沟槽20中时,可以几乎完全地防止来自表面O10a的材料块的爆裂。不能用于装备表面O10a的面通过沟槽20的宽度而预先给定。由此,与没有沟槽20的实施形式相比,可以明显地减小在两个部件之间要保持未被使用的面。
图6示出了分割之后的电部件1的一个实施形式。电部件1具有布置在支承体10的表面O10a上的器件30。在表面O10b上例如布置有接触端子40、传感器区域,检测器或者其他的有源/无源器件。接触端子40通过支承体10的材料中的穿通接触部70与器件30连接。该部件在表面O10a和O10b之间具有侧面S10。
支承体10在表面O10a的边缘R10a上具有切口80,所述切口通过沟槽引起。切口可以构建为在支承体10的材料中的中断。切口布置在部件1的表面O10a和侧面S10之间。切口80具有大约沟槽20的宽度B20减去切痕60的宽度B60的一半宽度。它可以例如具有超过10μm的宽度B20’和超过10μm的深度T20。
附图标记表
1 电部件
10 支承体
20 沟槽
30 电器件
40 接触端子
50 膜
60 切痕
70 穿通接触部
80 切口
100a,100b 切割装置,锯片
200 驱动装置
Claims (15)
1.一种用于切割电器件的支承体的方法,包括:
-提供电器件(30)的支承体(10),
-将电器件(30)设置在支承体(10)的第一表面(O10a)上,
-在支承体的第一表面(O10a)上将沟槽(20)引入支承体(10)的材料中,
-将膜(50)设置在支承体(10)的第一表面(O10a)上,
-通过从与支承体(10)的第一表面对置的第二表面(O10b)将切痕(60)引入到支承体的材料中来切穿支承体(10)以便分割电器件(30),其中切割引导进行为使得切痕在支承体的第一表面(O10a)上通过沟槽(20)走向,
其中将具有如下宽度(B20)的沟槽(20)引入到支承体的材料中:所述宽度比切痕(60)的宽度(B60)更大,
其中,在所述分割之后,所述电器件(30)附着在膜(50)上。
2.根据权利要求1所述的方法,
-其中借助切割装置(100b)将切痕(60)引入到支承体的材料中,
-其中以定位精度将切割装置(100b)设置到支承体的第二表面(O10b)上,
-其中沟槽(60)的宽度对应于切割装置(100b)的宽度加上所述定位精度,其中以所述定位精度将切割装置(100b)设置到支承体的第二表面(O10b)上。
3.根据权利要求2所述的方法,
-其中使用锯片作为切割装置(100b),
-其中切割装置(100b)的锯片的宽度(B100b)选择为使得切痕具有10μm到50μm之间的宽度(B60)。
4.根据权利要求3所述的方法,其中切割装置(100b)的定位精度在±5μm之间。
5.根据权利要求3所述的方法,
-其中切割装置(100b)的锯片的宽度(B100b)选择为使得切痕具有30μm的宽度(B60)。
6.根据权利要求3或4所述的方法,
-其中借助具有锯片的另一切割装置(100a)将沟槽(20)引入到支承体(10)的材料中,
-其中所述另一切割装置(100a)的锯片的宽度(B100a)选择为使得将宽度(B20)在15μm到80μm之间的沟槽(20)引入到支承体(10)的材料中。
7.根据权利要求6所述的方法,
-其中所述另一切割装置(100a)的锯片的宽度(B100a)选择为使得将宽度(B20)为40μm的沟槽(20)引入到支承体(10)的材料中。
8.根据权利要求1至4之一所述的方法,其中将深度(T20)超过10μm的沟槽(20)引入到支承体(10)的材料中。
9.根据权利要求8所述的方法,其中将深度(T20)超过20μm的沟槽(20)引入到支承体(10)的材料中。
10.根据权利要求1至4之一所述的方法,包括:
将接触端子(40)设置在支承体(10)的第二表面(O10b)上。
11.根据权利要求1至4之一所述的方法,其中通过刻蚀方法或者通过机械加工方法,将沟槽(20)引入到支承体(10)的材料中。
12.根据权利要求11所述的方法,其中通过干法刻蚀将沟槽(20)引入到支承体(10)的材料中。
13.根据权利要求11所述的方法,其中通过锯割将沟槽(20)引入到支承体(10)的材料中。
14.根据权利要求1至4之一所述的方法,其中支承体(10)构建为晶片。
15.根据权利要求14所述的方法,其中支承体(10)构建为由硅材料构成的晶片。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102011018295.0 | 2011-04-20 | ||
DE102011018295.0A DE102011018295B4 (de) | 2011-04-20 | 2011-04-20 | Verfahren zum Schneiden eines Trägers für elektrische Bauelemente |
PCT/EP2012/057009 WO2012143353A1 (de) | 2011-04-20 | 2012-04-17 | Verfahren zum schneiden eines trägers für elektrische bauelemente |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103493189A CN103493189A (zh) | 2014-01-01 |
CN103493189B true CN103493189B (zh) | 2016-11-23 |
Family
ID=45974346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201280019178.XA Active CN103493189B (zh) | 2011-04-20 | 2012-04-17 | 用于切割电器件的支承体的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9961777B2 (zh) |
CN (1) | CN103493189B (zh) |
DE (1) | DE102011018295B4 (zh) |
WO (1) | WO2012143353A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2908335B1 (en) | 2014-02-14 | 2020-04-15 | ams AG | Dicing method |
EP2913848A1 (en) | 2014-02-27 | 2015-09-02 | ams AG | Dicing method |
DE102015110429A1 (de) * | 2015-06-29 | 2017-01-12 | Osram Opto Semiconductors Gmbh | Optoelektronische Leuchtvorrichtung |
US10269756B2 (en) * | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1453857A (zh) * | 2002-04-24 | 2003-11-05 | 三洋电机株式会社 | 混合集成电路装置的制造方法 |
CN1531071A (zh) * | 2003-03-13 | 2004-09-22 | ������������ʽ���� | 半导体装置及其制造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3817600C2 (de) * | 1987-05-26 | 1994-06-23 | Matsushita Electric Works Ltd | Verfahren zur Herstellung einer Halbleitervorrichtung mit einem keramischen Substrat und einem integrierten Schaltungskreis |
US5128282A (en) | 1991-11-04 | 1992-07-07 | Xerox Corporation | Process for separating image sensor dies and the like from a wafer that minimizes silicon waste |
US5656547A (en) | 1994-05-11 | 1997-08-12 | Chipscale, Inc. | Method for making a leadless surface mounted device with wrap-around flange interface contacts |
KR100462980B1 (ko) * | 1999-09-13 | 2004-12-23 | 비쉐이 메저먼츠 그룹, 인코포레이티드 | 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정 |
DE10356885B4 (de) * | 2003-12-03 | 2005-11-03 | Schott Ag | Verfahren zum Gehäusen von Bauelementen und gehäustes Bauelement |
US7129114B2 (en) * | 2004-03-10 | 2006-10-31 | Micron Technology, Inc. | Methods relating to singulating semiconductor wafers and wafer scale assemblies |
US7268012B2 (en) * | 2004-08-31 | 2007-09-11 | Micron Technology, Inc. | Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby |
US7265034B2 (en) * | 2005-02-18 | 2007-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade |
JP2007311378A (ja) * | 2006-05-16 | 2007-11-29 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
US7435664B2 (en) * | 2006-06-30 | 2008-10-14 | Intel Corporation | Wafer-level bonding for mechanically reinforced ultra-thin die |
US8629532B2 (en) * | 2007-05-08 | 2014-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor wafer with assisting dicing structure and dicing method thereof |
JP2008288285A (ja) * | 2007-05-15 | 2008-11-27 | Sharp Corp | 積層基板の切断方法、半導体装置の製造方法、半導体装置、発光装置及びバックライト装置 |
US7553752B2 (en) * | 2007-06-20 | 2009-06-30 | Stats Chippac, Ltd. | Method of making a wafer level integration package |
CN102825802A (zh) | 2007-08-21 | 2012-12-19 | 约翰·D·布拉什公司 | 桶状防火箱及其制造方法 |
US7674689B2 (en) * | 2007-09-20 | 2010-03-09 | Infineon Technologies Ag | Method of making an integrated circuit including singulating a semiconductor wafer |
US20090166844A1 (en) * | 2007-12-26 | 2009-07-02 | Xuejiao Hu | Metal cover on flip-chip matrix-array (fcmx) substrate for low cost cpu assembly |
JP5108496B2 (ja) * | 2007-12-26 | 2012-12-26 | 三洋電機株式会社 | 回路基板およびその製造方法、回路装置およびその製造方法 |
US7622365B2 (en) * | 2008-02-04 | 2009-11-24 | Micron Technology, Inc. | Wafer processing including dicing |
US8110441B2 (en) * | 2008-09-25 | 2012-02-07 | Stats Chippac, Ltd. | Method of electrically connecting a shielding layer to ground through a conductive via disposed in peripheral region around semiconductor die |
US9136144B2 (en) * | 2009-11-13 | 2015-09-15 | Stats Chippac, Ltd. | Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation |
-
2011
- 2011-04-20 DE DE102011018295.0A patent/DE102011018295B4/de active Active
-
2012
- 2012-04-17 US US14/112,233 patent/US9961777B2/en active Active
- 2012-04-17 WO PCT/EP2012/057009 patent/WO2012143353A1/de active Application Filing
- 2012-04-17 CN CN201280019178.XA patent/CN103493189B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1453857A (zh) * | 2002-04-24 | 2003-11-05 | 三洋电机株式会社 | 混合集成电路装置的制造方法 |
CN1531071A (zh) * | 2003-03-13 | 2004-09-22 | ������������ʽ���� | 半导体装置及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2012143353A1 (de) | 2012-10-26 |
DE102011018295B4 (de) | 2021-06-24 |
US9961777B2 (en) | 2018-05-01 |
CN103493189A (zh) | 2014-01-01 |
US20140118974A1 (en) | 2014-05-01 |
DE102011018295A1 (de) | 2012-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110574151B (zh) | 用于形成微电子系统或器具的方法 | |
US7554211B2 (en) | Semiconductor wafer and manufacturing process for semiconductor device | |
CN103493189B (zh) | 用于切割电器件的支承体的方法 | |
US7316940B2 (en) | Chip dicing | |
JP2011525055A (ja) | 半導体ダイ分離方法 | |
TW201620094A (zh) | 半導體邊界保護密封劑 | |
US7541218B2 (en) | Wafer-level chip package process | |
US9070672B2 (en) | Semiconductor device packaging structure and packaging method | |
CN102668050A (zh) | 穿硅过孔保护环 | |
US10269640B2 (en) | Method for singulating packaged integrated circuits and resulting structures | |
US20160111255A1 (en) | Separation of Chips on a Substrate | |
CN106467289B (zh) | 晶圆结构及晶圆加工方法 | |
KR101192526B1 (ko) | 웨이퍼로부터 반도체 칩을 제조하기 위한 방법 및 반도체 구성 요소 | |
US20200144205A1 (en) | Semiconductor device, semiconductor device assembly and method for manufacturing semiconductor device assembly | |
US8048717B2 (en) | Method and system for bonding 3D semiconductor devices | |
CN1159075A (zh) | 用于减少芯片空间的沟槽划线 | |
CN105720007B (zh) | 电子封装结构及其制法 | |
KR20110077485A (ko) | 웨이퍼 가공 방법 | |
CN111696968B (zh) | 半导体结构的制造方法 | |
CN114078713A (zh) | 半导体装置的制造方法及半导体装置 | |
CN111211118A (zh) | 半导体装置以及半导体芯片 | |
CN103811536A (zh) | 圆片级封装工艺晶圆减薄结构 | |
TWI726279B (zh) | 半導體封裝裝置 | |
KR20160034099A (ko) | 인쇄회로기판 및 이를 포함하는 전자부품 패키지 | |
KR101847948B1 (ko) | 웨이퍼 절단 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |