TWI251864B - Production process for semiconductor apparatus - Google Patents

Production process for semiconductor apparatus Download PDF

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Publication number
TWI251864B
TWI251864B TW091135256A TW91135256A TWI251864B TW I251864 B TWI251864 B TW I251864B TW 091135256 A TW091135256 A TW 091135256A TW 91135256 A TW91135256 A TW 91135256A TW I251864 B TWI251864 B TW I251864B
Authority
TW
Taiwan
Prior art keywords
photoresist layer
semiconductor device
manufacturing
film
substrate
Prior art date
Application number
TW091135256A
Other languages
English (en)
Chinese (zh)
Other versions
TW200305923A (en
Inventor
Shinobu Isobe
Original Assignee
Umc Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Umc Japan filed Critical Umc Japan
Publication of TW200305923A publication Critical patent/TW200305923A/zh
Application granted granted Critical
Publication of TWI251864B publication Critical patent/TWI251864B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
TW091135256A 2002-04-26 2002-12-05 Production process for semiconductor apparatus TWI251864B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002127488A JP2003324104A (ja) 2002-04-26 2002-04-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200305923A TW200305923A (en) 2003-11-01
TWI251864B true TWI251864B (en) 2006-03-21

Family

ID=29541583

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091135256A TWI251864B (en) 2002-04-26 2002-12-05 Production process for semiconductor apparatus

Country Status (3)

Country Link
US (1) US6881656B1 (enExample)
JP (1) JP2003324104A (enExample)
TW (1) TWI251864B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20250016843A (ko) * 2023-07-26 2025-02-04 에스케이하이닉스 주식회사 메모리 장치 및 이의 제조방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679610A (en) * 1994-12-15 1997-10-21 Kabushiki Kaisha Toshiba Method of planarizing a semiconductor workpiece surface
US6858909B2 (en) * 2002-11-29 2005-02-22 International Business Machines Corporation CMP assisted liftoff micropatterning

Also Published As

Publication number Publication date
US6881656B1 (en) 2005-04-19
JP2003324104A (ja) 2003-11-14
TW200305923A (en) 2003-11-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees