CN103280403A - 双栅氧器件的制造方法 - Google Patents

双栅氧器件的制造方法 Download PDF

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CN103280403A
CN103280403A CN2013101775775A CN201310177577A CN103280403A CN 103280403 A CN103280403 A CN 103280403A CN 2013101775775 A CN2013101775775 A CN 2013101775775A CN 201310177577 A CN201310177577 A CN 201310177577A CN 103280403 A CN103280403 A CN 103280403A
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photoresist
dual gate
gate oxide
manufacture method
oxide layer
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CN103280403B (zh
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黄君
毛智彪
崇二敏
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Shanghai Huali Microelectronics Corp
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Abstract

本发明公开了一种双栅氧器件的制造方法包括在沉积了氧化层薄膜的衬底上涂布光刻胶;经过去除部分光刻胶,暴露出需要进行刻蚀的氧化层薄膜第一区域;在剩余光刻胶上涂布化学微缩材料,并加热;引入紫外光照射步骤S03处理后的光刻胶表面;刻蚀第一区域,去除剩余光刻胶,得到不同厚度的氧化层薄膜,形成双栅氧结构。本发明可以有效地提高刻蚀前光刻胶表层的致密性,提高抗酸性溶液浸蚀能力,降低光刻胶在湿法刻蚀过程中产生缺陷的几率;采用化学微缩材料和紫外线照射可以最大程度地减小工艺对线宽的影响。

Description

双栅氧器件的制造方法
技术领域
本发明涉及半导体制造领域,尤其涉及一种双栅氧器件的制造方法。
背景技术
随着半导体技术的发展,往往需要在一个集成电路芯片上集成多个功能器件,而多个功能器件一般需要对应设置不同的场效应晶体管(FETs)。多栅氧(multiple gate oxide)工艺是在同一芯片内制作多个不同场效应晶体管的常用方法。
现有技术已经提供了多种实现多栅氧的工艺,图1A至图1D显示了双栅氧(dual gateoxide)的一种现有制作工艺流程。如图1A所示,在已经形成浅隔绝沟道12并且沉积了氧化硅薄膜13的硅片11上涂布光刻胶14;图1B中,曝光和显影后暴露出待刻蚀的薄区域15,受到光刻胶14保护的厚区域16;再参阅图1C,采用湿法刻蚀工艺,完全去除待刻蚀的薄区域15的氧化硅薄膜;接着如图1D所示,去除剩余的光刻胶14后,再次沉积氧化硅,在氧化硅薄膜13的薄区域15和厚区域16上形成不同厚度的氧化硅层,即所谓的双栅氧结构。在薄区域15和厚区域16上,可以制作出不同的场效应晶体管。
如上述传统工艺中,湿法刻蚀氧化硅薄膜13的工艺是将沉积了氧化硅薄膜13的硅片11置于酸性溶液中,其中,常用的酸性溶液比如氢氟酸(HF)。酸性溶液在刻蚀氧化硅薄膜13的同时也会对光刻胶14产生作用,形成工艺缺陷,主要的工艺缺陷包括光刻胶残留和碳化硅(SiC)沉积。具体来说,形成光刻胶残留缺陷是因为酸性溶液会浸蚀光刻胶,将光刻胶薄膜中的部分高分子化合物从光刻胶薄膜中剥离出来,导致在硅片表面形成缺陷;碳化硅沉积缺陷的形成机理是,氢氟酸与氧化硅反应会生成六氟化硅(SiF6),六氟化硅与光刻胶薄膜中的高分子化合物进一步反应会生成碳化硅微粒,然后在硅片上形成沉积。
为解决上述技术问题,现有的防止湿法刻蚀过程中产生光刻胶缺陷的方法包括:1)在光刻曝光和显影后对光刻胶薄膜进一步烘培,形成更加致密的光刻胶薄膜,使得湿法刻蚀的酸性溶液难以从光刻胶高分子化合物之间的缝隙浸入,与光刻胶高分子化合物作用生成缺陷;2)在光刻曝光和显影后对光刻胶薄膜进行紫外光(UV)固化处理,在光刻胶表面形成高分子化合物的交联,交联的高分子表面可以有效地提高光刻胶的抗酸性溶液浸蚀能力。
然而,上述现有防止湿法刻蚀过程中产生光刻胶缺陷的方法仍然存在一些需要解决的问题。在第1种方法中,烘培温度不宜太高,烘培时间不宜太长,否则会导致光刻胶图形变形,而且会对生产吞吐量(throughput)产生不利影响;此外,由于受到烘培温度和烘培时间的限制,烘培后光刻胶薄膜的致密性可能还不能满足抗酸性溶液浸蚀的要求。在第2种方法中,需要在光刻工艺之后加入紫外光(UV)固化工艺,紫外光(UV)固化工艺对光刻胶图案的厚度和线宽会产生收缩作用,通常光刻胶的缩小率会达到15%~25%,显影后的线宽会缩小10~30纳米,影响器件线宽和质量。
发明内容
本发明针对这些问题,提出了采用化学微缩材料(RELACS,Resolution EnhancementLithography Assisted by Chemical Shrink)在显影机台内对显影后的光刻胶图形进行化学固化处理和紫外光照射的工艺,可以在光刻胶表面完全形成高分子交联的保护膜,既能满足抗酸性溶液浸蚀的要求,同时,由于采用化学微缩材料的化学固化处理会使线宽增加10~20纳米,而采用紫外线照射处理的固化方法会使线宽缩小10~30纳米,这样的相互补偿可以最大程度地减小工艺对器件线宽的影响,从而得到一种制造双栅氧器件的方法。
其中,本发明实施例所用的化学微缩材料(RELACS)是安智电子材料公司(AZElectronic Materials USA Corp.)为缩小沟槽或孔图形尺寸开发的商用材料。如美国专利US7745077B2中记载的式(I)化合物以及美国专利US7923200B2中记载的式(II)化合物。
其中,式(I)中R1至R5分别选自氢或C1-C6烷基,W选自C1-C6烷基;式(II)中R1选自氢、C1-C4烷基、C1-C6烷基醇、羟基(OH)、胺(NH2)、羧酸或酰胺(CONH2),
Figure BDA00003186563800022
代表与聚合物相连,m=1-6,n=1-4。
本发明双栅氧器件的制造方法包括以下步骤:
步骤S01,在沉积了氧化层薄膜的衬底上涂布光刻胶;
步骤S02,经过曝光和显影去除部分光刻胶,暴露出需要进行刻蚀的氧化层薄膜第一区域,未被去除的剩余光刻胶下的氧化层薄膜为第二区域;
步骤S03,在剩余光刻胶上涂布化学微缩材料,并加热,使化学微缩材料与光刻胶表面反应形成高分子交联的保护膜;
步骤S04,引入紫外光照射步骤S03处理后的光刻胶表面,加强固化光刻胶表面的高分子交联保护膜;
步骤S05,刻蚀去除该第一区域的氧化层薄膜,去除剩余光刻胶;
步骤S06,再次沉积一层氧化层薄膜,得到不同厚度的氧化层,形成双栅氧结构。
进一步地,步骤S01中光刻胶为适合I线光刻工艺、248纳米光刻工艺、193纳米光刻工艺或EUV光刻工艺的光刻胶。
进一步地,步骤S03中化学微缩材料是含烷基氨基的水溶性高分子材料。优选的,该水溶性高分子材料为含烷基氨基的丙烯酸酯或甲基丙烯酸酯高分子材料。
进一步地,步骤S03中加热温度为80至180℃,加热时间为15至300秒。优选的,加热温度为90至170℃,加热时间为30至120秒。
进一步地,步骤S04中紫外光的光波波长为280至330纳米,紫外光的烘焙温度为100至180℃。
进一步地,该氧化层薄膜为氧化硅,该衬底为硅。
进一步地,步骤S03中加热后还包括去除多余的化学微缩材料,步骤S03和S04均使用与步骤S02相同的显影机台。
进一步地,该去除包括用去离子水或含表面活性剂的去离子水溶液去除。
进一步地,步骤S05中刻蚀为湿法刻蚀。
本发明提供的双栅氧器件的制造方法,可以有效地提高刻蚀前光刻胶表层的致密性,从而提高抗酸性溶液浸蚀能力,降低光刻胶在湿法刻蚀过程中产生缺陷的几率;同时,由于采用化学微缩材料的化学固化处理会使线宽增加10-20纳米,而采用紫外线照射的固化方法会使线宽缩小10-30纳米,这样的相互补偿可以最大程度地减小工艺对线宽的影响,从而改善现有工艺对器件质量的不利影响。本发明的制造方法工艺简单,适合于工业生产。
附图说明
为能更清楚理解本发明的目的、特点和优点,以下将结合附图对本发明的较佳实施例进行详细描述,其中:
图1A至图1D是现有工艺步骤中的器件结构示意图;
图2A至图2E是本发明双栅氧器件的制造方法第一实施例的器件结构示意图。
具体实施方式
第一实施例
请参阅图2A至图2E,本实施例的双栅氧器件的制造方法包括以下步骤:
步骤S01,在已经形成浅隔绝沟道22并沉积了氧化硅薄膜23的硅衬底21上涂布光刻胶24,如图2A所示,其中,该光刻胶为适合I线光刻工艺的光刻胶。
步骤S02,经过曝光和显影去除部分光刻胶,暴露出需要进行刻蚀的氧化硅薄膜第一区域25,未被去除的剩余光刻胶下的氧化硅薄膜为第二区域26,如图2B所示;
步骤S03,在与步骤S02同一显影机台内,在剩余光刻胶上涂布化学微缩材料,并在120℃的温度下加热60秒以固化光刻胶图形,使化学微缩材料与光刻胶表面反应形成部分高分子交联的保护膜27,用去离子水去除多余的化学微缩材料,如图2C所示;其中,本实施例的化学微缩材料选用安智电子材料公司的RELACS产品R607或SH-114,该产皮市售可得;
步骤S04,在同一个显影机台内,引入一道波长为300纳米的紫外光(UV)照射步骤S03处理后的光刻胶表面,烘焙温度为120℃,加强固化光刻胶表面,与光刻胶表面反应完全形成高分子交联的保护膜,此时,由于采用化学微缩材料的化学固化处理会使线宽增加10-20纳米,而采用紫外线照射处理的固化方法会使线宽缩小10-30纳米,这样的相互补偿可以最大程度地减小工艺对线宽的影响;
步骤S05,用本领域常规的湿法刻蚀工艺,完全去除第一区域25的氧化硅薄膜,其中,如图2E所示;
步骤S06,去除剩余光刻胶后,在硅片上再次沉积一层氧化硅薄膜,从而得到不同厚度的氧化硅,形成双栅氧结构,如图2E所示;
步骤S07,在第一区域25和第二区域26上制作不同的场效应晶体管。
在实际应用中,光刻胶可以选用其他适合于I线光刻工艺、248纳米光刻工艺、193纳米光刻工艺、EUV光刻工艺的光刻胶;化学微缩材料可以是其他含烷基氨基的水溶性高分子材料,如美国专利US7745077B2中记载的式(I)化合物以及美国专利US7923200B2中记载的式(II)化合物;加热温度和时间以及紫外光的波长和烘焙温度可以根据实际工艺器件和条件,在本发明内容中的优选范围内进行调节。
此外,本发明的发明点在于如何通过化学微缩材料和紫外光照射来固化光刻胶材料,以避免现有工艺对光刻胶和器件的腐蚀等不利影响的产生,因此,本发明所述如浅隔绝沟道的形成、曝光、显影、涂布、照射、刻蚀、沉积等步骤方法均可参照现有工艺。

Claims (9)

1.一种双栅氧器件的制造方法,其特征在于,包括以下步骤:
步骤S01,在沉积了氧化层薄膜的衬底上涂布光刻胶;
步骤S02,经过曝光和显影去除部分光刻胶,暴露出需要进行刻蚀的氧化层薄膜第一区域,未被去除的剩余光刻胶下的氧化层薄膜为第二区域;
步骤S03,在剩余光刻胶上涂布化学微缩材料,并加热,使化学微缩材料与光刻胶表面反应形成高分子交联的保护膜;
步骤S04,引入紫外光照射步骤S03处理后的光刻胶表面,加强固化光刻胶表面的高分子交联保护膜;
步骤S05,刻蚀去除该第一区域的氧化层薄膜,去除剩余光刻胶;
步骤S06,再次沉积一层氧化层薄膜,得到不同厚度的氧化层,形成双栅氧结构。
2.根据权利要求1所述的双栅氧器件的制造方法,其特征在于:步骤S01中光刻胶为适合I线光刻工艺、248纳米光刻工艺、193纳米光刻工艺或EUV光刻工艺的光刻胶。
3.根据权利要求1所述的双栅氧器件的制造方法,其特征在于:步骤S03中化学微缩材料是含烷基氨基的水溶性高分子材料。
4.根据权利要求3所述的双栅氧器件的制造方法,其特征在于:该水溶性高分子材料为含烷基氨基的丙烯酸酯或甲基丙烯酸酯高分子材料。
5.根据权利要求1所述的双栅氧器件的制造方法,其特征在于:步骤S03中加热温度为80至180℃,加热时间为15至300秒。
6.根据权利要求5所述的双栅氧器件的制造方法,其特征在于:加热温度为90至170℃,加热时间为30至120秒。
7.根据权利要求1所述的双栅氧器件的制造方法,其特征在于:步骤S04中紫外光的光波波长为280至330纳米,紫外光的烘焙温度为100至180℃。
8.根据权利要求1所述的双栅氧器件的制造方法,其特征在于:该氧化层薄膜为氧化硅,该衬底为硅。
9.根据权利要求1所述的双栅氧器件的制造方法,其特征在于:步骤S03中加热后还包括用去离子水或含表面活性剂的去离子水溶液去除多余的化学微缩材料;步骤S03和S04均使用与步骤S02相同的显影机台;步骤S05中刻蚀为湿法刻蚀。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103293848A (zh) * 2013-05-23 2013-09-11 上海华力微电子有限公司 光刻胶的处理方法以及半导体器件的制备方法
CN105655249A (zh) * 2016-03-21 2016-06-08 京东方科技集团股份有限公司 一种刻蚀方法
CN108281356A (zh) * 2018-01-22 2018-07-13 上海华力微电子有限公司 光刻胶去除方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080199814A1 (en) * 2006-12-06 2008-08-21 Fujifilm Electronic Materials, U.S.A., Inc. Device manufacturing process utilizing a double patterning process
CN101796631A (zh) * 2007-09-07 2010-08-04 飞思卡尔半导体公司 双栅氧化物器件集成
US20100311244A1 (en) * 2009-06-09 2010-12-09 Shanghai Ic R&D Center Co., Ltd. Double-exposure method
CN102841499A (zh) * 2012-09-19 2012-12-26 上海华力微电子有限公司 相移光掩模制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627524B2 (en) * 2001-06-06 2003-09-30 Micron Technology, Inc. Methods of forming transistor gates; and methods of forming programmable read-only memory constructions
WO2004100235A1 (ja) * 2003-05-09 2004-11-18 Fujitsu Limited レジストの加工方法、半導体装置及びその製造方法
US7687395B2 (en) * 2006-11-02 2010-03-30 International Business Machines Corporation Contact aperture and contact via with stepped sidewall and methods for fabrication thereof
US8039195B2 (en) * 2008-02-08 2011-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Si device making method by using a novel material for packing and unpacking process
US8728335B2 (en) * 2009-07-23 2014-05-20 Dow Corning Corporation Method and materials for double patterning
KR101675458B1 (ko) * 2010-07-27 2016-11-14 삼성전자 주식회사 산 확산을 이용하는 반도체 소자의 제조 방법
US8916439B2 (en) * 2012-07-20 2014-12-23 Monolithic Power Systems, Inc. Method for forming dual gate insulation layers and semiconductor device having dual gate insulation layers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080199814A1 (en) * 2006-12-06 2008-08-21 Fujifilm Electronic Materials, U.S.A., Inc. Device manufacturing process utilizing a double patterning process
CN101796631A (zh) * 2007-09-07 2010-08-04 飞思卡尔半导体公司 双栅氧化物器件集成
US20100311244A1 (en) * 2009-06-09 2010-12-09 Shanghai Ic R&D Center Co., Ltd. Double-exposure method
CN102841499A (zh) * 2012-09-19 2012-12-26 上海华力微电子有限公司 相移光掩模制作方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103293848A (zh) * 2013-05-23 2013-09-11 上海华力微电子有限公司 光刻胶的处理方法以及半导体器件的制备方法
CN103293848B (zh) * 2013-05-23 2015-12-23 上海华力微电子有限公司 光刻胶的处理方法以及半导体器件的制备方法
CN105655249A (zh) * 2016-03-21 2016-06-08 京东方科技集团股份有限公司 一种刻蚀方法
WO2017161683A1 (zh) * 2016-03-21 2017-09-28 京东方科技集团股份有限公司 刻蚀方法
CN108281356A (zh) * 2018-01-22 2018-07-13 上海华力微电子有限公司 光刻胶去除方法
CN108281356B (zh) * 2018-01-22 2020-06-26 上海华力微电子有限公司 光刻胶去除方法

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