JP2003324104A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2003324104A
JP2003324104A JP2002127488A JP2002127488A JP2003324104A JP 2003324104 A JP2003324104 A JP 2003324104A JP 2002127488 A JP2002127488 A JP 2002127488A JP 2002127488 A JP2002127488 A JP 2002127488A JP 2003324104 A JP2003324104 A JP 2003324104A
Authority
JP
Japan
Prior art keywords
resist
manufacturing
semiconductor device
layer
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002127488A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003324104A5 (enExample
Inventor
Katsu Isobe
克 礒部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UMC Japan Co Ltd
Original Assignee
UMC Japan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UMC Japan Co Ltd filed Critical UMC Japan Co Ltd
Priority to JP2002127488A priority Critical patent/JP2003324104A/ja
Priority to US10/310,625 priority patent/US6881656B1/en
Priority to TW091135256A priority patent/TWI251864B/zh
Publication of JP2003324104A publication Critical patent/JP2003324104A/ja
Publication of JP2003324104A5 publication Critical patent/JP2003324104A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2002127488A 2002-04-26 2002-04-26 半導体装置の製造方法 Pending JP2003324104A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002127488A JP2003324104A (ja) 2002-04-26 2002-04-26 半導体装置の製造方法
US10/310,625 US6881656B1 (en) 2002-04-26 2002-12-05 Production process for semiconductor apparatus
TW091135256A TWI251864B (en) 2002-04-26 2002-12-05 Production process for semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002127488A JP2003324104A (ja) 2002-04-26 2002-04-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2003324104A true JP2003324104A (ja) 2003-11-14
JP2003324104A5 JP2003324104A5 (enExample) 2005-09-22

Family

ID=29541583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002127488A Pending JP2003324104A (ja) 2002-04-26 2002-04-26 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US6881656B1 (enExample)
JP (1) JP2003324104A (enExample)
TW (1) TWI251864B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20250016843A (ko) * 2023-07-26 2025-02-04 에스케이하이닉스 주식회사 메모리 장치 및 이의 제조방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679610A (en) * 1994-12-15 1997-10-21 Kabushiki Kaisha Toshiba Method of planarizing a semiconductor workpiece surface
US6858909B2 (en) * 2002-11-29 2005-02-22 International Business Machines Corporation CMP assisted liftoff micropatterning

Also Published As

Publication number Publication date
US6881656B1 (en) 2005-04-19
TWI251864B (en) 2006-03-21
TW200305923A (en) 2003-11-01

Similar Documents

Publication Publication Date Title
JP4557479B2 (ja) フォーミングガスプラズマを用いたフォトレジスト除去プロセス
US7012022B2 (en) Self-patterning of photo-active dielectric materials for interconnect isolation
JP3226021B2 (ja) 半導体装置の製造方法
US20120193763A1 (en) Method of manufacturing semiconductor device, semiconductor device and resist coater
JPH11186235A (ja) 半導体装置の製造方法
CN101625968A (zh) 提高湿法刻蚀性能的方法
US20030194647A1 (en) Composite photoresist for pattern transferring
JP2003324104A (ja) 半導体装置の製造方法
CN115223849A (zh) 一种半导体器件及其制作方法
US20040121264A1 (en) Pattern transfer in device fabrication
JP2005072360A (ja) 電気絶縁膜のパターン製造方法および電子デバイス
JP2923908B2 (ja) 半導体装置の製造方法
KR950009291B1 (ko) 시릴화된 레지스트의 박리방법
JP2002075961A (ja) 半導体装置の製造方法
JP4178227B2 (ja) 基板処理方法及び半導体装置の製造方法
JPH06275511A (ja) ポリイミドパターンの形成方法
JPH05142788A (ja) レジストパターンの形成方法
JPH0845811A (ja) パターン形成方法およびそれを用いた半導体集積回路装置の製造方法
JP3653960B2 (ja) 半導体装置の製造方法
JP2003013246A (ja) 半導体装置の電極の製造方法
JP2001194805A (ja) 半導体工程におけるパターン形成方法
KR100613097B1 (ko) 반도체 제조 방법
JP2006253437A (ja) 半導体装置の製造方法
JPH09199473A (ja) ポリイミド系樹脂膜パターンの形成法
CN102270571A (zh) 半导体器件的制作方法

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050413

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050413

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070531

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080624

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20081021