TWI250607B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
TWI250607B
TWI250607B TW093132342A TW93132342A TWI250607B TW I250607 B TWI250607 B TW I250607B TW 093132342 A TW093132342 A TW 093132342A TW 93132342 A TW93132342 A TW 93132342A TW I250607 B TWI250607 B TW I250607B
Authority
TW
Taiwan
Prior art keywords
film
ruthenium
trench
semiconductor device
oxide film
Prior art date
Application number
TW093132342A
Other languages
English (en)
Chinese (zh)
Other versions
TW200527587A (en
Inventor
Mikio Tsujiuchi
Toshiaki Iwamatsu
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200527587A publication Critical patent/TW200527587A/zh
Application granted granted Critical
Publication of TWI250607B publication Critical patent/TWI250607B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
TW093132342A 2003-11-06 2004-10-26 Manufacturing method of semiconductor device TWI250607B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003376639A JP2005142319A (ja) 2003-11-06 2003-11-06 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200527587A TW200527587A (en) 2005-08-16
TWI250607B true TWI250607B (en) 2006-03-01

Family

ID=34544369

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093132342A TWI250607B (en) 2003-11-06 2004-10-26 Manufacturing method of semiconductor device

Country Status (5)

Country Link
US (1) US20050101070A1 (https=)
JP (1) JP2005142319A (https=)
KR (1) KR100654871B1 (https=)
CN (1) CN1311539C (https=)
TW (1) TWI250607B (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5455530B2 (ja) 2009-09-30 2014-03-26 株式会社トクヤマ ポリシリコン金属汚染防止方法
CN103887223A (zh) * 2014-03-12 2014-06-25 上海华力微电子有限公司 降低炉管工艺金属污染的方法
JP6246664B2 (ja) 2014-06-04 2017-12-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2016134614A (ja) * 2015-01-22 2016-07-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2021129042A (ja) * 2020-02-14 2021-09-02 キオクシア株式会社 半導体装置およびその製造方法
CN113257734B (zh) * 2021-04-30 2023-06-23 北海惠科半导体科技有限公司 半导体器件及其制作方法和芯片

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2955459B2 (ja) * 1993-12-20 1999-10-04 株式会社東芝 半導体装置の製造方法
JPH08340044A (ja) * 1995-06-09 1996-12-24 Rohm Co Ltd 半導体装置及びその製造方法
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
JP3296229B2 (ja) * 1997-01-21 2002-06-24 株式会社デンソー 半導体装置の製造方法
US5817566A (en) * 1997-03-03 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration
JPH113936A (ja) * 1997-06-13 1999-01-06 Nec Corp 半導体装置の製造方法
US5783476A (en) * 1997-06-26 1998-07-21 Siemens Aktiengesellschaft Integrated circuit devices including shallow trench isolation
KR100268453B1 (ko) * 1998-03-30 2000-11-01 윤종용 반도체 장치 및 그것의 제조 방법
TW426874B (en) * 1998-10-14 2001-03-21 United Microelectronics Corp Method for cleaning a semiconductor wafer
JP2000164569A (ja) * 1998-11-25 2000-06-16 Nec Corp 半導体装置の製造方法
TW461025B (en) * 2000-06-09 2001-10-21 Nanya Technology Corp Method for rounding corner of shallow trench isolation
US6627484B1 (en) * 2000-11-13 2003-09-30 Advanced Micro Devices, Inc. Method of forming a buried interconnect on a semiconductor on insulator wafer and a device including a buried interconnect
US6879000B2 (en) * 2003-03-08 2005-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation for SOI chip with multiple silicon film thicknesses
US6864152B1 (en) * 2003-05-20 2005-03-08 Lsi Logic Corporation Fabrication of trenches with multiple depths on the same substrate

Also Published As

Publication number Publication date
US20050101070A1 (en) 2005-05-12
CN1614762A (zh) 2005-05-11
KR100654871B1 (ko) 2006-12-11
KR20050043622A (ko) 2005-05-11
TW200527587A (en) 2005-08-16
CN1311539C (zh) 2007-04-18
JP2005142319A (ja) 2005-06-02

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