TWI247897B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI247897B
TWI247897B TW093104543A TW93104543A TWI247897B TW I247897 B TWI247897 B TW I247897B TW 093104543 A TW093104543 A TW 093104543A TW 93104543 A TW93104543 A TW 93104543A TW I247897 B TWI247897 B TW I247897B
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TW
Taiwan
Prior art keywords
potential
substrate
semiconductor
fixed
semiconductor substrate
Prior art date
Application number
TW093104543A
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English (en)
Other versions
TW200504367A (en
Inventor
Hiroshi Otani
Original Assignee
Mitsubishi Electric Corp
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Publication of TW200504367A publication Critical patent/TW200504367A/zh
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Publication of TWI247897B publication Critical patent/TWI247897B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
    • E04G21/00—Preparing, conveying, or working-up building materials or building elements in situ; Other devices or measures for constructional work
    • E04G21/24—Safety or protective measures preventing damage to building parts or finishing work during construction
    • E04G21/246—Safety or protective measures preventing damage to building parts or finishing work during construction specially adapted for curing concrete in situ, e.g. by covering it with protective sheets
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
    • E04G21/00—Preparing, conveying, or working-up building materials or building elements in situ; Other devices or measures for constructional work
    • E04G21/24—Safety or protective measures preventing damage to building parts or finishing work during construction
    • E04G21/28—Safety or protective measures preventing damage to building parts or finishing work during construction against unfavourable weather influence
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Description

1247897 玖、發明說明 【發明所屬之技術區域】 本發明係有關一種使用於加速度感測器、角速度感測 器以及靜電致動器（Actuator)之半導體裝置。 【先前技術】 在先前技術中，有關慣性力感測器、加速度感測器、 角速度感測器以及靜電致動器等，例如後述之專利文獻j 至專利文獻3之方法，係將可動子和固定子以極近之距離 分隔配置，並對可動子於位置變化時與固定子間產生之靜 電電容的變化進行檢測。 此時之可動子所使用之半導體裝置之構成係以玻璃_ 矽-玻璃之三層構造形成矽微（SiUc〇n Micr〇)構造體，再由 一側之玻璃之貫穿孔導出該各構成部之電位。 專利文獻1 :日本國特開平05_34〇961號公報 專利文獻2 :日本國特開平1〇_1〇4265號公報 專利文獻3:曰本國特開平〇5_142252號公報 在先jiij之技術中，右關破^上 ^有關將由矽形成之各構成部之電位 導出的方式，係於一側之玻 尾位 璃上形成貝穿孔，通過古歹言空 孔露出電極銲墊（pad、，* # 以貝牙 (驗…岭 ）並於該電極鲜塾進行導線辉接 如下問題··由於貫穿孔的 管（Capillary))足以進入之 但是，該種電極接出構造有 尺寸必須具有使焊接工具（毛細 315563 5 1247897 大小’使得雖欲縮小晶片尺寸卻有其限制。 因此，本發明之目的係据 之半導體裝置。一供-種可使晶片尺寸小型化 〇5::r:般而言’以衫微構造體形成的電容雖然有 〇.5pF的权度，但對應慣性 化量只有其mo的程度，因L 度專之靜電電容之變 容。另一古 必須檢測出非常小的靜電電 微構1體开：他物質接近該石夕微構造體，則由石夕 之電氣力線會有變化，而會有靜電電 因靜電等之電荷影響或電波障c問題。再者’ 樣會使靜電電容產生變化二:2外部干擾之影響也同 雜艾化而發生同樣的問題。因而，有 難以南精密地測量慣性力或加速度之虞。 此本毛明之另-目的係提供一種因外部干擾影塑 所4成之靜電電容的變化較少之半導體裝置。 a 【發明内容】 2發日㈣有鑑於前述之問題所開發者，係具備：形成 =個貫穿孔之上基板；下基板；爽在該上基板和該下 =1而形成固定電極和可變電極1時分別形成有面向 该通孔而用以將電位導出之電位導出部之複數個半導體基 板，以及形成於該上基板表面之複數個焊接辉塾⑺⑽㈣ ’而該焊接銲墊部係用以使由該各半導體基板之該 電位導出部分別經由該各貫穿孔引導至該上基板之電位導 出至焊接銲線’並將複數個半導體基板中的一個半導體基 板’形成用以圍住該上基板和該下基板間所夾持之區域周 315563 6 1247897 而將複數個上述半導體基板中之其他半導
其他半導體基板之該電位導出部之面積 緣的外周框狀， 體基板，以由开
基板以免受到其他物質 電位之導電層，俾遮蔽上述各半導體 質之接近或靜電等或電波干擾等之外 部干擾。 【實施方式】 第一實施形熊 第1圖係表示和後述之各實施形態之基本構成相關之 第一實施形態之半導體裝置（微構造體）的俯視圖，第2圖 係表示相同之該微構造體的側面剖視圖，第3圖係表示省 略微構造體之上基板之狀態的俯視圖，第4圖為第3圖之 IV-IV剖視圖’第5圖為第3圖之V-V剖視圖。 本微構造體係使用於慣性力感測器、加速度感測器、 角速度感測器以及靜電致動器之矽微構造體。如第丨圖至 弟5圖所示’邊微構造體係由上側之玻璃板（以下稱為「上 基板」）1 ’以石夕晶體構成之半導體基板3、5、7、9，以及 下側之破璃板（以下稱為「下基板」）11堆積而成之三層構 造，並具有將該各構成部中之半導體基板3、5、7、9的電 位通過穿設於上基板1之一部份之貫穿孔1 3、1 5、1 7、1 9， 315563 7 .1247897 而分別導接至上基板1表面上之各銲接銲墊部2 1之構成。 上基板1和下基板11係使用相同面積之板狀玻璃體， 將複數個半導體基板3、5、7、9夾持配置於該上基板1 和下基板11間。其中，在上基板丨之既定處，穿設如上述 之貫穿孔13、15、17、19。該貫穿孔13、15、17、19係 一列形成在例如上基板1上設定為一直線之電位導出區域 23上。 在半導體基板3、5、7、9中，第一半導體3係為以圍 住俯視為四角形狀之微構造體之四邊之方式形成外周框狀 之外周框部，並固定於接&(GND)電位，且形成相對兩玻 璃板1、11不會移動之固定電極。如此，藉由以形成外周 框部之第一半導體基板3作為固定電極，而得以防止側面 方向之帶電。 ----- 門丨沔邢，於1：位等 出區域2 3所屬之位詈v，丨、，#、a ^ i 、 置上以朝俯視之内側突出之方式，死 成有俯視時有既定面積之矩形等之電位導出部31。如[ :所示’將該電位導出部31之面積設定成 斗 2基板5、7、9之電位導出部—大略相同: 導體基板3,而係以由形成該外周框狀之體: t内周所包，之方一，並作為分別固定於:玻: 丨之固疋電極。第二和第三半導體基板5 作為外周框部H導體基板3之内側進行配線之: 315563 8 1247897 3 3 ’以及用以减鹿* # ^ 4愿和弟四半導體基板9間發生之靜電雷宠 變化之固定側雷办a 今 谷感應子35所形成。其中該固定側電衮咸 應子35係由該美η ^ 4 ^ 丞片33朝向俯視之内側方向，且呈大略 齒狀（梳狀）。秋接 + 、 ）…、後，在苐二和第三半導體基板5、7之端部， ;電{ V出區域23所屬之位置上，形成有俯視時具有既定 面積之矩形等之電位導出部36a、36b。 再者’第四半導體基板9為相對兩玻璃板1、u可移 動之可變電極，且以由形成外周框狀之第-半導體基板3 之内周所包圍之方式配置。言亥第四半導體基板9係由配置 於俯視時之中央部之幹線部37，以及用以感應在與第二及 第三半導體基板5、7之固定側電容感應子35間發生之靜 電電容變化的可變側電容感應？ 39所形成。#中，該可變 侧電容感應子39係由該幹線部37向俯視之兩側突出。然 後，在第四半導體基板9之端部，亦即於電位導出區域= 所屬之位置上，形成俯視時具有既定面積之矩形等之電位 導出部40。 如第1圖所示，銲接銲墊21位於鄰接電位導出區域 23且設定於上基板1之俯視端部處之接線區域（電位導出 部）41内，並分別一列配置於四個位置。如第1圖和第2 圖所示’將以埋藏貫穿孔13、15、17、19之方式塗佈形成 之配線層43之一部分45在上基板！延長配設，並使其連 接至銲接銲墊部21，而將各貫穿孔13、Μ、17、19正下 方之電位導出部31、36a、36b、40電性連接至銲接銲墊部 21。另外，可利用同一金屬塗料（Paste)或銲料等同時形成 315563 9 .1247897 銲接銲墊部2 1和配線層43。 该貫施形態之微構造體如上述般，由各半導體基板 3、5、7、9之各貫穿孔13、15、17、19正下方之電位導 出部31、36a、3 6b、40，藉由配線層43，導出至上基板工 上之銲接銲墊部21。故如第2圖所示，可在上基板1上之 銲接銲墊部2 1上，連接銲接銲線（B〇ncjing wire)47，而可 進行各半導體基板3、5、7、9之電性導出。另外，符號 48 表示 ASIC(Applicati〇n Specific Integrated Circuit，既 定應用積體電路）等之半導體積體電路。 於此，比較如上述將銲接銲線47連接至基板丨上之銲 接銲墊部21之本實施形態之微構造體（第2圖），以及不形 成銲接銲墊部21而直接將銲接銲線47連接至貫穿孔13 ^ 15、17、19正下方之電位導出部31、363、鳩、4〇之情 況(第6圖和第7圖)後可得知，在第6圖和第7圖的情況 下貝穿孔1 3、1 5、1 7、1 9之尺寸必須具有可使用以連接 銲接銲線47之銲接工具（毛細管：省略圖示）進入之大小， 因^即使欲縮小晶片尺寸卻有其限度。但若如第2圖所示 ^施形態，即可於上基之上面操作銲接卫具(毛細管) /連接鮮接銲、線47。因而，可將電位導㈣ 晶片尺寸小型化。 ΰ之清况(L2)，而可將 亦 半導體 之該第 :板= (微構造體)之角隅部形成第 :半導體=導出部A且將包含該電位導出部 基板3之角隅部的面積，設U約略等 315563 10 1247897 36a、36b、40 於其他半導體基板5、7、9之電位導出部 之面積，而得以將晶片尺寸小型化。 另外，在本實施形態中，雖然係將包含該電位導出部 3!之該第一半導體基才反3之角隅料面積，設定為約略等 同於其他半導體基板5、7、9之電位導出部36a、36b、4〇 之面積，但角隅部之面積之大小關係除了完全一致之外， 包含該電位導出部31之該第一半導體基板3之角隅部的面 積’也可稍大於其他半導體基板5、7、9之電位導出部36a、 36b、40之面積。 此外，包含該電位導出部31之該第一半導體基板3 之角隅部的面積，若小於其他半導體基板5、7、9之電位 導出部36a、36b、40之面積時，也能得到同等之效果。 i二實施形熊 第8圖係表示有關本發明之第二實施形態之半導體裝 置（微構造體）之省略上基板之狀態的俯視圖。此外，在第8 圖中，將具有和第一實施形態同樣功能之元件標以同一符 號0 本實施形態之微構造體係如第8圖所示，其基本之構 成和第一實施形態之微構造體共通，在微構造體之設定為 一直線之電位導出區域23内之角隅部，形成有作為外周框 部之第一半導體基板（矽晶體）3之電位導出部3 i。 於此，在第一實施形態中，以從作為外周框部之第一 半導體基才反3之框部幸月俯才見之内側突出之方式％成有該電 位導出部31。特別是，如第3圖所示，為了能夠使該突出 315563 11 1247897 之電位導出部31之面積和其他半導體基板(石夕晶體)5、7、 之電位導出部36a、遍、4G之面積約略相同而使包含 ^位導出部31之第_半導體基板3之角隅部的面積大於 ”半導體基板5、7、9之電位導出部36a、鳩、4〇。 相對於A，在本實施形態中，將由作為外周框部（其形 -外周框狀）之第-半導體基板3朝作為電位導出部η ]大出之部分的面積’設定為小於其他半導體基板 人、9之電位導出部36a、规、4〇之面積由此，使包 =位導出部31之第一半導體基板3之角隅部的面積等 、、他半導體基板5、7、9之電位導出部36”鳩、4〇 之面積。 ^第8圖所示’在第一半導體基板3之一角隅部形成 出部31，由於將包含該電位導出部31之第一半導 土板3之一角隅部的面積設定成和其他半導體基板5、 、之電位導出部36a、36b、4〇約略相同之面積因此 例如第9圖所示’在除了第一半導體基板3之角隅 二卜的中間位置形成電位導出部31之情況，本實施形態 了使日日片尺寸小型化。 具體而言，可考慮該微構造體之端部位置至第二個電 ^出區域之距離L3(第8圖）、叫第9圖）。在第9圖中， ^了=第二半導體基板5之電位導出部^配置於微構造 之角隅部附近，必須將該電位導出部％和第—半導體 二一予以間配置。因此’由該微構造體之端部位置至 個電位導出部31之長度即為L4。相對於此，在第8 315563 12 1247897 圖中在第半導體基板3之一角隅部以拉入方式形成電 ^出^ 31°由於將包含該電位導出部31之第一半導體 基板3之一角隅部的面積設定成和其他半導體基板5、7、 電4導出崢36a、36b、40約略相同之面積，故由該微 構造體之端部位置至第二個電位導出部36a之長度即為比 L 3 一 丑之L4。因而，藉由本實施形態可使晶片尺寸比第9 圖所示之情況更為小型化。 差^實施形能 第1 〇圖係表示有關本發明之第三實施形態之半導體 裝置（微構造體）之省略上基板之狀態的俯視圖。此外，在 第1 0圖中，將具有和第一實施形態及第二實施形態同樣功 能之元件標記同一符號。 在上述之第二實施形態中，將作為外周框部之第一半 V體基板（矽晶體）3之電位導出部3〗形成在設定為微構造 體之一直線狀之電位導出區域23之角隅部，而在本第三實 施形態中，並未將作為外周框部之第一半導體基板3之電 位導出部31配置在相對於其他半導體基板（矽晶體”〜了、 9之電位導出部36a、36b、40之直線位置上，而將其配設 於微構造體之切割線（Dicing Line)上（亦即切割並分割之 線上）之任意角隅部。如此，將第一半導體基板3之電位導 出邛31铋跨配設於微構造體之切割線上之角隅部時，在切 斷该切割線後’第-半導體基板3之電位導出部3 i即會被 配設於微構造體之周緣部。藉此，可使第一半導體基板3 之電位導出部3 1避開半導體基板5、7、9比較密集之部分， 315563 13 1247897 而將其配置於該半導體基板5、7、9比較不密集之部分， 故可使整體之密度平均化而縮小晶片之尺寸。 另外，根據該構成，雖然僅將第一半導體基板3之電 位導出部31孤立配置於遠離其他半導體基板5、厂9之電 位導出部36a、36b、4〇之位置上，但若考慮接線作業之自 動化之便利H ’則最好與第一實施形態和第二實施形態同 樣地如第11圖所示將連接銲接銲線47之複數個銲接銲 、卩2 1郇接配置成一直線狀。因此，形成其長度比從其他 半導體基板5、7、9之電位導出部36a、36b、4()至該銲接 在干墊。卩2 1之配線層43之長度長的從孤立配置之第一半導 體基板3之電位導出部3丨至該銲接銲墊部2 1⑴&)之配線 另外在第二實施形態中，係將包含第一半導體基板 3 ,二位導出部31之該第一半導體基板3之一角隅部的面 積又疋成和其他半導體基板5、7、9之電位導出部36a、 :二、4"勺略相同之面積，而在本第三實施形態中，由於 4:1立¥出部31橫跨設定於切割線上，在切斷該切割線 腺今入位導出部31即會被配設於微構造體之周緣部，而可 導出部31之該第-半導體基板3之-角隅部 又疋成比其他半導體基板5、7、9之電位導出部 过、36b、4〇 话 t Jr -r- ^ . 積。因此，由本實施形態可使晶片 寸匕第二實施形態更為小型化。 甚 半‘體基板3之電位導出部3 1之位置並非 弟〇圖所不之位置。例如，如第12圖所示，也可 315563 14 1247897 配置在微構造體之切割線上之橫跨位置上，亦^卩 二實施形態所述之第-半導體基板3之電位導出部心 置附近，也可將電位導出部31之面積限定於以第—半導： 基板3形成之外周框部之寬度以μ。在此情況下豆 橫跨並突出第-半導體基板3之切割線上之角端部的二 形成貫穿孔13，也不致有所妨礙。 & 或是，如第13圖所示，將第一半導體基板3之電位導 出部31的位置，配置於接近第1〇圖所示之位置之橫跨切 割線之位置上。在此情況下，即使以橫跨並突出第—半導 體基板3之切割線上之角端部的方式形成貫穿孔〖3，也 致有所妨礙。 再者，上基板1上之配線層43、49之形狀並非僅限於 第11圖所示之形狀。例如，如第14圖所示，當然也可藉 由配線圖案化形成為各種形狀之配線層49，而將銲接鲜塾 部2 1配置於所期望之位置。 第四實施形態 第1 5圖係有關本發明之第四實施形態之半導體裳置 (微構造體）之示意圖。另外，在第15圖中，將具有和第一 實施形態至第三實施形態之同樣功能的元件標記同一符 號。 本實施形態之微構造體如第1 5圖所示，在上基板j 之表面，將由接地（GND)電位之第一半導體基板（矽晶體）3 導出至銲接銲墊部2 1之配線層43，於電位導出區域23以 及接線區域（電位導出部）4 1以外之區域（以下稱為「遮蔽 15 315563 1247897 (SMehi)區域」上擴張成導電I 51，並將上基板i上之該 導電層51之表面電位固定為接地電位。 如此藉由形成該導電層51，而得以實現不會因其他 物質之接近、#電等或電波干擾等之外部干擾而產生電容 變化之高性能製品。 另外，各配線層43、49及導電層51的形狀並非僅限 於第15圖所示之形狀’例如也可以形成如第㈣所示之 圖案。 此外導電層5丨的電位並非僅限於接地（GND)電位， 只要設定於既定之固定電位即可。 第五實施形熊 第1 7圖係表不使用有關本發明之第五實施形態之微 構造體之半導體裝置的側面剖視圖。另外，在帛17圖中， 將具有和第一實施形態至第四實施形態之同樣功能的元件 標記同一符號。 本實施形t之半導體裝置係如第丨7圖所示，將微構造 一 ·下基板11之下面，透過既定之導電構件55黏貼（黏 晶（Die Bond))於晶片座（Die心）57之上面。 導電構件55為可使用將銀等金屬混入環氧樹脂 (―)等樹脂材料的導電性樹脂，或是鋅料或金-錫(AU-s i)共晶性之金屬等。 座7係使用既定金屬材料之導電板。將該晶片座 5:之電位固定於接地電位或固定之電位。具體而言，該晶 座57之電位係透過第18圖所示之内部引線⑽ 315563 16 1247897 之半導體元件63等上。 脂等之絕緣性樹脂形成之 連接在外部引線61或是ASIc等 此外，符號60表示由環氧樹 絕緣模塑（Mold)體。 :將上述之方法與使用絕緣體將微構 晶片座57之情況相比較後可知，在微構造體53之下二於 可貫現不會因其他物質之接近、靜電等或外 部干擾而產生電容變化之高性 馒4之外 ，外，如…所示，在鄰V配置之半導雜元件63 …上’也同樣以同等之導電搆件55 &行金屬化 (Metallizmg)，而得以使微構造體53之下基板11之下 之晶片座57的電位等與半導體元件〇之基板之下面= 位相同。因而，也可使半導體元件63等成為不會因其他物 質之接近、靜電等或電波干擾等之外部干擾而產生電容變 化之高性能製品。 此外，在第18圖中，雖然係將晶片座57之電位以内 部引線（Inner Lead)59導出至外部，但其他如第19圖所 示，同樣也可在晶片座57之既定位置上連接銲接銲線65，· 而透過該銲接銲線65將晶片座57之電位導出至外部。 第六實施形態 第20圖係使用有關本發明之第六實施形態之微構造 體的半導體裝置之圖。另外，在第20圖中，將具有和第一 實施形態至第五實施形態之同樣功能的元件標記同一符 號0 本貫施形態之半導體裝置係在信號處理電路用之 17 315563 1247897 ASIC等，半導體元件71之上面上，堆疊搭載有微構造體 73之堆豐（Stack)構造。在堆疊有半導體元件η之微構造 體73之表面區域上形成導電層”，並透過於該導電層乃 之上面形成的導電構件77，將該微構造體73予以黏晶。 於此，將半導體元件71之導電層Μ之電位固定於接 地電位或固定之電位。 導電構件77為可使用將銀等金屬混入環氧樹脂等之 树知材料的導電性樹脂，或是銲料或金_錫共晶性之金屬 等。 、 藉由上述之構成，和第五實施形態同樣地，在微構造 體73之下基板丨丨侧，可實現不會因其他物質之接近、靜 電等或電波干擾等之外部干擾而產生電容變化之高性能製 品。 ijr實施形熊 第21圖係使用有關本發明之第七實施形態之微構造 體的半導體裝置的圖。另外，在第21圖中，將具有和第一 實施形態至第六實施形態之同樣功能的元件標記同一符 號。 本實施形態之半導體裝置係在晶片座57上搭載微構 造體83，然後在微構造體83之上基板〗之上面堆疊搭載 信號處理電路用之ASIC等之半導體元件81。將形成堆疊 構造之微構造體83之上基板1，透過導電構件85黏貼於 半導體元件81上。該導電構件85為可使用將銀等金屬混 入環氧樹脂等樹脂材料的導電性樹脂，或是適用銲料或 315563 18 1247897 金-錫共晶性之金屬等。 然後，將該半導體元件8丨之導電性基板85之電位固 定於接地電位或固定之電位。 藉由上述之構成，可固定微構造體83之下基板11之 下面的電位’而可得到和第五實施形態同樣之效果。 1八實施形態 第22圖係表示有關本發明之第八實施形態之微構造 體之俯視圖’而第23圖係第22圖之ΧΧΠΙ-ΧΧΙΙΙ剖視圖。 另外’在第22圖和第23圖中，將具有和第一實施形態至 第七實施形態之同樣功能的元件標以同一符號。 本實施形態之微構造體如同第一實施形態至第三實施 形態，在互相併排配置之上基板丨和下基板丨丨間，分別配 置作為固定電極和可變電極之半導體基板（矽晶體）3、5、 7、9。在上基板1之一部份形成貫穿孔丨3、丨5、丨7、丨9， 透過形成於上基板1之表面中的配線層43，將各半導體基 板3 5 7 9之電位導出部3 1、36a、36b、4 1電性從該 貝穿孔13、15、17、19連接至上基板丨之銲接銲墊部21。 然後，在以如此形成配線層43的上基板丨之再上層 上’形成有絕緣膜91。該絕緣膜91係使用可於低溫下堆 疊形成之氮化膜或是聚醯亞胺（p〇lyimide)。 然後，在對應配線層43之中間位置的位置上，於絕緣 膜91上穿設有配線導出孔…其中該配線層43係由固定 於接地(_)電位之第一半導體基板3經過貫穿孔 出。將使用銀等金屬混入A # 八蜋虱树知荨之樹脂材料的導電性 315563 19 1247897 樹脂 塗布 導體 側。 ，或是銲料或金·錫共晶性之金屬等之導電體％充填 形成於該配線導出93。藉由該導電體％將第一半 基板3之電位（接地電位）導出至絕㈣^之上表面 因此，在絕緣膜91之上面側形成有連接於上述之接地 電位之導電體95,並且防止因其他物f之接近、靜電等外 部干擾而造成電容變化之導電層97。該導電層97係形成 在覆蓋配線層43之大部分的所期望之遮蔽區域。 藉由上述之構成，可將包含配線層43之微構造體的上 方電位固定於接地電位，而得以實現不會因其他物質之接 近、靜電等或電波干擾等之外部干擾而產生電容變化之高 性能製品。 此外，在本實施形態中，雖然因將第一半導體基板3 作為接地電位，而使在遮蔽區域上形成之導電層97也作為 接地電位，但是若將第一半導體基板3固定於接地電位以 外之既定固定電位，而使導電層97固定於該固定電位的 話，當然也可得到同樣之效果。 1九實施形能 第24圖係使用有關本發明之第九實施形態之微構造 體的半導體裝置之側面剖視圖。另外，在第24圖中，將具 有和第五貫施形態之同樣功能的元件標記同一符號。 本貫施$悲之半導體裝置係如第24圖所示，和第五實 施形態之共通點為··將微構造體53之下基板u之背面透 過既疋之導電構件5 5黏貼於導電性晶片座5 7之表面上。 315563 20 1247897 導電構件5 5和第五實施形態相同，係可使用將銀等金 屬混入環氧樹脂等之樹脂材料的導電性樹脂，或是銲料或 金-錫共晶性之金屬等。 另外晶塊57也和第五實施形態相同，係使用既定金屬 材料之導電板。將該晶片座57的電位係固定於接地電位或 疋固定之電位。 此外，第24圖中的符號63表示ASIC等之半導體元 件。 然後，在本實施形態中，如第24圖所示，將微構造體 5 3以上下相反於第丨7圖所示之第五實施形態之微構造體 53的方向設置。再者，將用以連接外部引線61和半導體 兀件63之銲接銲線1〇7等之全部電路銲接於兩構件63、 6 1之下側，亦即將全部電路以所謂反向彎曲（Reverse Bend) 方式進行安裝。藉此，可藉由導電性之晶片座57遮蔽全部 電路、微構造體53及半導體元件63之上方。 如此，藉由固定於接地電位或固定電位的晶片座57， 可防止由上方之其他物質之接近，靜電等或電波干擾等之 外部干擾而造成之電容變化。 另外，在本實施形態中，在與安裝該半導體裝置1〇2 的安裝基板1〇3之半導體裝置102相對向的表面上，形成 有導電層105。藉由该導電& 1〇5可遮蔽半導體裝置⑽ 的下方。藉由該導電層1〇5，可1!七1«丄 声 守电層1υ5可防止由下方之其他物質之 接近’靜電等或電波干擾算 > 冰工α 人私收丁儍寻之外部干擾而造成之電容變 化。 315563 21 !247897 藉由這些方式，得以實現可防止由上下兩方向之其他 物質之接近、靜電等或電波干擾等之外部干擾而造成電容 變化之高性能製品。 本發明為將複數個半導體基板内之一半導體基板形成 為用以將上基板和下基板間夾起之區域之周緣圍住之外周 框狀，而以由形成外周框狀之該一半導體基板的内周所圍 燒之方式配置複數個半導體基板内之其他導體基板。在角 隅部形成該一半導體基板的電位導出部，且因為將包含該 電位導出部之該一半導體基板的角隅部之面積，設定為約 略等同或小於其他半導體基板之電位導出部的面積，而得 以將晶片尺寸小型化。 此外，在上基板的表面上等，由於形成有固定於包含 接地電位之既定固定電位且用以遮蔽各半導體基板以免其 他物質之接近或靜電等或電波干擾等之外部干擾之導電層 等，因此可提供一種不易受外部干擾之影響而減少靜電電 容變化之半導體裝置。 【圖式簡單說明】 第1圖係表不有關本發明之第一實施形態之微構造體 之俯視圖。 第2圖係表示有關本發明之第一實施形態之微構造體 之側面剖視圖。 第3圖係表不有關本發明之第一實施形態之微構造體 之省略上基板之狀態的俯視圖。 苐4圖係為第Λ 勺乐^圖的α-α剖視圖。 22 315563 1247897 苐5圖係為弟3圖的B-B剖視圖。 曰第6圖係表示在貫穿孔正下方之電位導出部直接連接 鲜接銲線之範例的側面剖視圖。 日第7圖係表示在貫穿孔正下方之電位導出部直接連接 杯接#線之範例的俯視圖。 第8圖係表示有關本發明之第二實施形態之微構造體 之省略上基板之狀態的俯視圖。 第圖係表示其他例之省略上基板之狀態的俯視圖。 第1 0圖係表示有關本發明之第三實施形態之微構造 體之省略上基板之狀態的俯視圖。 第1 1圖係表不有關本發明之第三實施形態之微構造 體的俯視圖。 12圖係表示有關本發明之第三實施形態之其他例 之微構1 體之省略上基板之狀態的俯視圖。 第1 3圖係表示有關本發明之第三實施形態之其他例 之微構造體之省略上基板之狀態的俯視圖。 第14圖係表示有關本發明之其他例之第三實施形態 之^政構造體的俯視圖。 第1 5圖係表示有關本發明之第四實施形態之微構造 體的俯視圖。 第1 6圖係表示有關本發明之其他例之第四實施形態 之微構造體的俯視圖。 第 17圖孫主- 表不有關本發明之第五實施形態之半導體 裝置的側面剖視圖。 ' 23 315563 ^47897 弟18圖係夺一 裝置的俯視圖"不有關本發明之第五實施形態之半導體 第19圖係表 之半暮#祐$ /、有關本發明之第五實施形態之其他例 體衮置的俯視圖。 第 20圖倍矣一 士
Mi » „ ^不有關本發明之第六實施形態之半導體 裝置的側面剖視圖。 弟 21圖仓；± — _» 择里 ’、衣不有關本發明之第七實施形態之半導艤 、置的側面剖視圖。 圖係表示有關本發明之第八實施形態之微構造 體的俯視圖。 第23圖係表示有關本發明之第八實施形態之微構造 體的側面剖視圖。 圖係表示有關本發明之第九實施形態之微構造 體的側面剖視圖。 (元件符號說明） 上基板（玻璃板） j、 5、7 、9 半導體基板 11 下基板（玻璃板） 13、 15 > 17、19 貫穿孔 21、 21a 銲接銲墊部 23 電 位 導 出 區域 3卜 36a 、36b 、 40 電位導出部 33 基片 35 固 定 側 電 容感應子 37 幹線部 39 可 變 側 電 容感應子 41 接線區域 43、49 配 線層 315563 24 1247897 45 47 > 48 5卜 55 ^ 57 60 63 > 91 95 103 配線層4 3之一部份 65、107 銲接銲線 ASIC(既定應用積體電路） 75 導電層 53、73、83 微構造體 77、85 導電構件 晶片座 59 内部引線 絕緣模塑體 61 外部引線 71、81、102 半導體元件 絕緣膜 93 配線導出孔 導電體 97、105 導電層 安裝基板 25 315563

Claims (1)

1247897 拾、申請專利範圍： 1. 一種半導體裝置，包括： 形成有複數個貫穿孔之上基板； 下基板；以及 爽在上述上基板和上述下基板間而形成固定電極 和可變電極’且分別形成有面向該通孔而用以將電位導 出之電位導出部的複數個半導體基板， 並將複數個上述半導體基板中的一個半導體基 板以圍住由上述上基板和上述下基板間所夾持之區域 周緣的方式形成外周框狀， 將複數個上述半導體基板中的其他半導體基板，以 由形成外周框狀之上述一個半導體基板的内周所包圍 之方式配置， 將上述一個半導體基板之上述電位導出部形成於 角隅部，且將包含上述電位導出部之上述一個半導體基 板之上述角隅部的面積，設定為約略等同或小於上述其 他半導體基板之上述電位導出部的面積。 2·如申請專利範圍第1項之半導體裝置，復具備在上述上 基板的表面所形成之複數個銲接銲墊部，上述銲接銲墊 P係用以使由上述各半導體基板之上述電位導出部分 別、、1由上述各貫穿孔引導至上述上基板之電位導出至 銲接銲線。 3·=申請專利範圍第丨項之半導體裝置，其中，上述電位 導出部係配設於周緣部上。 315563 26 1247897 4.二申請專利範圍第1項之半導體裝置，其中，在上述上 上，形成有用以遮蔽上述各半導體基板以免 ;=:物質之接近或靜電等或電波干擾等之外部干 擾的導電層，而該導電層择 电層係固疋於包含接地電位之既定 的固定電位。 5·如申凊專利範圍第1項之半$ 只心千等體裝置，其中，上述一個 半導體基板係固定於包含接地電位之既定的固定電 位0 6·如申請專利範圍第4項之丰壤 只心千導體裝置，其中，上述一個 半導體基板係固定於包含接地電位之既定的固定電 位且上述導電層係藉由連接至上述一個半導體基板而 固定於上述固定電位。 7·如中請專利範圍第1項之半導體裝置，其中，上述下基 板的背面係透過既定之導電構件黏晶於導電性之晶二 座上。 8·如申請專利範圍第丨項之半導體裝置，其中，在上述上 基板表面上堆疊搭載有信號處理用之半導體元件，且接 合於上述上基板表面之上述半導體元件之基板係固定 於包含接地電位之既定的固定電位。 9·如申請專利範圍第2項之半導體裝置，復包括： 以由上述各貫穿孔連接至上述各銲接銲墊部之方 式配線於上述上基板之表面上的配線層； 覆盍於配線有上述配線層之上述上基板之表面上 的絕緣膜；以及 27 315563 1247897 形成於上述絕緣膜之上層，固定於包含接地電位之 既定的固定電位，以遮蔽上述各半導體基板以及上述配 線層以免受到其他物質之接近或靜電等或電波干擾等 之外部干擾的導電層。 28 315563
TW093104543A 2003-07-16 2004-02-24 Semiconductor device TWI247897B (en)

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