CN1296715C - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1296715C
CN1296715C CNB2004100348228A CN200410034822A CN1296715C CN 1296715 C CN1296715 C CN 1296715C CN B2004100348228 A CNB2004100348228 A CN B2004100348228A CN 200410034822 A CN200410034822 A CN 200410034822A CN 1296715 C CN1296715 C CN 1296715C
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Prior art keywords
substrate
semiconductor substrate
current potential
semiconductor
extraction unit
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Expired - Fee Related
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CNB2004100348228A
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English (en)
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CN1576853A (zh
Inventor
大谷浩
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
    • E04G21/00—Preparing, conveying, or working-up building materials or building elements in situ; Other devices or measures for constructional work
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
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    • E—FIXED CONSTRUCTIONS
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Abstract

本发明的课题是将芯片小型化，减小外部干扰的影响造成的静电电容的变化。以可包围在上衬底(1)和下衬底(11)之间被夹置的区域的周边的外周框形状来形成第1半导体衬底(3)，在角部形成第1半导体衬底(3)的电位提取部(31)，将包含电位提取部(31)的第1半导体衬底(3)的角部的面积设定在其他半导体衬底(5、7、9)的电位提取部(36a、36b、40)的面积以下，使芯片尺寸小型化。通过导电层等，使各半导体衬底屏蔽来自靠近其他物质、静电等或电波干扰等的外部干扰。

Description

半导体器件
技术领域
本发明涉及用于加速度传感器、角速度传感器和静电致动器等的半导体器件。
背景技术
以往，在惯性力传感器、加速度传感器、角速度传感器及静电致动器等中，例如后述的专利文献1～专利文献3那样，将可动元件和固定元件靠近分离配置，检测可动元件位移时与固定元件之间产生的静电电容的变化。
作为这种情况下的可动元件，使用以玻璃-硅-玻璃的三层结构来形成微型硅结构体，从一层玻璃的通孔中提取其各构成部的电位所构成的半导体器件。
【专利文献1】
(日本)特开平05-340961号公报
【专利文献2】
特开平10-104265号公报
【专利文献3】
特开平05-142252号公报
以往，就提取由硅形成的各构成部的电位来说，在一层玻璃中形成通孔，通过该通孔露出电极焊盘，对该电极焊盘进行引线键合。
但是，在这样的电极提取结构中，作为通孔的尺寸，存在需要焊头(毛细管)进入的大尺寸，在减小芯片尺寸上存在限制这样的问题。
发明内容
因此，本发明的课题是，提供可进行芯片尺寸小型化的半导体器件。
此外，一般地，相对于0.5pF左右的微型硅结构体中形成的电容，对应于惯性力和加速度等的静电电容的变化量是其1/10左右，需要检测非常小的静电电容。另一方面，如果其他物质靠近该微型硅结构体，则微型硅结构体中形成的电容的电力线产生变化，存在静电电容值与惯性力和加速度等无关变化的问题。而且，即使是静电等的电荷影响或电波干扰等的外部干扰的影响，也同样产生静电电容的变化，产生同样的问题。因此，有难以高精度测定惯性力和加速度等的危险。
因此，本发明的课题还有提供外部干扰的影响造成的静电电容变化小的半导体器件。
为了解决上述课题，本发明提供一种半导体器件，包括：形成了多个通孔的上衬底；下衬底；多个半导体衬底，被夹置在所述上衬底和所述下衬底之间来形成固定电极和可变电极，同时分别在所述通孔中形成用于提取期望电位的电位提取部；以及多个键合焊盘部，形成在所述上衬底的表面上，以便从所述各半导体衬底的所述电位提取部中分别通过所述通孔将环绕所述上衬底的电位引出到键合线上；其中，将多个所述半导体衬底中的一半导体衬底形成为外周框状，以包围所述上衬底和所述下衬底之间被夹置的区域的周边，多个所述半导体衬底中的其他半导体衬底以被外周框状形成的所述一半导体衬底的内周包围来配置，所述一半导体衬底的所述电位提取部形成在角部，并且包含该电位提取部的对应一半导体衬底的所述角部的面积与所述其他半导体衬底的所述电位提取部的面积大致相同，或被设定为其以下。
此外，在所述上衬底的表面上，形成导电层，其被固定为包含接地电位的规定的固定电压，使所述各半导体衬底屏蔽来自靠近其他物质、静电等或电波干扰等的外部干扰。
附图说明
图1是表示本发明实施方式1的微型结构体的平面图。
图2是表示本发明实施方式1的微型结构体的侧面剖面图。
图3是表示本发明实施方式1的省略了微型结构体的上衬底的状态平面图。
图4是图3的IV-IV剖面图。
图5是图3的V-V剖面图。
图6是表示将直接键合线连接于通孔正下方的电位取出部的例子的侧面剖面图。
图7是表示将直接键合线连接于通孔正下方的电位取出部的例子的平面图。
图8是表示本发明实施方式2的省略了微型结构体上衬底的状态平面图。
图9是表示另一例子中省略了上衬底的状态平面图。
图10是表示本发明实施方式3的省略了微型结构体上衬底的状态平面图。
图11是表示本发明实施方式3的微型结构体的平面图。
图12是表示本发明实施方式3的另一例子的省略了微型结构体上衬底的状态平面图。
图13是表示本发明实施方式3的另一例子的省略了微型结构体上衬底的状态平面图。
图14是表示本发明实施方式3的另一例子的微型结构体的平面图。
图15是表示本发明实施方式4的微型结构体的平面图。
图16是表示本发明实施方式4的另一例子的微型结构体的平面图。
图17是表示本发明实施方式5的半导体器件的侧面剖面图。
图18是表示本发明实施方式5的半导体器件的平面图。
图19是表示本发明实施方式5的半导体器件的另一例子的平面图。
图20是表示本发明实施方式6的半导体器件的侧面剖面图。
图21是表示本发明实施方式7的半导体器件的侧面剖面图。
图22是表示本发明实施方式8的微型结构体的平面图。
图23是表示本发明实施方式8的微型结构体的侧面剖面图。
图24是表示本发明实施方式9的微型结构体的侧面剖面图。
具体实施方式
实施方式1
图1是表示与后述各实施方式的基本结构有关的作为实施方式1的半导体器件(微型结构体)的平面图，图2是表示该微型结构体的侧面剖面图，图3是表示省略了微型结构体的上衬底状态的平面图，图4是图3的IV-IV剖面图，图5是图3的V-V剖面图。
该微型结构体是用于惯性力传感器、加速度传感器、角速度传感器和静电致动器等的微型硅结构体，如图1～图5所示，由叠层了上侧的玻璃板(以下称为‘上衬底’)1、硅体构成的半导体衬底3、5、7、9、以及下侧的玻璃板(以下称为‘下衬底’)11的三层结构组成，构成为将其各构成部中的半导体衬底3、5、7、9的电位通过在上衬底1的一部分上贯穿设置的通孔13、15、17、19分别引出到上衬底1的表面上的各键合焊盘部21。
上衬底1和下衬底11使用同面积的玻璃体，以通过该上衬底1和下衬底11可夹置多个半导体衬底3、5、7、9来配置。其中，在上衬底1的规定部位中，如上述那样贯穿设置通孔13、15、17、19。这样的通孔13、15、17、19例如在上衬底1上被一列地形成于直线状设定的电位提取区域23中。
在半导体衬底3、5、7、9中，第1半导体衬底3形成可包围平面观察四方形状的微型结构体的四边的外周框状形成的外周框部，被固定为接地(GND)电位，并且形成为相对于两玻璃板1、11没有位移的固定电极。这样，通过将形成外周框部的第1半导体衬底3作为固定电极，可以防止侧面方向的带电。
此外，在该第1半导体衬底3的一角部，在属于电位提取区域23的位置，平面观察有规定面积的矩形等的电位提取部31以平面观察可突出到内侧来形成。如图3所示，将该电位提取部31的面积设定为与后述的其他半导体衬底5、7、9的电位提取部36a、36b、40大致相同面积。
此外，第2及第3半导体衬底5、7都不接触第1半导体衬底3，以可被形成了该外周框状的第1半导体衬底3的内周包围来配置，分别是相对于两玻璃板1、11固定的固定电极。第2及第3半导体衬底5、7形成沿作为外周框部的第1半导体衬底3的内侧布线的基片33，以及从该基片33平面观察朝向内侧用于感应与第4半导体衬底9之间产生的静电电容变化的平面观察略梳齿状的固定侧电容感应元件35。而且，在第2及第3半导体衬底5、7的端部属于电位提取区域23的位置，形成平面观察有规定面积的矩形等的电位提取部36a、36b。
而且，第4半导体衬底9是相对于两玻璃板1、11可位移的可变电极，以可被外周框状形成的第1半导体衬底3的内周包围来配置，形成平面观察配置在中央部的干线部37，以及从该干线部37平面观察向两侧突出的用于感应与第2及第3半导体衬底5、7的固定侧电容感应元件35之间产生的静电电容变化的可变侧电容感应元件39。而且，在第4半导体衬底9的端部属于电位提取区域23的位置，形成平面观察有规定面积的矩形等的电位提取部40。
如图1所示，键合焊盘部21在相邻电位提取区域23并且上衬底1的平面观察端部中设定的连线区域(电位提取部)41内，分别一列配置在四个部位，如图1和图2所示，为填埋通孔13、15、17、19而涂敷形成的布线层43的一部分45在上衬底1上被延长，通过连接到键合焊盘部21，将各通孔13、15、17、19的各正下方的电位提取部31、36a、36b、40和键合焊盘部21电连接。再有，键合焊盘部21和布线层43用相同的金属膏或焊料等同时形成。
本实施方式的微型结构体如上述那样从各半导体衬底3、5、7、9的各通孔13、15、17、18的各正下方的电位提取部31、36a、36b、40中，用布线层43引出至上衬底1上的键合焊盘部21，所以如图2所示，通过在上衬底1上面的键合焊盘部21上连接键合线47，可以进行各半导体衬底3、5、7、9的电气提取。再有，标号48表示ASIC等的半导体集成电路。
这里，如果仅比较如上述那样在上衬底1上的键合焊盘部21上连接了键合线47的本实施方式的微型结构体(图2)和不形成键合焊盘部21而在通孔13、15、17、19正下方的电位提取部31、36a、36b、40上连接直接键合线47的情况(图6和图7)，则图6和图7的情况下，作为通孔13、15、17、19的尺寸，需要用于连接键合线47的焊头(毛细管；图示省略)进入的大尺寸，在减小芯片尺寸上有限制，但在图2所示的本实施方式中，可在上衬底1上面操作焊头(毛细管)来连接键合线47。因此，与图6和图7的情况(L2)相比，可以减小设定电位提取部31、36a、36b、40的直径(图2中的L1)，可以将芯片尺寸进一步小型化。
即，第1半导体衬底3的电位提取部31形成该半导体器件(微型结构体)的角部，并且包含该电位提取部31的该第1半导体衬底3的角部的面积设定为与其他半导体衬底5、7、9的电位提取部36a、36b、40的角部的面积大致相等，所以可以将芯片尺寸小型化。
再有，在本实施方式中，包含电位提取部31的该第1半导体衬底3的角部的面积设定为与其他半导体衬底5、7、9的电位提取部36a、36b、40的角部的面积大致相等，但这里除了包含角部的面积的大小关系是相同的以外，包含角部的面积的大小关系完全相同以外，还包含与其它半导体衬底5、7、9的电位提取部36a、36b、40的面积相比，包含电位提取部31的该第1半导体衬底3的角部的面积稍大的情况。
此外，在包含电位提取部31的该第1半导体衬底3的角部的面积比其它半导体衬底5、7、9的电位提取部36a、36b、40的面积小的情况下，也可获得同等的效果。
实施方式2
图8是表示本发明实施方式2的省略了半导体器件(微型结构体)的上衬底状态的平面图。再有，在图8中对具有与实施方式1同样功能的主要元件附以同一标号。
如图8所示，本实施方式的微型结构体的其基本结构与实施方式1的微型结构体相同，成为外周框部的第1半导体衬底(硅体)3的电位提取部31形成在微型结构体的一直线状设定的电位提取区域23内的角部。
这里，在实施方式1中，该电位提取部31以从作为外周框部的第1半导体衬底3的框部平面观察向内侧突出来形成，如图3那样，特别是该突出的电位提取部31的面积与其他半导体衬底(硅体)5、7、9的电位提取部36a、36b、40大致为相同面积，所以包含该电位提取部31的第1半导体衬底3的角部的面积比其他半导体衬底5、7、9的电位提取部36a、36b、40大。
相反，在本实施方式中，将从外周框状形成的作为外周框部的第1半导体衬底3中作为电位提取部31向内侧突出的部分的面积设定得比其他半导体衬底5、7、9的电位提取部36a、36b、40小，由此，将包含电位提取部31的第1半导体衬底3的角部的面积设定为大致与其他半导体衬底5、7、9的电位提取部36a、36b、40相同的面积。
如图8那样，在第1半导体衬底3的一角部上形成电位提取部31，将包含该电位提取部31的第1半导体衬底3的一角部的面积设定为大致与其他半导体衬底5、7、9的电位提取部36a、36b、40相同的面积，所以例如图9那样，与在除了第1半导体衬底3的角部以外的中间位置形成电位提取部31的情况相比，可以将芯片尺寸小型化。
具体地说，考虑从该微型结构体的端部位置至第2电位提取区域的距离L3(图8)、L4(图9)。在图9中，第2半导体衬底5的电位提取部36a位于微型结构体的角部附近，所以需要将该电位提取部36a和第1半导体衬底3间隔配置。因此，从该微型结构体的端部位置至包含第2电位提取部31的长度为L4。相反，在图8中，在第1半导体衬底3的一角部中引入形成电位提取部31，将包含该电位提取部31的第1半导体衬底3的一角部的面积设定为大致与其他半导体衬底5、7、9的电位提取部36a、36b、40相同的面积，所以从该微型结构体的端部位置至包含第2电位提取部36a的长度为比L4小的L3。因此，根据本实施方式，与图9所示的情况相比，可以将芯片尺寸进一步小型化。
实施方式3
图10是表示本发明实施方式3的省略了半导体器件(微型结构体)的上衬底状态的平面图。再有，在图10中对具有与实施方式1和实施方式2同样功能的主要元件附以同一标号。
在上述实施方式2中，相对于将成为外周框部的第1半导体衬底(硅体)3的电位提取部31形成在微型结构体的一直线状设定的电位提取区域23内的角部，在本实施方式3中，将成为外周框部的第1半导体衬底3的电位提取部31不是配置在面对其他半导体衬底(硅体)5、7、9的电位提取部36a、36b、40直线上的位置，而是在微型结构体的划片线上(即切断分割的线上)配设在任意的角部。这样，如果将第1半导体衬底3的电位提取部31跨越配设在微型结构体的划片线上的角部，则在切断划片线时，第1半导体衬底3的电位提取部31被配设在微型结构体的周边部。由此，避开半导体衬底5、7、9比较密集的部分，可以在该半导体衬底5、7、9不密集的区域中配置第1半导体衬底3的电位提取部31，所以进行作为整体密度的正常化，可以减小芯片尺寸。
再有，如果形成这样的结构，仅第1半导体衬底3的电位提取部31孤立配置在比其他半导体衬底5、7、9的电位提取部36a、36b、40远的位置，但如果考虑连接键合线47的多个键合焊盘部21的其连接作业的自动化等的方便，则与实施方式1和实施方式2同样，期望如图11那样一直线状地靠近配置。因此，从孤立配置的第1半导体衬底3的电位提取部31至其键合焊盘部21(21a)的布线层49比从其他半导体衬底5、7、9的电位提取部36a、36b、40至其键合焊盘部21的布线层43更长地形成。
此外，在实施方式2中，相对于将包含第1半导体衬底3的电位提取部31的该半导体衬底3的一角部的面积设定为大致与其他半导体衬底5、7、9的电位提取部36a、36b、40相同面积，在本实施方式3中，通过将电位提取部31跨越设定在划片线上，在切断该划片线后，电位提取部31被配设在微型结构体的周边部，与其他半导体衬底5、7、9的电位提取部36a、36b、40相比，可以将包含该电位提取部31的该第1半导体衬底3的一角部的面积设定得小。因此，根据本实施方式，与实施方式2相比，可以将芯片尺寸进一步小型化。
再有，第1半导体衬底3的电位提取部31的位置不限于图10所示的位置。例如，如图12所示，位于跨越微型结构体的划片线上的位置，配置在实施方式2中说明的靠近第1半导体衬底3的电位提取部31的位置，但电位提取部31的面积仅限定于作为半导体衬底3的外周框部的宽度就可以。这种情况下，即使通孔13以跨越突出第1半导体衬底3的划片线上的角端部而形成也没有问题。
或者，如图13那样，将第1半导体衬底3的电位提取部31的位置配置在图10所示的跨越位置靠近的划片线上的位置，即使将通孔13跨越突出第1半导体衬底3的划片线的角端部而形成也没有问题。
而且，上衬底1的布线层43、49的形状不限于图11所示的形状，例如图14那样，不用说，可用各种形状布线图形化的布线层49将键合焊盘部21配置在期望的位置。
实施方式4
图15表示本发明实施方式4的半导体器件(微型结构体)。再有，在图15中对与实施方式1～实施方式3具有同样功能的主要元件附以相同标号。
本实施方式的微型结构体如图15所示，从接地(GND)电位的第1半导体衬底(硅体)3引出至键合焊盘部21的布线层43，在上衬底1的表面上，被连接到在电位提取区域23和连接区域(电位提取部)41以外的区域(以下称为‘屏蔽区域’)中延伸的导电层51，将上衬底1的导电层51的表面电位固定为接地电位。
通过形成这样的导电层51，可以实现不因靠近其他物质、静电等和电波干扰等外部干扰而产生电容变化的高性能的制品。
再有，各布线层43、49和导电层51的形状不限于图15的形状，例如也可以形成如图16那样的图形。
此外，导电层51的电位不限定于接地(GND)电位，也可以设定为规定的固定电位。
实施方式5
图17是表示使用本发明实施方式5的微型结构体的半导体器件的侧面剖面图。再有，在图17中对与实施方式1～实施方式4具有同样功能的主要元件附以相同标号。
本实施方式的半导体器件如图17所示，将微型结构体53的下衬底11的下表面通过规定的导电部件55粘结(进行管芯键合)在管芯焊盘57的上面。
导电部件55采用将银等的金属混入在环氧树脂等的树脂材料中的导电性树脂，或焊料或Au-Si共晶性的金属等。
管芯焊盘57可以是使用规定的金属材料的导电板。该管芯焊盘57的电位被固定为接地电位或固定的电压。具体地说，该管芯焊盘57的电位通过图18所示的内部引线59连接到外部引线61或ASIC等的半导体元件63等。
再有，标号60表示由环氧树脂等的绝缘性树脂形成的绝缘模塑体。
由此，与使用绝缘体将微型结构体53管芯键合在管芯焊盘57的情况相比，在微型结构体53的下表面侧，可以实现不因靠近其他物质、静电等和电波干扰等外部干扰而产生电容变化的高性能的制品。
此外，如图17所示，在相邻配置的半导体元件63的背面，通过用同样的导电部件55实施金属喷镀，可以使微型结构体53的下衬底11下面的管芯焊盘57的电位与半导体元件63的衬底下面的电位相同。因此，可以与半导体元件63一起实现不因靠近其他物质、静电等和电波干扰等外部干扰而产生电容变化的高性能的制品。
再有，在图18中，将管芯焊盘57的电位用内部引线59引出到外部，除此以外，如图19所示，在管芯焊盘57的规定部位连接键合线65，通过该键合线65将管芯焊盘57的电位引出到外部也没有问题。
实施方式6
图20是表示使用本发明实施方式6的微型结构体的半导体器件的侧面剖面图。再有，在图20中对与实施方式1～实施方式5具有同样功能的主要元件附以相同标号。
本实施方式的半导体器件有在信号处理电路用的ASIC等的半导体元件71的上面叠层搭载微型结构体73的叠层结构，在叠层半导体元件71的微型结构体73的表面区域中形成导电层75，通过该导电层75上面形成的导电部件77，管芯键合微型结构体73。
这里，半导体元件71的导电层75的电位被固定为接地电位或固定的电压。
导电部件77采用将银等的金属混入在环氧树脂等的树脂材料中的导电性树脂，或焊料或Au-Si共晶性的金属等。
通过这样的结构，与实施方式5同样，在微型结构体73的下衬底11侧，可以实现不因靠近其他物质、静电等和电波干扰等外部干扰而产生电容变化的高性能的制品。
实施方式7
图21是表示使用本发明实施方式7的微型结构体的半导体器件的侧面剖面图。再有，在图21中对与实施方式1～实施方式6具有同样功能的主要元件附以相同标号。
本实施方式的半导体器件在管芯焊盘57上搭载微型结构体83，而且在微型结构体83的上衬底1的上面，叠层搭载信号处理电路用的ASIC等的半导体元件81，形成叠层结构，微型结构体83的上衬底1通过导电部件85粘结在半导体元件81上。该导电部件85采用将银等的金属混入在环氧树脂等的树脂材料中的导电性树脂，或焊料或Au-Si共晶性的金属等。
而且，该半导体元件81的导电性的衬底85的电位被固定为接地电位或固定电压。
根据这样的结构，可以固定微型结构体83的下衬底11的下面的电位，可以获得与实施方式5同样的效果。
实施方式8
图22是表示本发明实施方式8的微型结构体的平面图，图23是图22的XXIII-XXIII剖面图。再有，在图22和图23中对与实施方式1～实施方式7具有同样功能的主要元件附以相同标号。
本实施方式的微型结构体与实施方式1～实施方式3同样，在相互平行配置的上衬底1和下衬底11之间，分别配有作为固定电极和可变电极的半导体衬底(硅体)3、5、7、9，在一部分上衬底1中形成通孔13、15、17、19，通过从这些通孔13、15、17、19在上衬底1的表面中形成的布线层43，各半导体衬底3、5、7、9的电位提取部31、36a、36b、41与上衬底1上的键合焊盘部21电连接。
而且，还在这样形成了布线层43的状态的上衬底1的上层，形成绝缘膜91。绝缘膜91使用低温下可叠层形成的氮化膜或聚酰亚胺等。
而且，在从被固定为接地(GND)电位的第1半导体衬底3通过通孔13引出的布线层43的中间位置所对应的位置，在绝缘膜91中贯通设置布线引出孔93。在该布线引出孔93中，填充涂敷形成导电体95，它采用将银等的金属混入环氧树脂等的树脂材料中的导电性树脂、或焊料或Au-Si共晶性的金属等，通过该导电体95，将第1半导体衬底3的电位(接地电位)引出到绝缘膜91的上面侧。
而且，在绝缘膜91的上面，连接上述接地电位的导电体95，形成防止因靠近其他物质、静电等和电波干扰等的外部干扰造成的电容变化的导电层97。该导电层97覆盖布线层43的大部分，形成在期望的屏蔽区域。
根据这样的结构，可以将还包含布线层43的微型结构体上方的电位固定为接地电位，可以实现不因靠近其他物质、静电等和电波干扰等外部干扰而产生电容变化的高性能的制品。
再有，在本实施方式中，将第1半导体衬底3作为接地电位，所以屏蔽区域中形成的导电层97也为接地电位，但不用说，即使将第1半导体衬底3固定为接地电位以外的规定的固定电位，将导电层97固定为该电位，也可获得同样的效果。
实施方式9
图24是表示使用本发明实施方式9的微型结构体的半导体器件的侧面剖面图。再有，在图24中对与实施方式5具有同样功能的主要部件附以相同标号。
本实施方式的半导体器件如图24所示，在将微型结构体53的下衬底11的背面通过规定的导电部件55粘结在导电性的管芯焊盘57的表面上与实施方式5相同。
导电部件55与实施方式5同样，采用将银等的金属混入在环氧树脂等的树脂材料中的导电性树脂、或焊料或Au-Si共晶性的金属等。
此外，管芯焊盘57也与实施方式5同样，是使用规定的金属材料的导电板，该管芯焊盘57的电位被固定为接地电位或固定的电压。
再有，图24中的标号63表示ASIC等的半导体元件。
而且，如图24所示，在本实施方式中，微型结构体53与图17所示的实施方式5的微型结构体53上下相反地设置，而且，用于连接外部引线61和半导体元件63的键合线107等的所有电路将两部件63、61的下侧之间进行引线键合等而形成，所以所有的电路以所谓反向弯曲方式来安装。由此，所有的电路、微型结构体53和半导体元件63的上方通过导电性的管芯焊盘57来屏蔽。
这样，通过被固定为接地电位或固定电压的管芯焊盘57，可以防止因靠近其他物质、静电等和电波干扰等的外部干扰造成的电容变化。
此外，在本实施方式中，在面对安装该半导体器件102的安装衬底103的半导体器件102的表面上，形成导电层105，通过该导电层105，可以防止下方向其他物质的靠近、静电等或电波干扰等的外部干扰造成的电容变化。
由此，可在上下两方向上防止其他物质的靠近、静电等或电波干扰等的外部干扰造成的电容变化，可以实现高性能的制品。
根据本发明，多个半导体衬底中的一半导体衬底以可包围在上衬底和下衬底之间被夹置的区域周边的外周框状来形成，多个半导体衬底中的其他半导体衬底以可被外周框状形成的一半导体衬底的内周包围来配置，将一半导体衬底的电位提取部形成在角部，并且将包含该电位提取部的对应的一半导体衬底的角部的面积设定为与其他半导体衬底的电位提取部的面积大致相同或在其以下，所以可以将芯片尺寸小型化。
此外，在上衬底的表面上，形成导电层等，其被固定为包含接地电位的规定的固定电压，使各半导体衬底屏蔽来自其他物质的靠近、静电等或电波干扰等的外部干扰，所以可以提供外部干扰的影响造成的静电电容变化小的半导体器件。

Claims (9)

1.一种半导体器件，包括：
形成了多个通孔的上衬底；
下衬底；以及
多个半导体衬底，被夹置在所述上衬底和所述下衬底之间来形成固定电极和可变电极，同时分别在所述通孔中形成用于提取期望电位的电位提取部；
其中，多个所述半导体衬底中的一个半导体衬底形成为外周框状，以包围在所述上衬底和所述下衬底之间被夹置的区域的周边，
多个所述半导体衬底中的其他半导体衬底配置成被形成为外周框状的所述一个半导体衬底的内周所包围，
所述一个半导体衬底的所述电位提取部形成在角部，并且包含该电位提取部的该一个半导体衬底的所述角部的面积小于等于所述其他半导体衬底的所述电位提取部的面积。
2.如权利要求1所述的半导体器件，其中，
还包括形成于所述上衬底表面上的多个键合焊盘部，以便把从所述各半导体衬底的所述电位提取部分别通过所述各通孔导出到所述上衬底上的电位引出到键合线。
3.如权利要求1所述的半导体器件，其中，
所述一个半导体衬底的所述电位提取部配置在不与所述其他半导体衬底的所述电位提取部位于同一条直线上的角部。
4.如权利要求1所述的半导体器件，其中，
在所述上衬底的表面上形成有导电层，该导电层被固定为包括接地电位在内的规定的固定电压，对所述各半导体衬底进行屏蔽，以使其免受来自其他物质的靠近、静电或电波干扰这些外部干扰。
5.如权利要求1所述的半导体器件，其中，
将所述一个半导体衬底固定为包括接地电位在内的规定的固定电位。
6.如权利要求4所述的半导体器件，其中，
将所述一个半导体衬底固定为包括接地电位在内的规定的固定电位，
通过连接到所述一个半导体衬底，将所述导电层固定为所述固定电位。
7.如权利要求1所述的半导体器件，其中，
所述下衬底的背面通过规定的导电部件管芯键合在导电性管芯焊盘上。
8.如权利要求1所述的半导体器件，其中，
在所述上衬底的表面上，叠层搭载用于信号处理的半导体元件，
在所述上衬底的表面上接合的所述半导体元件的衬底被固定为包括接地电位在内的规定的固定电位。
9.如权利要求2所述的半导体器件，其中，还包括：
在所述上衬底的表面上布线成连接从所述各通孔到所述各键合焊盘部的布线层；
覆盖在布线有该布线层的所述上衬底的表面上的绝缘膜；以及
形成在所述绝缘膜的上层中的导电层，该导电层被固定为包括接地电位在内的规定的固定电压，对所述各半导体衬底和所述布线层进行屏蔽，以使其免受来自其他物质的靠近、静电或电波干扰这些外部干扰。
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JP2008304218A (ja) * 2007-06-05 2008-12-18 Mitsubishi Electric Corp 加速度センサおよびその製造方法
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JP5708235B2 (ja) * 2011-05-18 2015-04-30 大日本印刷株式会社 Ｍｅｍｓデバイス
JP6413462B2 (ja) * 2014-08-15 2018-10-31 セイコーエプソン株式会社 物理量センサー、物理量センサー装置、電子機器および移動体
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JP2005038911A (ja) 2005-02-10
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KR100576302B1 (ko) 2006-05-03
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